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authorRanjani Vaidyanathan <ra5478@freescale.com>2012-02-07 14:34:13 -0600
committerJason Liu <r64343@freescale.com>2012-07-20 13:36:15 +0800
commite49e91034281133c9871a9fe6a1ed2864a947765 (patch)
tree3dab4075e6c6807d9cc2d03307ad4e77cf2d30d9 /arch/arm/mach-mx6/devices-imx6q.h
parent6079ec044048b2f50f53a22c48df84e123d24535 (diff)
ENGR00179574: MX6- Add bus frequency scaling support
Add support for scaling the bus frequency (both DDR and ahb_clk). The DDR and AHB_CLK are dropped to 24MHz when all devices that need high AHB frequency are disabled and the CORE frequency is at the lowest setpoint. The DDR is dropped to 400MHz for the video playback usecase. In this mode the GPU, FEC, SATA etc are disabled. To scale the bus frequency, its necessary that all cores except the core that is executing the DDR frequency change are in WFE. This is achieved by generating interrupts on un-used interrupts (Int no 139, 144, 145 and 146). Signed-off-by: Ranjani Vaidyanathan <ra5478@freescale.com>
Diffstat (limited to 'arch/arm/mach-mx6/devices-imx6q.h')
-rw-r--r--arch/arm/mach-mx6/devices-imx6q.h3
1 files changed, 3 insertions, 0 deletions
diff --git a/arch/arm/mach-mx6/devices-imx6q.h b/arch/arm/mach-mx6/devices-imx6q.h
index df5e72cc7910..2c3e0c53ac06 100644
--- a/arch/arm/mach-mx6/devices-imx6q.h
+++ b/arch/arm/mach-mx6/devices-imx6q.h
@@ -213,3 +213,6 @@ extern const struct imx_vdoa_data imx6q_vdoa_data __initconst;
extern const struct imx_pcie_data imx6q_pcie_data __initconst;
#define imx6q_add_pcie(pdata) imx_add_pcie(&imx6q_pcie_data, pdata)
+
+#define imx6q_add_busfreq(pdata) imx_add_busfreq(pdata)
+