diff options
| author | Ranjani Vaidyanathan <ra5478@freescale.com> | 2012-04-26 17:53:14 -0500 |
|---|---|---|
| committer | Ranjani Vaidyanathan <ra5478@freescale.com> | 2012-05-04 12:07:10 -0500 |
| commit | 63f88588fe7ebc06039cf7346a653a49d66e532c (patch) | |
| tree | b7cb042bf53d950d7178da9533d209e12403859c /arch/arm/mach-mx6/mx6_mmdc.c | |
| parent | 3a227e2db36aa075eb7534fa5d83ae17011a57dc (diff) | |
ENGR00181068: MX6 Source IPU_HSP and AXI clocks from 540M PFD.
IPU_HSP clocks should NOT be sourced from MMDC clock since the
MMDC clock can be scaled.
Move the IPU_HSP clock to be sourced from PLL3_PFD_540M instead.
Also don't source AXI_CLK from periph_clk as this domain is
scaled between 528MHz, 400MHz and 24MHz. Move AXI_CLK
clock to be sourced from PLL3_PFD_540M too.
When the system needs to enter low power mode, AXI_CLK is switched
from PLL3_PFD_540M to periph_clk. And then switched back
when low power mode is exited.
The code will print a warning message if PLL3_PFD_540M is
relocked to a different frequency when IPU_HSP or axi_clk is
sourced from it.
Currently remove the support for 400Mhz DDR working point for
MX6Q since we can get IPU underruns during the DDR frequency
transitions.
The DDR freq change code needs to ensure that all bus clocks
donot exceed max frequency during the frequency transition.
Signed-off-by: Ranjani Vaidyanathan <ra5478@freescale.com>
Diffstat (limited to 'arch/arm/mach-mx6/mx6_mmdc.c')
| -rw-r--r-- | arch/arm/mach-mx6/mx6_mmdc.c | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/arch/arm/mach-mx6/mx6_mmdc.c b/arch/arm/mach-mx6/mx6_mmdc.c index 2498f01e0889..c4f232f0e56d 100644 --- a/arch/arm/mach-mx6/mx6_mmdc.c +++ b/arch/arm/mach-mx6/mx6_mmdc.c @@ -227,7 +227,6 @@ int update_ddr_freq(int ddr_rate) /* Set the interrupt to be pending in the GIC. */ reg = 1 << (irq_used[cpu] % 32); writel_relaxed(reg, gic_dist_base + GIC_DIST_PENDING_SET + (irq_used[cpu] / 32) * 4); - udelay(10); } } while (cpus_in_wfe != online_cpus) @@ -343,6 +342,8 @@ int init_mmdc_settings(void) memcpy(ddr_freq_change_iram_base, mx6_ddr_freq_change, SZ_8K); mx6_change_ddr_freq = (void *)ddr_freq_change_iram_base; + curr_ddr_rate = ddr_normal_rate; + for_each_online_cpu(cpu) { /* Set up a reserved interrupt to get all the active cores into a WFE state * before changing the DDR frequency. |