diff options
| author | Anson Huang <b20788@freescale.com> | 2011-08-02 17:24:15 +0800 |
|---|---|---|
| committer | Jason Liu <r64343@freescale.com> | 2012-07-20 13:15:10 +0800 |
| commit | 2830baec62492050b35a1c150a611bb1adc510eb (patch) | |
| tree | 7b1a5a6372a77b61a5b3cfd177f86fd6d3fc7180 /arch/arm/mach-mx6/system.c | |
| parent | 0429bc217a19c1a77022049929df95b32962e0be (diff) | |
ENGR00154056-2 [MX6]Enable dormant mode in suspend
1. Enable dormant mode in suspend, which means arm
core will be powered off when enter wfi, the latest
command for stop mode and dormant mode are as below:
echo standby > /sys/power/state
-> stop mode with arm core power on
echo mem > /sys/power/state
-> stop mode with arm core power off
2. Remove all iram related code in suspend.
Signed-off-by: Anson Huang <b20788@freescale.com>
Diffstat (limited to 'arch/arm/mach-mx6/system.c')
| -rw-r--r-- | arch/arm/mach-mx6/system.c | 25 |
1 files changed, 20 insertions, 5 deletions
diff --git a/arch/arm/mach-mx6/system.c b/arch/arm/mach-mx6/system.c index eb22241a6848..0737207c54b0 100644 --- a/arch/arm/mach-mx6/system.c +++ b/arch/arm/mach-mx6/system.c @@ -33,6 +33,9 @@ #define SCU_CPU_STATUS 0x08 #define SCU_INVALIDATE 0x0c #define SCU_FPGA_REVISION 0x10 +#define GPC_PGC_CPU_PDN_OFFSET 0x2a0 +#define GPC_PGC_CPU_PUPSCR_OFFSET 0x2a4 +#define GPC_PGC_CPU_PDNSCR_OFFSET 0x2a8 extern unsigned int gpc_wake_irq[4]; @@ -65,19 +68,28 @@ void mxc_cpu_lp_set(enum mxc_cpu_pwr_mode mode) break; case WAIT_UNCLOCKED_POWER_OFF: case STOP_POWER_OFF: + case ARM_POWER_OFF: if (mode == WAIT_UNCLOCKED_POWER_OFF) { ccm_clpcr |= 0x1 << MXC_CCM_CLPCR_LPM_OFFSET; ccm_clpcr &= ~MXC_CCM_CLPCR_VSTBY; ccm_clpcr &= ~MXC_CCM_CLPCR_SBYOS; stop_mode = 0; - } else { + } else if (mode == STOP_POWER_OFF) { ccm_clpcr |= 0x2 << MXC_CCM_CLPCR_LPM_OFFSET; ccm_clpcr |= 0x3 << MXC_CCM_CLPCR_STBY_COUNT_OFFSET; ccm_clpcr |= MXC_CCM_CLPCR_VSTBY; ccm_clpcr |= MXC_CCM_CLPCR_SBYOS; ccm_clpcr |= MXC_CCM_CLPCR_BYP_MMDC_CH1_LPM_HS; stop_mode = 1; + } else { + ccm_clpcr |= 0x2 << MXC_CCM_CLPCR_LPM_OFFSET; + ccm_clpcr |= 0x3 << MXC_CCM_CLPCR_STBY_COUNT_OFFSET; + ccm_clpcr |= MXC_CCM_CLPCR_VSTBY; + ccm_clpcr |= MXC_CCM_CLPCR_SBYOS; + ccm_clpcr |= MXC_CCM_CLPCR_BYP_MMDC_CH1_LPM_HS; + stop_mode = 2; } + /* scu standby enable, scu clk will be * off after all cpu enter WFI */ scu_cr |= 0x20; @@ -90,12 +102,15 @@ void mxc_cpu_lp_set(enum mxc_cpu_pwr_mode mode) return; } - if (stop_mode == 1) { - + if (stop_mode > 0) { gpc_set_wakeup(gpc_wake_irq); /* Power down and power up sequence */ - __raw_writel(0xFFFFFFFF, gpc_base + 0x2a4); - __raw_writel(0xFFFFFFFF, gpc_base + 0x2a8); + __raw_writel(0xFFFFFFFF, gpc_base + GPC_PGC_CPU_PUPSCR_OFFSET); + __raw_writel(0xFFFFFFFF, gpc_base + GPC_PGC_CPU_PDNSCR_OFFSET); + + /* dormant mode, need to power off the arm core */ + if (stop_mode == 2) + __raw_writel(0x1, gpc_base + GPC_PGC_CPU_PDN_OFFSET); } __raw_writel(scu_cr, scu_base + SCU_CTRL); |