diff options
| author | Ranjani Vaidyanathan <ra5478@freescale.com> | 2012-02-23 12:19:23 -0600 |
|---|---|---|
| committer | Jason Liu <r64343@freescale.com> | 2012-07-20 13:36:14 +0800 |
| commit | 6079ec044048b2f50f53a22c48df84e123d24535 (patch) | |
| tree | 480beceda4a6df20bcc214159996bcf3192d923b /arch/arm/mach-mx6/system.c | |
| parent | 19bd2e51bfd7883a5ff3ecd1cf419d5d0d1c752f (diff) | |
ENGR00179582 MX6: Bypass PLL1 during WAIT
When system is going to enter WAIT mode, set PLL1 to 24MHz
so that ARM is running at 24MHz. This is a SW workaround for
the WAIT mode issue.
Signed-off-by: Ranjani Vaidyanathan <ra5478@freescale.com>
Diffstat (limited to 'arch/arm/mach-mx6/system.c')
| -rw-r--r-- | arch/arm/mach-mx6/system.c | 18 |
1 files changed, 7 insertions, 11 deletions
diff --git a/arch/arm/mach-mx6/system.c b/arch/arm/mach-mx6/system.c index 0eb6592969dd..8210f9a93830 100644 --- a/arch/arm/mach-mx6/system.c +++ b/arch/arm/mach-mx6/system.c @@ -49,9 +49,10 @@ extern int mx6q_revision(void); static void __iomem *gpc_base = IO_ADDRESS(GPC_BASE_ADDR); -extern void (*mx6_wait_in_iram)(void); -extern void mx6_wait(void); -extern void *mx6_wait_in_iram_base; +volatile unsigned int num_cpu_idle; +volatile unsigned int num_cpu_idle_lock = 0x0; + +extern void mx6_wait(void *num_cpu_idle_lock, void *num_cpu_idle); extern bool enable_wait_mode; void gpc_set_wakeup(unsigned int irq[4]) @@ -159,14 +160,9 @@ void mxc_cpu_lp_set(enum mxc_cpu_pwr_mode mode) void arch_idle(void) { if (enable_wait_mode) { - if ((num_online_cpus() == num_present_cpus()) - && mx6_wait_in_iram != NULL) { - mxc_cpu_lp_set(WAIT_UNCLOCKED_POWER_OFF); - if (smp_processor_id() == 0) - mx6_wait_in_iram(); - else - cpu_do_idle(); - } + *((char *)(&num_cpu_idle_lock) + smp_processor_id()) = 0x0; + mxc_cpu_lp_set(WAIT_UNCLOCKED_POWER_OFF); + mx6_wait((void *)&num_cpu_idle_lock, (void *)&num_cpu_idle); } else cpu_do_idle(); } |