diff options
| author | Anson Huang <b20788@freescale.com> | 2012-08-30 03:10:07 +0800 |
|---|---|---|
| committer | Anson Huang <b20788@freescale.com> | 2012-08-30 03:29:20 +0800 |
| commit | 9f654ff1ecd99a8171dc739e8f8474d8390a0978 (patch) | |
| tree | 52dd09f870f9a7b7dc921e303dbdf72d042ddf6d /arch/arm/mach-mx6/system.c | |
| parent | 3052b56745ce89d440c106922a7015d8bf11627c (diff) | |
ENGR00221902 [MX6]Fix udelay inaccurate issue during suspend/resume
When system enter suspend, we increase CPUFreq to the highest point
without update the global loops_per_jiffy, it will lead to udelay
inaccurate during the last phase of suspend/resume.
WB counter and RBC counter need at least two 32K cycles to finish,
here we add 80us for safe.
Signed-off-by: Anson Huang <b20788@freescale.com>
Diffstat (limited to 'arch/arm/mach-mx6/system.c')
| -rw-r--r-- | arch/arm/mach-mx6/system.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/arm/mach-mx6/system.c b/arch/arm/mach-mx6/system.c index 686c58c1e0e5..800c7cc4e8bd 100644 --- a/arch/arm/mach-mx6/system.c +++ b/arch/arm/mach-mx6/system.c @@ -195,7 +195,7 @@ void mxc_cpu_lp_set(enum mxc_cpu_pwr_mode mode) __raw_writel(__raw_readl(MXC_CCM_CCR) & (~MXC_CCM_CCR_WB_COUNT_MASK) & (~MXC_CCM_CCR_REG_BYPASS_CNT_MASK), MXC_CCM_CCR); - udelay(60); + udelay(80); /* Reconfigurate WB and RBC counter */ __raw_writel(__raw_readl(MXC_CCM_CCR) | (0x1 << MXC_CCM_CCR_WB_COUNT_OFFSET) | |