diff options
| author | Robby Cai <R63905@freescale.com> | 2012-07-06 17:51:13 +0800 |
|---|---|---|
| committer | Terry Lv <r65388@freescale.com> | 2012-07-25 13:10:36 +0800 |
| commit | f86a8329318fd6374c30a8a340ac8b81db100dfc (patch) | |
| tree | 5d17dc57c96c651d340b177d08c8b4d8f5c7dfb4 /arch/arm/mach-mx6/system.c | |
| parent | 473ad2b1fa2c1441db562a58859be5a7eb18ce93 (diff) | |
ENGR00216010-1: gpc: Add missing display_pup_req config after system resumes
There's only DISPLAY power down request setting before system suspends,
but without the paired DISPLAY power up request setting after resume.
This will cause ePxP/EPDC/SPDC module nonfunctional because the modules
will be powered down once pdn_req is asserted but not powered up again.
With this patch, ePxP/EPDC/SPDC survived (need reinitialize each, however)
on resume.
Signed-off-by: Robby Cai <R63905@freescale.com>
Diffstat (limited to 'arch/arm/mach-mx6/system.c')
| -rw-r--r-- | arch/arm/mach-mx6/system.c | 5 |
1 files changed, 0 insertions, 5 deletions
diff --git a/arch/arm/mach-mx6/system.c b/arch/arm/mach-mx6/system.c index 943b757997d6..b9efbb64c8f9 100644 --- a/arch/arm/mach-mx6/system.c +++ b/arch/arm/mach-mx6/system.c @@ -39,7 +39,6 @@ #define SCU_INVALIDATE 0x0c #define SCU_FPGA_REVISION 0x10 #define GPC_CNTR_OFFSET 0x0 -#define GPC_PGC_DISP_PGCR_OFFSET 0x240 #define GPC_PGC_GPU_PGCR_OFFSET 0x260 #define GPC_PGC_CPU_PDN_OFFSET 0x2a0 #define GPC_PGC_CPU_PUPSCR_OFFSET 0x2a4 @@ -149,10 +148,6 @@ void mxc_cpu_lp_set(enum mxc_cpu_pwr_mode mode) __raw_writel(0x1, gpc_base + GPC_PGC_CPU_PDN_OFFSET); __raw_writel(0x1, gpc_base + GPC_PGC_GPU_PGCR_OFFSET); __raw_writel(0x1, gpc_base + GPC_CNTR_OFFSET); - if (cpu_is_mx6sl()) { - __raw_writel(0x1, gpc_base + GPC_PGC_DISP_PGCR_OFFSET); - __raw_writel(0x10, gpc_base + GPC_CNTR_OFFSET); - } if (cpu_is_mx6q() || cpu_is_mx6dl()) { /* Enable weak 2P5 linear regulator */ anatop_val = __raw_readl(anatop_base + |