ENGR00268893 mx6q/sdl clock:Correct emi_clk set/get rate in aclk_podf

The read/write values of aclk_podf[20:22] field in register 'CCM Serial
Clock Multiplexer Register 1' do not match with each other. The read/
write/divider values have the relationship described by the following
table:
============================================================
write value       read value        description
3b'000            3b'110            divided by 7
3b'001            3b'111            divided by 8
3b'010            3b'100            divided by 5
3b'011            3b'101            divided by 6
3b'100            3b'010            divided by 3
3b'101            3b'011            divided by 4
3b'110            3b'000            divided by 1
3b'111            3b'001            divided by 2(default)
============================================================

This patch corrects the emi_clk set/get rate functions according to
the above table. On i.MX6Q, emi_clk is used by MIPI CSI2 module as
ccm_pixel_clk, while on i.MX6SDL, it is not used by any module.
The patch may resolve the 1080P30 MIPI camera preview blur issue
indirectly by increasing ccm_pixel_clk for i.MX6Q.

Signed-off-by: Liu Ying <Ying.Liu@freescale.com>

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