Merge remote branch 'fsl-linux-sdk/imx_3.0.35' into imx_3.0.35_android

Conflicts:
	arch/arm/configs/imx6_defconfig
	arch/arm/configs/imx6_updater_defconfig
	arch/arm/configs/imx6s_defconfig
	arch/arm/include/asm/dma-mapping.h
	arch/arm/kernel/smp.c
	arch/arm/mach-mx6/Kconfig
	arch/arm/mach-mx6/board-mx6dl_arm2.h
	arch/arm/mach-mx6/board-mx6dl_sabresd.h
	arch/arm/mach-mx6/board-mx6q_arm2.c
	arch/arm/mach-mx6/board-mx6q_arm2.h
	arch/arm/mach-mx6/board-mx6q_sabreauto.c
	arch/arm/mach-mx6/board-mx6q_sabreauto.h
	arch/arm/mach-mx6/board-mx6q_sabrelite.c
	arch/arm/mach-mx6/board-mx6q_sabresd.c
	arch/arm/mach-mx6/board-mx6q_sabresd.h
	arch/arm/mach-mx6/board-mx6sl_arm2.c
	arch/arm/mach-mx6/board-mx6sl_arm2.h
	arch/arm/mach-mx6/board-mx6solo_sabreauto.h
	arch/arm/mach-mx6/bus_freq.c
	arch/arm/mach-mx6/clock.c
	arch/arm/mach-mx6/clock_mx6sl.c
	arch/arm/mach-mx6/cpu.c
	arch/arm/mach-mx6/crm_regs.h
	arch/arm/mach-mx6/devices-imx6q.h
	arch/arm/mach-mx6/devices.c
	arch/arm/mach-mx6/mx6_anatop_regulator.c
	arch/arm/mach-mx6/pcie.c
	arch/arm/mach-mx6/system.c
	arch/arm/mm/dma-mapping.c
	arch/arm/plat-mxc/devices/Makefile
	arch/arm/plat-mxc/devices/platform-imx-dcp.c
	arch/arm/plat-mxc/devices/platform-imx-ocotp.c
	arch/arm/plat-mxc/devices/platform-imx-rngb.c
	arch/arm/plat-mxc/devices/platform-mxc_hdmi.c
	arch/arm/plat-mxc/include/mach/devices-common.h
	arch/arm/plat-mxc/include/mach/esdhc.h
	arch/arm/plat-mxc/include/mach/iomux-mx6dl.h
	arch/arm/plat-mxc/include/mach/iomux-mx6q.h
	arch/arm/plat-mxc/include/mach/memory.h
	arch/arm/plat-mxc/include/mach/mx6.h
	arch/arm/plat-mxc/include/mach/mxc_edid.h
	arch/arm/plat-mxc/include/mach/mxc_hdmi.h
	arch/arm/plat-mxc/system.c
	drivers/Kconfig
	drivers/char/hw_random/fsl-rngc.c
	drivers/cpufreq/Makefile
	drivers/cpufreq/cpufreq_interactive.c
	drivers/crypto/Kconfig
	drivers/crypto/caam/caamalg.c
	drivers/crypto/caam/compat.h
	drivers/crypto/caam/ctrl.c
	drivers/crypto/caam/desc_constr.h
	drivers/crypto/caam/intern.h
	drivers/crypto/dcp.c
	drivers/dma/pch_dma.c
	drivers/input/keyboard/gpio_keys.c
	drivers/input/touchscreen/egalax_ts.c
	drivers/input/touchscreen/max11801_ts.c
	drivers/media/video/mxc/capture/Kconfig
	drivers/media/video/mxc/capture/adv7180.c
	drivers/media/video/mxc/capture/ipu_csi_enc.c
	drivers/media/video/mxc/capture/ipu_prp_vf_sdc.c
	drivers/media/video/mxc/capture/ipu_prp_vf_sdc_bg.c
	drivers/media/video/mxc/capture/mxc_v4l2_capture.c
	drivers/media/video/mxc/capture/ov5640_mipi.c
	drivers/media/video/mxc/output/mxc_vout.c
	drivers/misc/Kconfig
	drivers/misc/Makefile
	drivers/mmc/card/block.c
	drivers/mmc/core/mmc.c
	drivers/mmc/host/mmci.c
	drivers/mmc/host/sdhci-esdhc-imx.c
	drivers/mmc/host/sdhci.c
	drivers/mmc/host/sdhci.h
	drivers/mxc/Kconfig
	drivers/mxc/Makefile
	drivers/mxc/asrc/mxc_asrc.c
	drivers/mxc/gpu-viv/arch/XAQ2/hal/kernel/gc_hal_kernel_context.c
	drivers/mxc/gpu-viv/arch/XAQ2/hal/kernel/gc_hal_kernel_hardware.c
	drivers/mxc/gpu-viv/hal/kernel/gc_hal_kernel.c
	drivers/mxc/gpu-viv/hal/kernel/gc_hal_kernel.h
	drivers/mxc/gpu-viv/hal/kernel/gc_hal_kernel_command.c
	drivers/mxc/gpu-viv/hal/kernel/gc_hal_kernel_event.c
	drivers/mxc/gpu-viv/hal/kernel/inc/gc_hal.h
	drivers/mxc/gpu-viv/hal/kernel/inc/gc_hal_base.h
	drivers/mxc/gpu-viv/hal/kernel/inc/gc_hal_options.h
	drivers/mxc/gpu-viv/hal/os/linux/kernel/gc_hal_kernel_os.c
	drivers/mxc/ipu3/ipu_device.c
	drivers/mxc/vpu/mxc_vpu.c
	drivers/net/fec.c
	drivers/net/wireless/Makefile
	drivers/power/sabresd_battery.c
	drivers/regulator/core.c
	drivers/tty/serial/imx.c
	drivers/usb/core/hub.c
	drivers/usb/gadget/arcotg_udc.c
	drivers/usb/gadget/fsl_updater.c
	drivers/usb/gadget/inode.c
	drivers/usb/host/ehci-hub.c
	drivers/video/mxc/ldb.c
	drivers/video/mxc/mipi_dsi.c
	drivers/video/mxc/mxc_dispdrv.c
	drivers/video/mxc/mxc_dispdrv.h
	drivers/video/mxc/mxc_edid.c
	drivers/video/mxc/mxc_elcdif_fb.c
	drivers/video/mxc/mxc_ipuv3_fb.c
	drivers/video/mxc/mxc_spdc_fb.c
	drivers/video/mxc_hdmi.c
	drivers/watchdog/imx2_wdt.c
	fs/proc/base.c
	include/linux/mmc/host.h
	include/linux/mmc/sdhci.h
	include/linux/mxc_v4l2.h
	kernel/power/main.c
	sound/soc/codecs/mxc_hdmi.c
	sound/soc/codecs/mxc_spdif.c
	sound/soc/codecs/wm8962.c
	sound/soc/imx/Kconfig
	sound/soc/imx/Makefile
	sound/soc/imx/imx-cs42888.c
	sound/soc/imx/imx-esai.c
	sound/soc/imx/imx-wm8958.c
	sound/soc/imx/imx-wm8962.c

22 files changed, 666 insertions, 292 deletions

diff --git a/arch/arm/mach-mx6/Kconfig b/arch/arm/mach-mx6/Kconfig
index a96597d2d599..5c60c560f03a 100644
--- a/arch/arm/mach-mx6/Kconfig
+++ b/arch/arm/mach-mx6/Kconfig
@@ -65,6 +65,7 @@ config MACH_MX6Q_ARM2
 	select IMX_HAVE_PLATFORM_IMX_ELCDIF
 	select IMX_HAVE_PLATFORM_IMX_PXP
 	select IMX_HAVE_PLATFORM_IMX_PCIE
+	select IMX_HAVE_PLATFORM_IMX_CAAM
 	help
 	  Include support for i.MX 6Quad Armadillo2 platform. This includes specific
 	  configurations for the board and its peripherals.
@@ -99,6 +100,9 @@ config MACH_MX6SL_ARM2
 	select IMX_HAVE_PLATFORM_IMX_SPDC
 	select IMX_HAVE_PLATFORM_IMX_PXP
 	select IMX_HAVE_PLATFORM_IMX_KEYPAD
+	select IMX_HAVE_PLATFORM_IMX_DCP
+	select IMX_HAVE_PLATFORM_RANDOM_RNGC
+	select ARCH_HAS_RNGC
 	help
 	  Include support for i.MX 6Sololite Armadillo2 platform. This includes specific
 	  configurations for the board and its peripherals.
@@ -131,6 +135,7 @@ config MACH_MX6Q_SABRELITE
 	select IMX_HAVE_PLATFORM_MXC_HDMI
 	select IMX_HAVE_PLATFORM_IMX_ASRC
 	select IMX_HAVE_PLATFORM_FLEXCAN
+	select IMX_HAVE_PLATFORM_IMX_CAAM
 	help
 	  Include support for i.MX 6Quad SABRE Lite platform. This includes specific
 	  configurations for the board and its peripherals.
@@ -164,6 +169,7 @@ config MACH_MX6Q_SABRESD
 	select IMX_HAVE_PLATFORM_IMX_ASRC
 	select IMX_HAVE_PLATFORM_FLEXCAN
 	select IMX_HAVE_PLATFORM_IMX_PCIE
+	select IMX_HAVE_PLATFORM_IMX_CAAM
 	help
 	  Include support for i.MX 6Quad SABRE SD platform. This includes specific
 	  configurations for the board and its peripherals.
@@ -200,6 +206,8 @@ config MACH_MX6Q_SABREAUTO
 	select IMX_HAVE_PLATFORM_IMX_MIPI_DSI
 	select IMX_HAVE_PLATFORM_FLEXCAN
 	select IMX_HAVE_PLATFORM_IMX_MIPI_CSI2
+	select IMX_HAVE_PLATFORM_IMX_PCIE
+	select IMX_HAVE_PLATFORM_IMX_CAAM
 	help
 	  Include support for i.MX 6Quad SABRE Auto platform. This includes specific
 	  configurations for the board and its peripherals.
diff --git a/arch/arm/mach-mx6/board-mx6dl_arm2.h b/arch/arm/mach-mx6/board-mx6dl_arm2.h
index 4528da53694a..6ed3e65e68ee 100644
--- a/arch/arm/mach-mx6/board-mx6dl_arm2.h
+++ b/arch/arm/mach-mx6/board-mx6dl_arm2.h
@@ -319,3 +319,13 @@ static iomux_v3_cfg_t mx6dl_gpmi_nand[] __initdata = {
 	MX6DL_PAD_SD4_CLK__RAWNAND_WRN,
 	MX6DL_PAD_NANDF_WP_B__RAWNAND_RESETN,
 };
+
+static iomux_v3_cfg_t mx6dl_arm2_hdmi_ddc_pads[] = {
+	MX6DL_PAD_KEY_COL3__HDMI_TX_DDC_SCL, /* HDMI DDC SCL */
+	MX6DL_PAD_KEY_ROW3__HDMI_TX_DDC_SDA, /* HDMI DDC SDA */
+};
+
+static iomux_v3_cfg_t mx6dl_arm2_i2c2_pads[] = {
+	MX6DL_PAD_KEY_COL3__I2C2_SCL,	/* I2C2 SCL */
+	MX6DL_PAD_KEY_ROW3__I2C2_SDA,	/* I2C2 SDA */
+};
diff --git a/arch/arm/mach-mx6/board-mx6dl_sabresd.h b/arch/arm/mach-mx6/board-mx6dl_sabresd.h
index 35701a4979d4..7e6a26143a49 100644
--- a/arch/arm/mach-mx6/board-mx6dl_sabresd.h
+++ b/arch/arm/mach-mx6/board-mx6dl_sabresd.h
@@ -390,4 +390,13 @@ static iomux_v3_cfg_t mx6dl_arm2_elan_pads[] = {
 	MX6DL_PAD_EIM_D28__GPIO_3_28,
 };
 
+static iomux_v3_cfg_t mx6dl_sabresd_hdmi_ddc_pads[] = {
+	MX6DL_PAD_KEY_COL3__HDMI_TX_DDC_SCL, /* HDMI DDC SCL */
+	MX6DL_PAD_KEY_ROW3__HDMI_TX_DDC_SDA, /* HDMI DDC SDA */
+};
+
+static iomux_v3_cfg_t mx6dl_sabresd_i2c2_pads[] = {
+	MX6DL_PAD_KEY_COL3__I2C2_SCL,	/* I2C2 SCL */
+	MX6DL_PAD_KEY_ROW3__I2C2_SDA,	/* I2C2 SDA */
+};
 #endif
diff --git a/arch/arm/mach-mx6/board-mx6q_arm2.c b/arch/arm/mach-mx6/board-mx6q_arm2.c
index 2bfd23e6085b..c335e5e451c0 100644
--- a/arch/arm/mach-mx6/board-mx6q_arm2.c
+++ b/arch/arm/mach-mx6/board-mx6q_arm2.c
@@ -77,7 +77,6 @@
 #include "devices-imx6q.h"
 #include "crm_regs.h"
 #include "cpu_op-mx6.h"
-
 #include "board-mx6q_arm2.h"
 #include "board-mx6dl_arm2.h"
 
@@ -1413,8 +1412,34 @@ static void hdmi_init(int ipu_id, int disp_id)
 	mxc_iomux_set_gpr_register(3, 2, 2, hdmi_mux_setting);
 }
 
+/* On mx6x arm2 board i2c2 iomux with hdmi ddc,
+ * the pins default work at i2c2 function,
+ when hdcp enable, the pins should work at ddc function */
+
+static void hdmi_enable_ddc_pin(void)
+{
+	if (cpu_is_mx6dl())
+		mxc_iomux_v3_setup_multiple_pads(mx6dl_arm2_hdmi_ddc_pads,
+			ARRAY_SIZE(mx6dl_arm2_hdmi_ddc_pads));
+	else
+		mxc_iomux_v3_setup_multiple_pads(mx6q_arm2_hdmi_ddc_pads,
+			ARRAY_SIZE(mx6q_arm2_hdmi_ddc_pads));
+}
+
+static void hdmi_disable_ddc_pin(void)
+{
+	if (cpu_is_mx6dl())
+		mxc_iomux_v3_setup_multiple_pads(mx6dl_arm2_i2c2_pads,
+			ARRAY_SIZE(mx6dl_arm2_i2c2_pads));
+	else
+		mxc_iomux_v3_setup_multiple_pads(mx6q_arm2_i2c2_pads,
+			ARRAY_SIZE(mx6q_arm2_i2c2_pads));
+}
+
 static struct fsl_mxc_hdmi_platform_data hdmi_data = {
-	.init		= hdmi_init,
+	.init = hdmi_init,
+	.enable_pins = hdmi_enable_ddc_pin,
+	.disable_pins = hdmi_disable_ddc_pin,
 };
 
 static struct fsl_mxc_hdmi_core_platform_data hdmi_core_data = {
@@ -2184,6 +2209,7 @@ static void __init mx6_arm2_init(void)
 		mxc_register_device(&max17135_sensor_device, NULL);
 		imx6dl_add_imx_epdc(&epdc_data);
 	}
+	/* Add PCIe RC interface support */
 	imx6q_add_pcie(&mx6_arm2_pcie_data);
 	imx6q_add_busfreq();
 }
diff --git a/arch/arm/mach-mx6/board-mx6q_arm2.h b/arch/arm/mach-mx6/board-mx6q_arm2.h
index 8c3277d869e1..eb06ef89bdd8 100644
--- a/arch/arm/mach-mx6/board-mx6q_arm2.h
+++ b/arch/arm/mach-mx6/board-mx6q_arm2.h
@@ -315,3 +315,13 @@ static iomux_v3_cfg_t mx6q_gpmi_nand[] __initdata = {
 	MX6Q_PAD_SD4_CLK__RAWNAND_WRN,
 	MX6Q_PAD_NANDF_WP_B__RAWNAND_RESETN,
 };
+
+static iomux_v3_cfg_t mx6q_arm2_hdmi_ddc_pads[] = {
+	MX6Q_PAD_KEY_COL3__HDMI_TX_DDC_SCL, /* HDMI DDC SCL */
+	MX6Q_PAD_KEY_ROW3__HDMI_TX_DDC_SDA, /* HDMI DDC SDA */
+};
+
+static iomux_v3_cfg_t mx6q_arm2_i2c2_pads[] = {
+	MX6Q_PAD_KEY_COL3__I2C2_SCL,	/* I2C2 SCL */
+	MX6Q_PAD_KEY_ROW3__I2C2_SDA,	/* I2C2 SDA */
+};
diff --git a/arch/arm/mach-mx6/board-mx6q_sabreauto.c b/arch/arm/mach-mx6/board-mx6q_sabreauto.c
index 2e5cf702a23b..7d2eab2c89f2 100644
--- a/arch/arm/mach-mx6/board-mx6q_sabreauto.c
+++ b/arch/arm/mach-mx6/board-mx6q_sabreauto.c
@@ -104,6 +104,7 @@
 #define SABREAUTO_CSI0_RST		IMX_GPIO_NR(4, 5)
 #define SABREAUTO_DISP0_RESET		IMX_GPIO_NR(5, 0)
 #define SABREAUTO_I2C3_STEER		IMX_GPIO_NR(5, 4)
+#define SABREAUTO_WEIM_NOR_WDOG1        IMX_GPIO_NR(4, 29)
 #define SABREAUTO_ANDROID_VOLDOWN	IMX_GPIO_NR(5, 14)
 #define SABREAUTO_PMIC_INT		IMX_GPIO_NR(5, 16)
 #define SABREAUTO_ALS_INT		IMX_GPIO_NR(5, 17)
@@ -120,6 +121,7 @@
 #define SABREAUTO_IO_EXP_GPIO2(x)	(SABREAUTO_MAX7310_2_BASE_ADDR + (x))
 #define SABREAUTO_IO_EXP_GPIO3(x)	(SABREAUTO_MAX7310_3_BASE_ADDR + (x))
 
+#define SABREAUTO_PCIE_RST_B_REVB	(SABREAUTO_MAX7310_1_BASE_ADDR + 2)
 /*
  * CAN2 STBY and EN lines are the same as the CAN1. These lines are not
  * independent.
@@ -140,6 +142,7 @@ static int can0_enable;
 static int uart3_en;
 static int tuner_en;
 static int spinor_en;
+static int weimnor_en;
 
 static int __init spinor_enable(char *p)
 {
@@ -148,6 +151,13 @@ static int __init spinor_enable(char *p)
 }
 early_param("spi-nor", spinor_enable);
 
+static int __init weimnor_enable(char *p)
+{
+       weimnor_en = 1;
+       return 0;
+}
+early_param("weim-nor", weimnor_enable);
+
 static int __init uart3_enable(char *p)
 {
 	uart3_en = 1;
@@ -903,8 +913,34 @@ static void hdmi_init(int ipu_id, int disp_id)
 	mxc_iomux_set_gpr_register(3, 2, 2, hdmi_mux_setting);
 }
 
+/* On mx6x sabreauto board i2c2 iomux with hdmi ddc,
+ * the pins default work at i2c2 function,
+ when hdcp enable, the pins should work at ddc function */
+
+static void hdmi_enable_ddc_pin(void)
+{
+	if (cpu_is_mx6dl())
+		mxc_iomux_v3_setup_multiple_pads(mx6dl_sabreauto_hdmi_ddc_pads,
+			ARRAY_SIZE(mx6dl_sabreauto_hdmi_ddc_pads));
+	else
+		mxc_iomux_v3_setup_multiple_pads(mx6q_sabreauto_hdmi_ddc_pads,
+			ARRAY_SIZE(mx6q_sabreauto_hdmi_ddc_pads));
+}
+
+static void hdmi_disable_ddc_pin(void)
+{
+	if (cpu_is_mx6dl())
+		mxc_iomux_v3_setup_multiple_pads(mx6dl_sabreauto_i2c2_pads,
+			ARRAY_SIZE(mx6dl_sabreauto_i2c2_pads));
+	else
+		mxc_iomux_v3_setup_multiple_pads(mx6q_sabreauto_i2c2_pads,
+			ARRAY_SIZE(mx6q_sabreauto_i2c2_pads));
+}
+
 static struct fsl_mxc_hdmi_platform_data hdmi_data = {
 	.init = hdmi_init,
+	.enable_pins = hdmi_enable_ddc_pin,
+	.disable_pins = hdmi_disable_ddc_pin,
 };
 
 static struct fsl_mxc_hdmi_core_platform_data hdmi_core_data = {
@@ -1300,6 +1336,12 @@ static struct fsl_mxc_capture_platform_data capture_data[] = {
 	},
 };
 
+static const struct imx_pcie_platform_data mx6_sabreauto_pcie_data __initconst = {
+	.pcie_pwr_en	= -EINVAL,
+	.pcie_rst	= SABREAUTO_PCIE_RST_B_REVB,
+	.pcie_wake_up	= -EINVAL,
+	.pcie_dis	= -EINVAL,
+};
 
 /*!
  * Board specific initialization.
@@ -1314,6 +1356,8 @@ static void __init mx6_board_init(void)
 	iomux_v3_cfg_t *mipi_sensor_pads = NULL;
 	iomux_v3_cfg_t *i2c3_pads = NULL;
 	iomux_v3_cfg_t *tuner_pads = NULL;
+	iomux_v3_cfg_t *spinor_pads = NULL;
+	iomux_v3_cfg_t *weimnor_pads = NULL;
 
 	int common_pads_cnt;
 	int can0_pads_cnt;
@@ -1321,6 +1365,8 @@ static void __init mx6_board_init(void)
 	int mipi_sensor_pads_cnt;
 	int i2c3_pads_cnt;
 	int tuner_pads_cnt;
+	int spinor_pads_cnt;
+	int weimnor_pads_cnt;
 
 	if (cpu_is_mx6q()) {
 		common_pads = mx6q_sabreauto_pads;
@@ -1328,12 +1374,16 @@ static void __init mx6_board_init(void)
 		can1_pads = mx6q_sabreauto_can1_pads;
 		mipi_sensor_pads = mx6q_sabreauto_mipi_sensor_pads;
 		tuner_pads = mx6q_tuner_pads;
+		spinor_pads = mx6q_spinor_pads;
+		weimnor_pads = mx6q_weimnor_pads;
 
 		common_pads_cnt = ARRAY_SIZE(mx6q_sabreauto_pads);
 		can0_pads_cnt = ARRAY_SIZE(mx6q_sabreauto_can0_pads);
 		can1_pads_cnt = ARRAY_SIZE(mx6q_sabreauto_can1_pads);
 		mipi_sensor_pads_cnt = ARRAY_SIZE(mx6q_sabreauto_mipi_sensor_pads);
 		tuner_pads_cnt = ARRAY_SIZE(mx6q_tuner_pads);
+		spinor_pads_cnt = ARRAY_SIZE(mx6q_spinor_pads);
+		weimnor_pads_cnt = ARRAY_SIZE(mx6q_weimnor_pads);
 		if (board_is_mx6_reva()) {
 			i2c3_pads = mx6q_i2c3_pads_rev_a;
 			i2c3_pads_cnt = ARRAY_SIZE(mx6q_i2c3_pads_rev_a);
@@ -1347,12 +1397,17 @@ static void __init mx6_board_init(void)
 		can1_pads = mx6dl_sabreauto_can1_pads;
 		mipi_sensor_pads = mx6dl_sabreauto_mipi_sensor_pads;
 		tuner_pads = mx6dl_tuner_pads;
+		spinor_pads = mx6dl_spinor_pads;
+		weimnor_pads = mx6dl_weimnor_pads;
 
 		common_pads_cnt = ARRAY_SIZE(mx6dl_sabreauto_pads);
 		can0_pads_cnt = ARRAY_SIZE(mx6dl_sabreauto_can0_pads);
 		can1_pads_cnt = ARRAY_SIZE(mx6dl_sabreauto_can1_pads);
 		mipi_sensor_pads_cnt = ARRAY_SIZE(mx6dl_sabreauto_mipi_sensor_pads);
 		tuner_pads_cnt = ARRAY_SIZE(mx6dl_tuner_pads);
+		spinor_pads_cnt = ARRAY_SIZE(mx6dl_spinor_pads);
+		weimnor_pads_cnt = ARRAY_SIZE(mx6dl_weimnor_pads);
+
 		if (board_is_mx6_reva()) {
 			i2c3_pads = mx6dl_i2c3_pads_rev_a;
 			i2c3_pads_cnt = ARRAY_SIZE(mx6dl_i2c3_pads_rev_a);
@@ -1364,11 +1419,19 @@ static void __init mx6_board_init(void)
 
 	BUG_ON(!common_pads);
 	mxc_iomux_v3_setup_multiple_pads(common_pads, common_pads_cnt);
-	if (!spinor_en) {
+
+	/*If at least one NOR memory is selected we don't configure IC23 PADS*/
+	if (spinor_en) {
+		BUG_ON(!spinor_pads);
+		mxc_iomux_v3_setup_multiple_pads(spinor_pads, spinor_pads_cnt);
+	} else if (weimnor_en) {
+		BUG_ON(!weimnor_pads);
+		mxc_iomux_v3_setup_multiple_pads(weimnor_pads,
+						weimnor_pads_cnt);
+	} else {
 		BUG_ON(!i2c3_pads);
 		mxc_iomux_v3_setup_multiple_pads(i2c3_pads, i2c3_pads_cnt);
 	}
-
 	if (can0_enable) {
 		BUG_ON(!can0_pads);
 		mxc_iomux_v3_setup_multiple_pads(can0_pads,
@@ -1388,12 +1451,19 @@ static void __init mx6_board_init(void)
 	gpio_direction_output(SABREAUTO_I2C_EXP_RST, 1);
 
 	if (!board_is_mx6_reva()) {
-		/* enable i2c3_sda route path */
+		/* enable either EIM_D18 or i2c3_sda route path */
 		gpio_request(SABREAUTO_I2C3_STEER, "i2c3-steer");
 		if (spinor_en)
 			gpio_direction_output(SABREAUTO_I2C3_STEER, 0);
-		else
-			gpio_direction_output(SABREAUTO_I2C3_STEER, 1);
+		else if (weimnor_en) {
+			/*Put DISP0_DAT8 in ALT5 mode to prevent WDOG1 of
+			resetting WEIM NOR*/
+			gpio_direction_output(SABREAUTO_I2C3_STEER, 0);
+
+			gpio_request(SABREAUTO_WEIM_NOR_WDOG1, "nor-reset");
+			gpio_direction_output(SABREAUTO_WEIM_NOR_WDOG1, 1);
+		} else
+		gpio_direction_output(SABREAUTO_I2C3_STEER, 1);
 		/* Set GPIO_16 input for IEEE-1588 ts_clk and
 		 * RMII reference clk
 		 * For MX6 GPR1 bit21 meaning:
@@ -1443,6 +1513,8 @@ static void __init mx6_board_init(void)
 
 	imx6q_add_imx_snvs_rtc();
 
+	imx6q_add_imx_caam();
+
 	imx6q_add_imx_i2c(1, &mx6q_sabreauto_i2c1_data);
 	i2c_register_board_info(1, mxc_i2c1_board_info,
 			ARRAY_SIZE(mxc_i2c1_board_info));
@@ -1461,10 +1533,10 @@ static void __init mx6_board_init(void)
 	/* SPI */
 	imx6q_add_ecspi(0, &mx6q_sabreauto_spi_data);
 #if defined(CONFIG_MTD_M25P80) || defined(CONFIG_MTD_M25P80_MODULE)
-	spi_device_init();
+		spi_device_init();
 #else
-	mx6q_setup_weimcs();
-	platform_device_register(&physmap_flash_device);
+		mx6q_setup_weimcs();
+		platform_device_register(&physmap_flash_device);
 #endif
 	imx6q_add_mxc_hdmi(&hdmi_data);
 
@@ -1547,6 +1619,13 @@ static void __init mx6_board_init(void)
 	mxc_register_device(&mxc_si4763_audio_device, &si4763_audio_data);
 
 	imx6q_add_busfreq();
+
+	/* Add PCIe RC interface support */
+	imx6q_add_pcie(&mx6_sabreauto_pcie_data);
+
+	imx6q_add_perfmon(0);
+	imx6q_add_perfmon(1);
+	imx6q_add_perfmon(2);
 }
 
 extern void __iomem *twd_base;
diff --git a/arch/arm/mach-mx6/board-mx6q_sabreauto.h b/arch/arm/mach-mx6/board-mx6q_sabreauto.h
index bffd109115c2..da6e4387d781 100644
--- a/arch/arm/mach-mx6/board-mx6q_sabreauto.h
+++ b/arch/arm/mach-mx6/board-mx6q_sabreauto.h
@@ -215,69 +215,6 @@ static iomux_v3_cfg_t mx6q_sabreauto_pads[] = {
 	MX6Q_PAD_ENET_TXD1__MLB_MLBCLK,
 	MX6Q_PAD_GPIO_6__MLB_MLBSIG,
 	MX6Q_PAD_GPIO_2__MLB_MLBDAT,
-
-#if defined(CONFIG_MTD_M25P80) || defined(CONFIG_MTD_M25P80_MODULE)
-	/* eCSPI1 */
-	MX6Q_PAD_EIM_D16__ECSPI1_SCLK,
-	MX6Q_PAD_EIM_D17__ECSPI1_MISO,
-	MX6Q_PAD_EIM_D18__ECSPI1_MOSI,
-	MX6Q_PAD_EIM_D19__ECSPI1_SS1,
-	MX6Q_PAD_EIM_D19__GPIO_3_19,	/*SS1*/
-#else
-	/* Parallel NOR */
-	MX6Q_PAD_EIM_OE__WEIM_WEIM_OE,
-	MX6Q_PAD_EIM_RW__WEIM_WEIM_RW,
-	MX6Q_PAD_EIM_WAIT__WEIM_WEIM_WAIT,
-	MX6Q_PAD_EIM_CS0__WEIM_WEIM_CS_0,
-
-	MX6Q_PAD_EIM_LBA__WEIM_WEIM_LBA,
-	MX6Q_PAD_EIM_BCLK__WEIM_WEIM_BCLK,
-	/* Parallel Nor Data Bus */
-	MX6Q_PAD_EIM_D16__WEIM_WEIM_D_16,
-	MX6Q_PAD_EIM_D17__WEIM_WEIM_D_17,
-	MX6Q_PAD_EIM_D18__WEIM_WEIM_D_18,
-	MX6Q_PAD_EIM_D19__WEIM_WEIM_D_19,
-	MX6Q_PAD_EIM_D20__WEIM_WEIM_D_20,
-	MX6Q_PAD_EIM_D21__WEIM_WEIM_D_21,
-	MX6Q_PAD_EIM_D22__WEIM_WEIM_D_22,
-	MX6Q_PAD_EIM_D23__WEIM_WEIM_D_23,
-	MX6Q_PAD_EIM_D24__WEIM_WEIM_D_24,
-	MX6Q_PAD_EIM_D25__WEIM_WEIM_D_25,
-	MX6Q_PAD_EIM_D26__WEIM_WEIM_D_26,
-	MX6Q_PAD_EIM_D27__WEIM_WEIM_D_27,
-	MX6Q_PAD_EIM_D28__WEIM_WEIM_D_28,
-	MX6Q_PAD_EIM_D29__WEIM_WEIM_D_29,
-	MX6Q_PAD_EIM_D30__WEIM_WEIM_D_30,
-	MX6Q_PAD_EIM_D31__WEIM_WEIM_D_31,
-
-	/* Parallel Nor 25 bit Address Bus */
-	MX6Q_PAD_EIM_A24__WEIM_WEIM_A_24,
-	MX6Q_PAD_EIM_A23__WEIM_WEIM_A_23,
-	MX6Q_PAD_EIM_A22__WEIM_WEIM_A_22,
-	MX6Q_PAD_EIM_A21__WEIM_WEIM_A_21,
-	MX6Q_PAD_EIM_A20__WEIM_WEIM_A_20,
-	MX6Q_PAD_EIM_A19__WEIM_WEIM_A_19,
-	MX6Q_PAD_EIM_A18__WEIM_WEIM_A_18,
-	MX6Q_PAD_EIM_A17__WEIM_WEIM_A_17,
-	MX6Q_PAD_EIM_A16__WEIM_WEIM_A_16,
-
-	MX6Q_PAD_EIM_DA15__WEIM_WEIM_DA_A_15,
-	MX6Q_PAD_EIM_DA14__WEIM_WEIM_DA_A_14,
-	MX6Q_PAD_EIM_DA13__WEIM_WEIM_DA_A_13,
-	MX6Q_PAD_EIM_DA12__WEIM_WEIM_DA_A_12,
-	MX6Q_PAD_EIM_DA11__WEIM_WEIM_DA_A_11,
-	MX6Q_PAD_EIM_DA10__WEIM_WEIM_DA_A_10,
-	MX6Q_PAD_EIM_DA9__WEIM_WEIM_DA_A_9,
-	MX6Q_PAD_EIM_DA8__WEIM_WEIM_DA_A_8,
-	MX6Q_PAD_EIM_DA7__WEIM_WEIM_DA_A_7,
-	MX6Q_PAD_EIM_DA6__WEIM_WEIM_DA_A_6,
-	MX6Q_PAD_EIM_DA5__WEIM_WEIM_DA_A_5,
-	MX6Q_PAD_EIM_DA4__WEIM_WEIM_DA_A_4,
-	MX6Q_PAD_EIM_DA3__WEIM_WEIM_DA_A_3,
-	MX6Q_PAD_EIM_DA2__WEIM_WEIM_DA_A_2,
-	MX6Q_PAD_EIM_DA1__WEIM_WEIM_DA_A_1,
-	MX6Q_PAD_EIM_DA0__WEIM_WEIM_DA_A_0,
-#endif
 };
 
 static iomux_v3_cfg_t mx6q_sabreauto_can0_pads[] = {
@@ -355,3 +292,80 @@ static iomux_v3_cfg_t mx6q_tuner_pads[] __initdata = {
 
 };
 
+static iomux_v3_cfg_t mx6q_spinor_pads[] __initdata = {
+	/* eCSPI1 */
+	MX6Q_PAD_EIM_D16__ECSPI1_SCLK,
+	MX6Q_PAD_EIM_D17__ECSPI1_MISO,
+	MX6Q_PAD_EIM_D18__ECSPI1_MOSI,
+	MX6Q_PAD_EIM_D19__ECSPI1_SS1,
+
+	MX6Q_PAD_EIM_D19__GPIO_3_19,
+};
+
+static iomux_v3_cfg_t mx6q_weimnor_pads[] __initdata = {
+	/* Parallel NOR */
+	MX6Q_PAD_EIM_OE__WEIM_WEIM_OE,
+	MX6Q_PAD_EIM_RW__WEIM_WEIM_RW,
+	MX6Q_PAD_EIM_WAIT__WEIM_WEIM_WAIT,
+	MX6Q_PAD_EIM_CS0__WEIM_WEIM_CS_0,
+	/*Control NOR reset using gpio mode*/
+	MX6Q_PAD_DISP0_DAT8__GPIO_4_29,
+
+	MX6Q_PAD_EIM_LBA__WEIM_WEIM_LBA,
+	MX6Q_PAD_EIM_BCLK__WEIM_WEIM_BCLK,
+	/* Parallel Nor Data Bus */
+	MX6Q_PAD_EIM_D16__WEIM_WEIM_D_16,
+	MX6Q_PAD_EIM_D17__WEIM_WEIM_D_17,
+	MX6Q_PAD_EIM_D18__WEIM_WEIM_D_18,
+	MX6Q_PAD_EIM_D19__WEIM_WEIM_D_19,
+	MX6Q_PAD_EIM_D20__WEIM_WEIM_D_20,
+	MX6Q_PAD_EIM_D21__WEIM_WEIM_D_21,
+	MX6Q_PAD_EIM_D22__WEIM_WEIM_D_22,
+	MX6Q_PAD_EIM_D23__WEIM_WEIM_D_23,
+	MX6Q_PAD_EIM_D24__WEIM_WEIM_D_24,
+	MX6Q_PAD_EIM_D25__WEIM_WEIM_D_25,
+	MX6Q_PAD_EIM_D26__WEIM_WEIM_D_26,
+	MX6Q_PAD_EIM_D27__WEIM_WEIM_D_27,
+	MX6Q_PAD_EIM_D28__WEIM_WEIM_D_28,
+	MX6Q_PAD_EIM_D29__WEIM_WEIM_D_29,
+	MX6Q_PAD_EIM_D30__WEIM_WEIM_D_30,
+	MX6Q_PAD_EIM_D31__WEIM_WEIM_D_31,
+
+	/* Parallel Nor 25 bit Address Bus */
+	MX6Q_PAD_EIM_A24__GPIO_5_4,
+	MX6Q_PAD_EIM_A23__WEIM_WEIM_A_23,
+	MX6Q_PAD_EIM_A22__WEIM_WEIM_A_22,
+	MX6Q_PAD_EIM_A21__WEIM_WEIM_A_21,
+	MX6Q_PAD_EIM_A20__WEIM_WEIM_A_20,
+	MX6Q_PAD_EIM_A19__WEIM_WEIM_A_19,
+	MX6Q_PAD_EIM_A18__WEIM_WEIM_A_18,
+	MX6Q_PAD_EIM_A17__WEIM_WEIM_A_17,
+	MX6Q_PAD_EIM_A16__WEIM_WEIM_A_16,
+
+	MX6Q_PAD_EIM_DA15__WEIM_WEIM_DA_A_15,
+	MX6Q_PAD_EIM_DA14__WEIM_WEIM_DA_A_14,
+	MX6Q_PAD_EIM_DA13__WEIM_WEIM_DA_A_13,
+	MX6Q_PAD_EIM_DA12__WEIM_WEIM_DA_A_12,
+	MX6Q_PAD_EIM_DA11__WEIM_WEIM_DA_A_11,
+	MX6Q_PAD_EIM_DA10__WEIM_WEIM_DA_A_10,
+	MX6Q_PAD_EIM_DA9__WEIM_WEIM_DA_A_9,
+	MX6Q_PAD_EIM_DA8__WEIM_WEIM_DA_A_8,
+	MX6Q_PAD_EIM_DA7__WEIM_WEIM_DA_A_7,
+	MX6Q_PAD_EIM_DA6__WEIM_WEIM_DA_A_6,
+	MX6Q_PAD_EIM_DA5__WEIM_WEIM_DA_A_5,
+	MX6Q_PAD_EIM_DA4__WEIM_WEIM_DA_A_4,
+	MX6Q_PAD_EIM_DA3__WEIM_WEIM_DA_A_3,
+	MX6Q_PAD_EIM_DA2__WEIM_WEIM_DA_A_2,
+	MX6Q_PAD_EIM_DA1__WEIM_WEIM_DA_A_1,
+	MX6Q_PAD_EIM_DA0__WEIM_WEIM_DA_A_0,
+};
+
+static iomux_v3_cfg_t mx6q_sabreauto_hdmi_ddc_pads[] = {
+	MX6Q_PAD_KEY_COL3__HDMI_TX_DDC_SCL, /* HDMI DDC SCL */
+	MX6Q_PAD_KEY_ROW3__HDMI_TX_DDC_SDA, /* HDMI DDC SDA */
+};
+
+static iomux_v3_cfg_t mx6q_sabreauto_i2c2_pads[] = {
+	MX6Q_PAD_KEY_COL3__I2C2_SCL,    /* I2C2 SCL */
+	MX6Q_PAD_KEY_ROW3__I2C2_SDA,    /* I2C2 SDA */
+};
diff --git a/arch/arm/mach-mx6/board-mx6q_sabrelite.c b/arch/arm/mach-mx6/board-mx6q_sabrelite.c
index 3f00ae563492..925dfb71ea0e 100644
--- a/arch/arm/mach-mx6/board-mx6q_sabrelite.c
+++ b/arch/arm/mach-mx6/board-mx6q_sabrelite.c
@@ -327,6 +327,16 @@ static iomux_v3_cfg_t mx6q_sabrelite_csi0_sensor_pads[] = {
 	MX6Q_PAD_NANDF_WP_B__GPIO_6_9,		/* J16 - MIPI GP */
 };
 
+static iomux_v3_cfg_t mx6q_sabrelite_hdmi_ddc_pads[] = {
+	MX6Q_PAD_KEY_COL3__HDMI_TX_DDC_SCL, /* HDMI DDC SCL */
+	MX6Q_PAD_KEY_ROW3__HDMI_TX_DDC_SDA, /* HDMI DDC SDA */
+};
+
+static iomux_v3_cfg_t mx6q_sabrelite_i2c2_pads[] = {
+	MX6Q_PAD_KEY_COL3__I2C2_SCL,	/* I2C2 SCL */
+	MX6Q_PAD_KEY_ROW3__I2C2_SDA,	/* I2C2 SDA */
+};
+
 #define MX6Q_USDHC_PAD_SETTING(id, speed)	\
 mx6q_sd##id##_##speed##mhz[] = {		\
 	MX6Q_PAD_SD##id##_CLK__USDHC##id##_CLK_##speed##MHZ,	\
@@ -804,8 +814,26 @@ static void hdmi_init(int ipu_id, int disp_id)
 	mxc_iomux_set_gpr_register(3, 2, 2, hdmi_mux_setting);
 }
 
+/* On mx6x sbarelite board i2c2 iomux with hdmi ddc,
+ * the pins default work at i2c2 function,
+ when hdcp enable, the pins should work at ddc function */
+
+static void hdmi_enable_ddc_pin(void)
+{
+	mxc_iomux_v3_setup_multiple_pads(mx6q_sabrelite_hdmi_ddc_pads,
+		ARRAY_SIZE(mx6q_sabrelite_hdmi_ddc_pads));
+}
+
+static void hdmi_disable_ddc_pin(void)
+{
+	mxc_iomux_v3_setup_multiple_pads(mx6q_sabrelite_i2c2_pads,
+		ARRAY_SIZE(mx6q_sabrelite_i2c2_pads));
+}
+
 static struct fsl_mxc_hdmi_platform_data hdmi_data = {
 	.init = hdmi_init,
+	.enable_pins = hdmi_enable_ddc_pin,
+	.disable_pins = hdmi_disable_ddc_pin,
 };
 
 static struct fsl_mxc_hdmi_core_platform_data hdmi_core_data = {
@@ -1145,6 +1173,8 @@ static void __init mx6_sabrelite_board_init(void)
 	imx6q_add_mipi_csi2(&mipi_csi2_pdata);
 	imx6q_add_imx_snvs_rtc();
 
+	imx6q_add_imx_caam();
+
 	imx6q_add_imx_i2c(0, &mx6q_sabrelite_i2c_data);
 	imx6q_add_imx_i2c(1, &mx6q_sabrelite_i2c_data);
 	imx6q_add_imx_i2c(2, &mx6q_sabrelite_i2c_data);
diff --git a/arch/arm/mach-mx6/board-mx6q_sabresd.c b/arch/arm/mach-mx6/board-mx6q_sabresd.c
index 955f47e7ab8c..e03777884aa3 100644
--- a/arch/arm/mach-mx6/board-mx6q_sabresd.c
+++ b/arch/arm/mach-mx6/board-mx6q_sabresd.c
@@ -1277,8 +1277,34 @@ static void hdmi_init(int ipu_id, int disp_id)
 	mxc_iomux_set_gpr_register(3, 2, 2, hdmi_mux_setting);
 }
 
+/* On mx6x sabresd board i2c2 iomux with hdmi ddc,
+ * the pins default work at i2c2 function,
+ when hdcp enable, the pins should work at ddc function */
+
+static void hdmi_enable_ddc_pin(void)
+{
+	if (cpu_is_mx6dl())
+		mxc_iomux_v3_setup_multiple_pads(mx6dl_sabresd_hdmi_ddc_pads,
+			ARRAY_SIZE(mx6dl_sabresd_hdmi_ddc_pads));
+	else
+		mxc_iomux_v3_setup_multiple_pads(mx6q_sabresd_hdmi_ddc_pads,
+			ARRAY_SIZE(mx6q_sabresd_hdmi_ddc_pads));
+}
+
+static void hdmi_disable_ddc_pin(void)
+{
+	if (cpu_is_mx6dl())
+		mxc_iomux_v3_setup_multiple_pads(mx6dl_sabresd_i2c2_pads,
+			ARRAY_SIZE(mx6dl_sabresd_i2c2_pads));
+	else
+		mxc_iomux_v3_setup_multiple_pads(mx6q_sabresd_i2c2_pads,
+			ARRAY_SIZE(mx6q_sabresd_i2c2_pads));
+}
+
 static struct fsl_mxc_hdmi_platform_data hdmi_data = {
 	.init = hdmi_init,
+	.enable_pins = hdmi_enable_ddc_pin,
+	.disable_pins = hdmi_disable_ddc_pin,
 };
 
 static struct fsl_mxc_hdmi_core_platform_data hdmi_core_data = {
@@ -1702,6 +1728,8 @@ static void __init mx6_sabresd_board_init(void)
 	imx6q_add_mipi_csi2(&mipi_csi2_pdata);
 	imx6q_add_imx_snvs_rtc();
 
+	imx6q_add_imx_caam();
+
 	if (board_is_mx6_reva()) {
 		strcpy(mxc_i2c0_board_info[0].type, "wm8958");
 		mxc_i2c0_board_info[0].platform_data = &wm8958_config_data;
@@ -1737,6 +1765,7 @@ static void __init mx6_sabresd_board_init(void)
 	imx6q_add_anatop_thermal_imx(1, &mx6q_sabresd_anatop_thermal_data);
 	imx6_init_fec(fec_data);
 	imx6q_add_pm_imx(0, &mx6q_sabresd_pm_data);
+
 	/* Move sd4 to first because sd4 connect to emmc.
 	   Mfgtools want emmc is mmcblk0 and other sd card is mmcblk1.
 	*/
@@ -1842,6 +1871,7 @@ static void __init mx6_sabresd_board_init(void)
 	pm_power_off = mx6_snvs_poweroff;
 	imx6q_add_busfreq();
 
+	/* Add PCIe RC interface support */
 	imx6q_add_pcie(&mx6_sabresd_pcie_data);
 	if (cpu_is_mx6dl()) {
 		mxc_iomux_v3_setup_multiple_pads(mx6dl_arm2_elan_pads,
@@ -1872,6 +1902,10 @@ static void __init mx6_sabresd_board_init(void)
 		sdio_clk->flags = AHB_MED_SET_POINT | CPU_FREQ_TRIG_UPDATE;
 		clk_put(sdio_clk);
 	}
+	imx6_add_armpmu();
+	imx6q_add_perfmon(0);
+	imx6q_add_perfmon(1);
+	imx6q_add_perfmon(2);
 }
 
 extern void __iomem *twd_base;
diff --git a/arch/arm/mach-mx6/board-mx6q_sabresd.h b/arch/arm/mach-mx6/board-mx6q_sabresd.h
index af3df8b01092..54ad3ac416b6 100644
--- a/arch/arm/mach-mx6/board-mx6q_sabresd.h
+++ b/arch/arm/mach-mx6/board-mx6q_sabresd.h
@@ -28,7 +28,7 @@ static iomux_v3_cfg_t mx6q_sabresd_pads[] = {
 	MX6Q_PAD_CSI0_DAT7__AUDMUX_AUD3_RXD,
 
 	/* CAN1  */
-	MX6Q_PAD_KEY_ROW2__CAN1_RXCAN,
+	MX6Q_PAD_KEY_ROW2__HDMI_TX_CEC_LINE,
 	/* MX6Q_PAD_KEY_COL2__CAN1_TXCAN, */
 	MX6Q_PAD_GPIO_1__GPIO_1_1,		/* user defiend green led */
 	MX6Q_PAD_GPIO_2__GPIO_1_2,		/* user defined red led */
@@ -128,9 +128,9 @@ static iomux_v3_cfg_t mx6q_sabresd_pads[] = {
 	MX6Q_PAD_CSI0_DAT8__I2C1_SDA,
 	MX6Q_PAD_CSI0_DAT9__I2C1_SCL,
 
-	/* I2C2 Camera, MIPI */
-	MX6Q_PAD_KEY_COL3__I2C2_SCL,	/* GPIO4[12] */
-	MX6Q_PAD_KEY_ROW3__I2C2_SDA,	/* GPIO4[13] */
+	/* I2C2, Camera, MIPI */
+	MX6Q_PAD_KEY_COL3__I2C2_SCL,
+	MX6Q_PAD_KEY_ROW3__I2C2_SDA,
 
 	/* I2C3 */
 	MX6Q_PAD_GPIO_3__I2C3_SCL,	/* GPIO1[3] */
@@ -288,4 +288,14 @@ static iomux_v3_cfg_t mx6q_sabresd_mipi_sensor_pads[] = {
 	MX6Q_PAD_SD1_DAT2__GPIO_1_19,		/* camera PWDN */
 	MX6Q_PAD_SD1_CLK__GPIO_1_20,		/* camera RESET */
 };
+
+static iomux_v3_cfg_t mx6q_sabresd_hdmi_ddc_pads[] = {
+	MX6Q_PAD_KEY_COL3__HDMI_TX_DDC_SCL, /* HDMI DDC SCL */
+	MX6Q_PAD_KEY_ROW3__HDMI_TX_DDC_SDA, /* HDMI DDC SDA */
+};
+
+static iomux_v3_cfg_t mx6q_sabresd_i2c2_pads[] = {
+	MX6Q_PAD_KEY_COL3__I2C2_SCL,	/* I2C2 SCL */
+	MX6Q_PAD_KEY_ROW3__I2C2_SDA,	/* I2C2 SDA */
+};
 #endif
diff --git a/arch/arm/mach-mx6/board-mx6sl_arm2.c b/arch/arm/mach-mx6/board-mx6sl_arm2.c
index 2507970133eb..2efca1ba5d93 100755
--- a/arch/arm/mach-mx6/board-mx6sl_arm2.c
+++ b/arch/arm/mach-mx6/board-mx6sl_arm2.c
@@ -129,6 +129,7 @@
 #define MX6SL_ARM2_ELAN_INT		IMX_GPIO_NR(2, 10)
 #define MX6SL_ARM2_ELAN_RST		IMX_GPIO_NR(4, 4)
 
+static int spdc_sel;
 static int max17135_regulator_init(struct max17135 *max17135);
 struct clk *extern_audio_root;
 
@@ -670,23 +671,17 @@ static int mx6sl_arm2_fec_phy_init(struct phy_device *phydev)
 
 	/* power on FEC phy and reset phy */
 	gpio_request(MX6_ARM2_FEC_PWR_EN, "fec-pwr");
-	gpio_direction_output(MX6_ARM2_FEC_PWR_EN, 1);
+	gpio_direction_output(MX6_ARM2_FEC_PWR_EN, 0);
 	/* wait RC ms for hw reset */
-	udelay(50);
+	msleep(1);
+	gpio_direction_output(MX6_ARM2_FEC_PWR_EN, 1);
 
 	/* check phy power */
 	val = phy_read(phydev, 0x0);
 	if (val & BMCR_PDOWN) {
 		phy_write(phydev, 0x0, (val & ~BMCR_PDOWN));
-		udelay(50);
 	}
 
-	/* sw reset phy */
-	val = phy_read(phydev, 0x0);
-	val |= BMCR_RESET;
-	phy_write(phydev, 0x0, val);
-	udelay(50);
-
 	return 0;
 }
 
@@ -1084,13 +1079,19 @@ static struct imx_spdc_fb_platform_data spdc_data = {
 	.disable_pins = spdc_disable_pins,
 };
 
-#if defined(CONFIG_FB_MXC_SIPIX_PANEL)
+static int __init early_use_spdc_sel(char *p)
+{
+	spdc_sel = 1;
+	return 0;
+}
+early_param("spdc", early_use_spdc_sel);
+
 static void setup_spdc(void)
 {
 	/* GPR0[8]: 0:EPDC, 1:SPDC */
-	mxc_iomux_set_gpr_register(0, 8, 1, 1);
+	if (spdc_sel)
+		mxc_iomux_set_gpr_register(0, 8, 1, 1);
 }
-#endif
 
 static void imx6_arm2_usbotg_vbus(bool on)
 {
@@ -1207,6 +1208,17 @@ static void __init elan_ts_init(void)
 	gpio_direction_output(MX6SL_ARM2_ELAN_CE, 1);
 }
 
+#define SNVS_LPCR 0x38
+static void mx6_snvs_poweroff(void)
+{
+	u32 value;
+	void __iomem *mx6_snvs_base = MX6_IO_ADDRESS(MX6Q_SNVS_BASE_ADDR);
+
+	value = readl(mx6_snvs_base + SNVS_LPCR);
+	/* set TOP and DP_EN bit */
+	writel(value | 0x60, mx6_snvs_base + SNVS_LPCR);
+}
+
 /*!
  * Board specific initialization.
  */
@@ -1270,14 +1282,14 @@ static void __init mx6_arm2_init(void)
 	imx6dl_add_imx_pxp();
 	imx6dl_add_imx_pxp_client();
 	mxc_register_device(&max17135_sensor_device, NULL);
-	imx6dl_add_imx_epdc(&epdc_data);
-#if defined(CONFIG_FB_MXC_SIPIX_PANEL)
 	setup_spdc();
-#endif
-	imx6sl_add_imx_spdc(&spdc_data);
+	if (!spdc_sel)
+		imx6dl_add_imx_epdc(&epdc_data);
+	else
+		imx6sl_add_imx_spdc(&spdc_data);
 	imx6q_add_dvfs_core(&mx6sl_arm2_dvfscore_data);
 
-    imx6q_init_audio();
+	imx6q_init_audio();
 
 	imx6q_add_viim();
 	imx6q_add_imx2_wdt(0, NULL);
@@ -1285,6 +1297,10 @@ static void __init mx6_arm2_init(void)
 	imx_add_viv_gpu(&imx6_gpu_data, &imx6q_gpu_pdata);
 	imx6sl_add_imx_keypad(&mx6sl_arm2_map_data);
 	imx6q_add_busfreq();
+	imx6sl_add_dcp();
+	imx6sl_add_rngb();
+
+	pm_power_off = mx6_snvs_poweroff;
 }
 
 extern void __iomem *twd_base;
diff --git a/arch/arm/mach-mx6/board-mx6sl_arm2.h b/arch/arm/mach-mx6/board-mx6sl_arm2.h
index d720ab3465b6..09a211690029 100755
--- a/arch/arm/mach-mx6/board-mx6sl_arm2.h
+++ b/arch/arm/mach-mx6/board-mx6sl_arm2.h
@@ -153,6 +153,9 @@ static iomux_v3_cfg_t mx6sl_arm2_pads[] = {
 	MX6SL_PAD_KEY_ROW1__KPP_ROW_1,
 	MX6SL_PAD_KEY_ROW2__KPP_ROW_2,
 	MX6SL_PAD_KEY_ROW3__KPP_ROW_3,
+
+	/* WDOG */
+	MX6SL_PAD_WDOG_B__WDOG1_WDOG_B,
 };
 
 static iomux_v3_cfg_t mx6sl_arm2_epdc_enable_pads[] = {
diff --git a/arch/arm/mach-mx6/board-mx6solo_sabreauto.h b/arch/arm/mach-mx6/board-mx6solo_sabreauto.h
index dd113bab749b..f51925bee9fa 100644
--- a/arch/arm/mach-mx6/board-mx6solo_sabreauto.h
+++ b/arch/arm/mach-mx6/board-mx6solo_sabreauto.h
@@ -215,70 +215,6 @@ static iomux_v3_cfg_t mx6dl_sabreauto_pads[] = {
 	MX6DL_PAD_ENET_TXD1__MLB_MLBCLK,
 	MX6DL_PAD_GPIO_6__MLB_MLBSIG,
 	MX6DL_PAD_GPIO_2__MLB_MLBDAT,
-
-#if defined(CONFIG_MTD_M25P80) || defined(CONFIG_MTD_M25P80_MODULE)
-	/* eCSPI1 */
-	MX6DL_PAD_EIM_D16__ECSPI1_SCLK,
-	MX6DL_PAD_EIM_D17__ECSPI1_MISO,
-	MX6DL_PAD_EIM_D18__ECSPI1_MOSI,
-	MX6DL_PAD_EIM_D19__ECSPI1_SS1,
-
-	MX6DL_PAD_EIM_D19__GPIO_3_19,
-#else
-	/* Parallel NOR */
-	MX6DL_PAD_EIM_OE__WEIM_WEIM_OE,
-	MX6DL_PAD_EIM_RW__WEIM_WEIM_RW,
-	MX6DL_PAD_EIM_WAIT__WEIM_WEIM_WAIT,
-	MX6DL_PAD_EIM_CS0__WEIM_WEIM_CS_0,
-
-	MX6DL_PAD_EIM_LBA__WEIM_WEIM_LBA,
-	MX6DL_PAD_EIM_BCLK__WEIM_WEIM_BCLK,
-	/* Parallel Nor Data Bus */
-	MX6DL_PAD_EIM_D16__WEIM_WEIM_D_16,
-	MX6DL_PAD_EIM_D17__WEIM_WEIM_D_17,
-	MX6DL_PAD_EIM_D18__WEIM_WEIM_D_18,
-	MX6DL_PAD_EIM_D19__WEIM_WEIM_D_19,
-	MX6DL_PAD_EIM_D20__WEIM_WEIM_D_20,
-	MX6DL_PAD_EIM_D21__WEIM_WEIM_D_21,
-	MX6DL_PAD_EIM_D22__WEIM_WEIM_D_22,
-	MX6DL_PAD_EIM_D23__WEIM_WEIM_D_23,
-	MX6DL_PAD_EIM_D24__WEIM_WEIM_D_24,
-	MX6DL_PAD_EIM_D25__WEIM_WEIM_D_25,
-	MX6DL_PAD_EIM_D26__WEIM_WEIM_D_26,
-	MX6DL_PAD_EIM_D27__WEIM_WEIM_D_27,
-	MX6DL_PAD_EIM_D28__WEIM_WEIM_D_28,
-	MX6DL_PAD_EIM_D29__WEIM_WEIM_D_29,
-	MX6DL_PAD_EIM_D30__WEIM_WEIM_D_30,
-	MX6DL_PAD_EIM_D31__WEIM_WEIM_D_31,
-
-	/* Parallel Nor 25 bit Address Bus */
-	MX6DL_PAD_EIM_A24__WEIM_WEIM_A_24,
-	MX6DL_PAD_EIM_A23__WEIM_WEIM_A_23,
-	MX6DL_PAD_EIM_A22__WEIM_WEIM_A_22,
-	MX6DL_PAD_EIM_A21__WEIM_WEIM_A_21,
-	MX6DL_PAD_EIM_A20__WEIM_WEIM_A_20,
-	MX6DL_PAD_EIM_A19__WEIM_WEIM_A_19,
-	MX6DL_PAD_EIM_A18__WEIM_WEIM_A_18,
-	MX6DL_PAD_EIM_A17__WEIM_WEIM_A_17,
-	MX6DL_PAD_EIM_A16__WEIM_WEIM_A_16,
-
-	MX6DL_PAD_EIM_DA15__WEIM_WEIM_DA_A_15,
-	MX6DL_PAD_EIM_DA14__WEIM_WEIM_DA_A_14,
-	MX6DL_PAD_EIM_DA13__WEIM_WEIM_DA_A_13,
-	MX6DL_PAD_EIM_DA12__WEIM_WEIM_DA_A_12,
-	MX6DL_PAD_EIM_DA11__WEIM_WEIM_DA_A_11,
-	MX6DL_PAD_EIM_DA10__WEIM_WEIM_DA_A_10,
-	MX6DL_PAD_EIM_DA9__WEIM_WEIM_DA_A_9,
-	MX6DL_PAD_EIM_DA8__WEIM_WEIM_DA_A_8,
-	MX6DL_PAD_EIM_DA7__WEIM_WEIM_DA_A_7,
-	MX6DL_PAD_EIM_DA6__WEIM_WEIM_DA_A_6,
-	MX6DL_PAD_EIM_DA5__WEIM_WEIM_DA_A_5,
-	MX6DL_PAD_EIM_DA4__WEIM_WEIM_DA_A_4,
-	MX6DL_PAD_EIM_DA3__WEIM_WEIM_DA_A_3,
-	MX6DL_PAD_EIM_DA2__WEIM_WEIM_DA_A_2,
-	MX6DL_PAD_EIM_DA1__WEIM_WEIM_DA_A_1,
-	MX6DL_PAD_EIM_DA0__WEIM_WEIM_DA_A_0,
-#endif
 };
 
 static iomux_v3_cfg_t mx6dl_sabreauto_can0_pads[] = {
@@ -355,3 +291,81 @@ static iomux_v3_cfg_t mx6dl_tuner_pads[] __initdata = {
 	MX6DL_PAD_DISP0_DAT18__AUDMUX_AUD5_TXFS,
 	MX6DL_PAD_DISP0_DAT19__AUDMUX_AUD5_RXD,
 };
+
+static iomux_v3_cfg_t mx6dl_spinor_pads[] __initdata = {
+	/* eCSPI1 */
+	MX6DL_PAD_EIM_D16__ECSPI1_SCLK,
+	MX6DL_PAD_EIM_D17__ECSPI1_MISO,
+	MX6DL_PAD_EIM_D18__ECSPI1_MOSI,
+	MX6DL_PAD_EIM_D19__ECSPI1_SS1,
+
+	MX6DL_PAD_EIM_D19__GPIO_3_19,
+};
+
+static iomux_v3_cfg_t mx6dl_weimnor_pads[] __initdata = {
+	/* Parallel NOR */
+	MX6DL_PAD_EIM_OE__WEIM_WEIM_OE,
+	MX6DL_PAD_EIM_RW__WEIM_WEIM_RW,
+	MX6DL_PAD_EIM_WAIT__WEIM_WEIM_WAIT,
+	MX6DL_PAD_EIM_CS0__WEIM_WEIM_CS_0,
+	/*Control NOR reset using gpio mode*/
+	MX6DL_PAD_DISP0_DAT8__GPIO_4_29,
+
+	MX6DL_PAD_EIM_LBA__WEIM_WEIM_LBA,
+	MX6DL_PAD_EIM_BCLK__WEIM_WEIM_BCLK,
+	/* Parallel Nor Data Bus */
+	MX6DL_PAD_EIM_D16__WEIM_WEIM_D_16,
+	MX6DL_PAD_EIM_D17__WEIM_WEIM_D_17,
+	MX6DL_PAD_EIM_D18__WEIM_WEIM_D_18,
+	MX6DL_PAD_EIM_D19__WEIM_WEIM_D_19,
+	MX6DL_PAD_EIM_D20__WEIM_WEIM_D_20,
+	MX6DL_PAD_EIM_D21__WEIM_WEIM_D_21,
+	MX6DL_PAD_EIM_D22__WEIM_WEIM_D_22,
+	MX6DL_PAD_EIM_D23__WEIM_WEIM_D_23,
+	MX6DL_PAD_EIM_D24__WEIM_WEIM_D_24,
+	MX6DL_PAD_EIM_D25__WEIM_WEIM_D_25,
+	MX6DL_PAD_EIM_D26__WEIM_WEIM_D_26,
+	MX6DL_PAD_EIM_D27__WEIM_WEIM_D_27,
+	MX6DL_PAD_EIM_D28__WEIM_WEIM_D_28,
+	MX6DL_PAD_EIM_D29__WEIM_WEIM_D_29,
+	MX6DL_PAD_EIM_D30__WEIM_WEIM_D_30,
+	MX6DL_PAD_EIM_D31__WEIM_WEIM_D_31,
+
+	/* Parallel Nor 25 bit Address Bus */
+	MX6DL_PAD_EIM_A24__GPIO_5_4,
+	MX6DL_PAD_EIM_A23__WEIM_WEIM_A_23,
+	MX6DL_PAD_EIM_A22__WEIM_WEIM_A_22,
+	MX6DL_PAD_EIM_A21__WEIM_WEIM_A_21,
+	MX6DL_PAD_EIM_A20__WEIM_WEIM_A_20,
+	MX6DL_PAD_EIM_A19__WEIM_WEIM_A_19,
+	MX6DL_PAD_EIM_A18__WEIM_WEIM_A_18,
+	MX6DL_PAD_EIM_A17__WEIM_WEIM_A_17,
+	MX6DL_PAD_EIM_A16__WEIM_WEIM_A_16,
+
+	MX6DL_PAD_EIM_DA15__WEIM_WEIM_DA_A_15,
+	MX6DL_PAD_EIM_DA14__WEIM_WEIM_DA_A_14,
+	MX6DL_PAD_EIM_DA13__WEIM_WEIM_DA_A_13,
+	MX6DL_PAD_EIM_DA12__WEIM_WEIM_DA_A_12,
+	MX6DL_PAD_EIM_DA11__WEIM_WEIM_DA_A_11,
+	MX6DL_PAD_EIM_DA10__WEIM_WEIM_DA_A_10,
+	MX6DL_PAD_EIM_DA9__WEIM_WEIM_DA_A_9,
+	MX6DL_PAD_EIM_DA8__WEIM_WEIM_DA_A_8,
+	MX6DL_PAD_EIM_DA7__WEIM_WEIM_DA_A_7,
+	MX6DL_PAD_EIM_DA6__WEIM_WEIM_DA_A_6,
+	MX6DL_PAD_EIM_DA5__WEIM_WEIM_DA_A_5,
+	MX6DL_PAD_EIM_DA4__WEIM_WEIM_DA_A_4,
+	MX6DL_PAD_EIM_DA3__WEIM_WEIM_DA_A_3,
+	MX6DL_PAD_EIM_DA2__WEIM_WEIM_DA_A_2,
+	MX6DL_PAD_EIM_DA1__WEIM_WEIM_DA_A_1,
+	MX6DL_PAD_EIM_DA0__WEIM_WEIM_DA_A_0,
+};
+
+static iomux_v3_cfg_t mx6dl_sabreauto_hdmi_ddc_pads[] = {
+	MX6DL_PAD_KEY_COL3__HDMI_TX_DDC_SCL, /* HDMI DDC SCL */
+	MX6DL_PAD_KEY_ROW3__HDMI_TX_DDC_SDA, /* HDMI DDC SDA */
+};
+
+static iomux_v3_cfg_t mx6dl_sabreauto_i2c2_pads[] = {
+	MX6DL_PAD_KEY_COL3__I2C2_SCL,   /* I2C2 SCL */
+	MX6DL_PAD_KEY_ROW3__I2C2_SDA,   /* I2C2 SDA */
+};
diff --git a/arch/arm/mach-mx6/bus_freq.c b/arch/arm/mach-mx6/bus_freq.c
index cb4d6eaf880f..b1a0af0f3d35 100644
--- a/arch/arm/mach-mx6/bus_freq.c
+++ b/arch/arm/mach-mx6/bus_freq.c
@@ -78,7 +78,6 @@ void set_ddr_freq(int ddr_freq);
 extern int init_mmdc_settings(void);
 extern struct cpu_op *(*get_cpu_op)(int *op);
 extern int update_ddr_freq(int ddr_rate);
-extern void __iomem *gpc_base;
 
 struct mutex bus_freq_mutex;
 
@@ -93,18 +92,18 @@ static struct clk *ahb_clk;
 static struct clk *periph_clk;
 static struct clk *osc_clk;
 static struct clk *cpu_clk;
-static unsigned int org_ldo;
 static struct clk *pll3;
 static struct clk *pll2;
 static struct clk *pll3_sw_clk;
 static struct clk *pll2_200;
 static struct clk *mmdc_ch0_axi;
+struct regulator *vddsoc_cap_regulator;
 
 static struct delayed_work low_bus_freq_handler;
 
 static void reduce_bus_freq_handler(struct work_struct *work)
 {
-	unsigned long reg;
+	int ret = 0;
 
 	if (low_bus_freq_mode || !low_freq_bus_used())
 		return;
@@ -152,6 +151,17 @@ static void reduce_bus_freq_handler(struct work_struct *work)
 			clk_disable(pll2_400);
 		clk_disable(pll3);
 	} else {
+		/* Set VDDSOC_CAP to 1.1V */
+		ret = regulator_set_voltage(vddsoc_cap_regulator, 1100000,
+					    1100000);
+		if (ret < 0) {
+			printk(KERN_DEBUG
+			       "COULD NOT DECREASE VDDSOC_CAP VOLTAGE!!!!\n");
+			return;
+		}
+
+		udelay(150);
+
 		/* Set periph_clk to be sourced from OSC_CLK */
 		/* Set MMDC clk to 25MHz. */
 		/* First need to set the divider before changing the parent */
@@ -175,48 +185,8 @@ static void reduce_bus_freq_handler(struct work_struct *work)
 	high_bus_freq_mode = 0;
 	med_bus_freq_mode = 0;
 
-	/* Do not disable PU LDO if it is not enabled */
-	reg = __raw_readl(ANADIG_REG_CORE) & (ANADIG_REG_TARGET_MASK << ANADIG_REG1_PU_TARGET_OFFSET);
-	if ((low_bus_freq_mode || audio_bus_freq_mode) && reg != 0) {
-		/* Disable the brown out detection since we are going to be
-		  * disabling the LDO.
-		  */
-		reg = __raw_readl(ANA_MISC2_BASE_ADDR);
-		reg &= ~ANADIG_ANA_MISC2_REG1_BO_EN;
-		__raw_writel(reg, ANA_MISC2_BASE_ADDR);
-
-		/* Power gate the PU LDO. */
-		/* Power gate the PU domain first. */
-		/* enable power down request */
-		reg = __raw_readl(gpc_base + GPC_PGC_GPU_PGCR_OFFSET);
-		__raw_writel(reg | 0x1, gpc_base + GPC_PGC_GPU_PGCR_OFFSET);
-		/* power down request */
-		reg = __raw_readl(gpc_base + GPC_CNTR_OFFSET);
-		__raw_writel(reg | 0x1, gpc_base + GPC_CNTR_OFFSET);
-		/* Wait for power down to complete. */
-		while (__raw_readl(gpc_base + GPC_CNTR_OFFSET) & 0x1)
-			;
-
-		/* Mask the ANATOP brown out interrupt in the GPC. */
-		reg = __raw_readl(gpc_base + 0x14);
-		reg |= 0x80000000;
-		__raw_writel(reg, gpc_base + 0x14);
-
-		/* PU power gating. */
-		reg = __raw_readl(ANADIG_REG_CORE);
-		org_ldo = reg & (ANADIG_REG_TARGET_MASK << ANADIG_REG1_PU_TARGET_OFFSET);
-		reg &= ~(ANADIG_REG_TARGET_MASK << ANADIG_REG1_PU_TARGET_OFFSET);
-		__raw_writel(reg, ANADIG_REG_CORE);
-
-		/* Clear the BO interrupt in the ANATOP. */
-		reg = __raw_readl(ANADIG_MISC1_REG);
-		reg |= 0x80000000;
-		__raw_writel(reg, ANADIG_MISC1_REG);
-	}
-
 	mutex_unlock(&bus_freq_mutex);
 }
-
 /* Set the DDR, AHB to 24MHz.
   * This mode will be activated only when none of the modules that
   * need a higher DDR or AHB frequency are active.
@@ -241,7 +211,7 @@ int set_low_bus_freq(void)
  */
 int set_high_bus_freq(int high_bus_freq)
 {
-	unsigned long reg;
+	int ret = 0;
 
 	if (busfreq_suspended)
 		return 0;
@@ -255,6 +225,12 @@ int set_high_bus_freq(int high_bus_freq)
 	if (med_bus_freq_mode && !high_bus_freq)
 		return 0;
 
+	if (cpu_is_mx6dl() && high_bus_freq)
+		high_bus_freq = 0;
+
+	if (cpu_is_mx6dl() && med_bus_freq_mode)
+		return 0;
+
 	while (!mutex_trylock(&bus_freq_mutex))
 		msleep(1);
 
@@ -265,11 +241,15 @@ int set_high_bus_freq(int high_bus_freq)
 		return 0;
 	}
 
-	/* Enable the PU LDO */
-	if (low_bus_freq_mode || audio_bus_freq_mode) {
-		/* Set the voltage of VDDPU as in normal mode. */
-		__raw_writel(org_ldo | (__raw_readl(ANADIG_REG_CORE) &
-		(~(ANADIG_REG_TARGET_MASK << ANADIG_REG1_PU_TARGET_OFFSET))), ANADIG_REG_CORE);
+	if (cpu_is_mx6sl()) {
+		/* Set the voltage of VDDSOC to 1.2V as in normal mode. */
+		ret = regulator_set_voltage(vddsoc_cap_regulator, 1200000,
+					    1200000);
+		if (ret < 0) {
+			printk(KERN_DEBUG
+			       "COULD NOT INCREASE VDDSOC_CAP VOLTAGE!!!!\n");
+			return ret;
+		}
 
 		/* Need to wait for the regulator to come back up */
 		/*
@@ -279,52 +259,27 @@ int set_high_bus_freq(int high_bus_freq)
 		 */
 		udelay(150);
 
-		/* enable power up request */
-		reg = __raw_readl(gpc_base + GPC_PGC_GPU_PGCR_OFFSET);
-		__raw_writel(reg | 0x1, gpc_base + GPC_PGC_GPU_PGCR_OFFSET);
-		/* power up request */
-		reg = __raw_readl(gpc_base + GPC_CNTR_OFFSET);
-		__raw_writel(reg | 0x2, gpc_base + GPC_CNTR_OFFSET);
-		/* Wait for the power up bit to clear */
-		while (__raw_readl(gpc_base + GPC_CNTR_OFFSET) & 0x2)
-			;
-
-		/* Enable the Brown Out detection. */
-		reg = __raw_readl(ANA_MISC2_BASE_ADDR);
-		reg |= ANADIG_ANA_MISC2_REG1_BO_EN;
-		__raw_writel(reg, ANA_MISC2_BASE_ADDR);
-
-		/* Unmask the ANATOP brown out interrupt in the GPC. */
-		reg = __raw_readl(gpc_base + 0x14);
-		reg &= ~0x80000000;
-		__raw_writel(reg, gpc_base + 0x14);
-
-		if (cpu_is_mx6sl()) {
-			/* Set periph_clk to be sourced from pll2_pfd2_400M */
-			/* First need to set the divider before changing the */
-			/* parent if parent clock is larger than previous one */
-			clk_set_rate(ahb_clk, clk_round_rate(ahb_clk,
-							     LPAPM_CLK / 3));
-			clk_set_rate(axi_clk,
-				     clk_round_rate(axi_clk, LPAPM_CLK / 2));
-			clk_set_parent(periph_clk, pll2_400);
-
-			/* Set mmdc_clk_root to be sourced */
-			/* from pll2_pfd2_400M */
-			clk_set_rate(mmdc_ch0_axi,
-				     clk_round_rate(mmdc_ch0_axi,
-						    LPAPM_CLK / 2));
-			clk_set_parent(mmdc_ch0_axi, pll3_sw_clk);
-			clk_set_parent(mmdc_ch0_axi, pll2_400);
-			clk_set_rate(mmdc_ch0_axi,
-				     clk_round_rate(mmdc_ch0_axi, DDR_MED_CLK));
-
-			high_bus_freq_mode = 1;
-			med_bus_freq_mode = 0;
-		}
-	}
+		/* Set periph_clk to be sourced from pll2_pfd2_400M */
+		/* First need to set the divider before changing the */
+		/* parent if parent clock is larger than previous one */
+		clk_set_rate(ahb_clk, clk_round_rate(ahb_clk,
+						     LPAPM_CLK / 3));
+		clk_set_rate(axi_clk,
+			     clk_round_rate(axi_clk, LPAPM_CLK / 2));
+		clk_set_parent(periph_clk, pll2_400);
+
+		/* Set mmdc_clk_root to be sourced */
+		/* from pll2_pfd2_400M */
+		clk_set_rate(mmdc_ch0_axi,
+		     clk_round_rate(mmdc_ch0_axi, LPAPM_CLK / 2));
+		clk_set_parent(mmdc_ch0_axi, pll3_sw_clk);
+		clk_set_parent(mmdc_ch0_axi, pll2_400);
+		clk_set_rate(mmdc_ch0_axi,
+		     clk_round_rate(mmdc_ch0_axi, DDR_MED_CLK));
 
-	if (!cpu_is_mx6sl()) {
+		high_bus_freq_mode = 1;
+		med_bus_freq_mode = 0;
+	} else {
 		clk_enable(pll3);
 		if (high_bus_freq) {
 			update_ddr_freq(ddr_normal_rate);
@@ -355,7 +310,6 @@ int set_high_bus_freq(int high_bus_freq)
 	return 0;
 }
 
-
 int low_freq_bus_used(void)
 {
 	if (!bus_freq_scaling_initialized)
@@ -411,8 +365,7 @@ static ssize_t bus_freq_scaling_enable_store(struct device *dev,
 
 static int busfreq_suspend(struct platform_device *pdev, pm_message_t message)
 {
-	if (low_bus_freq_mode || audio_bus_freq_mode)
-		set_high_bus_freq(1);
+	set_high_bus_freq(1);
 	busfreq_suspended = 1;
 	return 0;
 }
@@ -517,6 +470,13 @@ static int __devinit busfreq_probe(struct platform_device *pdev)
 		return PTR_ERR(mmdc_ch0_axi);
 	}
 
+	vddsoc_cap_regulator = regulator_get(NULL, "cpu_vddsoc");
+	if (IS_ERR(vddsoc_cap_regulator)) {
+		printk(KERN_ERR "%s: failed to get vddsoc_cap regulator\n",
+				__func__);
+		return PTR_ERR(vddsoc_cap_regulator);
+	}
+
 	err = sysfs_create_file(&busfreq_dev->kobj, &dev_attr_enable.attr);
 	if (err) {
 		printk(KERN_ERR
@@ -526,8 +486,16 @@ static int __devinit busfreq_probe(struct platform_device *pdev)
 
 	cpu_op_tbl = get_cpu_op(&cpu_op_nr);
 	low_bus_freq_mode = 0;
-	high_bus_freq_mode = 1;
-	med_bus_freq_mode = 0;
+	if (cpu_is_mx6dl()) {
+		high_bus_freq_mode = 0;
+		med_bus_freq_mode = 1;
+		/* To make pll2_400 use count right, as when
+		system enter 24M, it will disable pll2_400 */
+		clk_enable(pll2_400);
+	} else {
+		high_bus_freq_mode = 1;
+		med_bus_freq_mode = 0;
+	}
 	bus_freq_scaling_is_active = 0;
 	bus_freq_scaling_initialized = 1;
 
@@ -575,18 +543,20 @@ static int __init busfreq_init(void)
 
 	printk(KERN_INFO "Bus freq driver module loaded\n");
 
-	if (cpu_is_mx6sl()) {
-		/* Enable busfreq by default. */
-		bus_freq_scaling_is_active = 1;
+	/* Enable busfreq by default. */
+	bus_freq_scaling_is_active = 1;
+
+	if (cpu_is_mx6q())
+		set_high_bus_freq(1);
+	else
 		set_high_bus_freq(0);
-		/* Make sure system can enter low bus mode if it should be in
-		low bus mode */
-		if (low_freq_bus_used() && !low_bus_freq_mode)
-			set_low_bus_freq();
 
-		printk(KERN_INFO "Bus freq driver Enabled\n");
-	}
+	/* Make sure system can enter low bus mode if it should be in
+	low bus mode */
+	if (low_freq_bus_used() && !low_bus_freq_mode)
+		set_low_bus_freq();
 
+	printk(KERN_INFO "Bus freq driver Enabled\n");
 	return 0;
 }
 
diff --git a/arch/arm/mach-mx6/clock.c b/arch/arm/mach-mx6/clock.c
index 3efb6b3e6378..600cd8b23414 100644
--- a/arch/arm/mach-mx6/clock.c
+++ b/arch/arm/mach-mx6/clock.c
@@ -1989,15 +1989,26 @@ static struct clk vdo_axi_clk = {
 	.set_parent = _clk_vdo_axi_set_parent,
 };
 
-static struct clk vdoa_clk = {
+static struct clk vdoa_clk[] = {
+	{
 	__INIT_CLK_DEBUG(vdoa_clk)
 	.id = 0,
 	.parent = &vdo_axi_clk,
-	.secondary = &ipg_clk,
 	.enable_reg = MXC_CCM_CCGR2,
 	.enable_shift = MXC_CCM_CCGRx_CG13_OFFSET,
 	.enable = _clk_enable,
 	.disable = _clk_disable,
+	.secondary = &vdoa_clk[1],
+	.flags = AHB_HIGH_SET_POINT | CPU_FREQ_TRIG_UPDATE,
+	},
+	{
+	.parent =  &mmdc_ch0_axi_clk[0],
+	.secondary = &vdoa_clk[2],
+	},
+	{
+	.parent =  &mx6fast1_clk,
+	.secondary = &ocram_clk,
+	},
 };
 
 static unsigned long _clk_gpt_get_rate(struct clk *clk)
@@ -4165,7 +4176,6 @@ static struct clk hdmi_clk[] = {
 	.enable_shift = MXC_CCM_CCGRx_CG2_OFFSET,
 	.enable = _clk_enable,
 	.disable = _clk_disable,
-	.flags = AHB_HIGH_SET_POINT | CPU_FREQ_TRIG_UPDATE,
 	},
 	{
 	 __INIT_CLK_DEBUG(hdmi_iahb_clk)
@@ -4187,7 +4197,6 @@ static struct clk caam_clk[] = {
 	.enable = _clk_enable,
 	.disable = _clk_disable,
 	.secondary = &caam_clk[1],
-	.flags = AHB_HIGH_SET_POINT | CPU_FREQ_TRIG_UPDATE,
 	},
 	{
 	 __INIT_CLK_DEBUG(caam_aclk_clk)
@@ -5247,7 +5256,7 @@ static struct clk_lookup lookups[] = {
 	_REGISTER_CLOCK(NULL, "hdmi_isfr_clk", hdmi_clk[0]),
 	_REGISTER_CLOCK(NULL, "hdmi_iahb_clk", hdmi_clk[1]),
 	_REGISTER_CLOCK(NULL, "mipi_pllref_clk", mipi_pllref_clk),
-	_REGISTER_CLOCK(NULL, "vdoa", vdoa_clk),
+	_REGISTER_CLOCK(NULL, "vdoa", vdoa_clk[0]),
 	_REGISTER_CLOCK(NULL, NULL, aips_tz2_clk),
 	_REGISTER_CLOCK(NULL, NULL, aips_tz1_clk),
 	_REGISTER_CLOCK(NULL, "clko_clk", clko_clk),
diff --git a/arch/arm/mach-mx6/clock_mx6sl.c b/arch/arm/mach-mx6/clock_mx6sl.c
index 42621f73dbbc..577a52277d68 100755
--- a/arch/arm/mach-mx6/clock_mx6sl.c
+++ b/arch/arm/mach-mx6/clock_mx6sl.c
@@ -3910,6 +3910,8 @@ static struct clk_lookup lookups[] = {
 	_REGISTER_CLOCK(NULL, "gpu2d_clk", gpu2d_core_clk),
 	_REGISTER_CLOCK(NULL, "gpu2d_axi_clk", gpu2d_axi_clk),
 	_REGISTER_CLOCK(NULL, "openvg_axi_clk", openvg_axi_clk),
+	_REGISTER_CLOCK(NULL, "rng_clk", dummy_clk),
+	_REGISTER_CLOCK(NULL, "dcp_clk", dummy_clk),
 };
 
 static void clk_tree_init(void)
diff --git a/arch/arm/mach-mx6/cpu.c b/arch/arm/mach-mx6/cpu.c
index 651b1ffd4344..5d9749653988 100644
--- a/arch/arm/mach-mx6/cpu.c
+++ b/arch/arm/mach-mx6/cpu.c
@@ -60,6 +60,8 @@ static int mx6_get_srev(void)
 		return IMX_CHIP_REVISION_1_0;
 	else if (rev == 1)
 		return IMX_CHIP_REVISION_1_1;
+	else if (rev == 2)
+		return IMX_CHIP_REVISION_1_2;
 
 	return IMX_CHIP_REVISION_UNKNOWN;
 }
diff --git a/arch/arm/mach-mx6/crm_regs.h b/arch/arm/mach-mx6/crm_regs.h
index c99caad1e776..2e1f3e4a32c4 100644
--- a/arch/arm/mach-mx6/crm_regs.h
+++ b/arch/arm/mach-mx6/crm_regs.h
@@ -121,6 +121,7 @@
 #define ANADIG_PLL_ENET_POWER_DOWN		(1 << 12)
 #define ANADIG_PLL_ENET_DIV_SELECT_MASK		(0x3)
 #define ANADIG_PLL_ENET_DIV_SELECT_OFFSET	(0)
+#define ANATOP_BYPASS_SRC_LVDS1         0x00004000
 
 /* PFD register defines. */
 #define ANADIG_PFD_FRAC_MASK			0x3F
diff --git a/arch/arm/mach-mx6/devices-imx6q.h b/arch/arm/mach-mx6/devices-imx6q.h
index 3255cf79decf..105e1f6d0a0e 100644
--- a/arch/arm/mach-mx6/devices-imx6q.h
+++ b/arch/arm/mach-mx6/devices-imx6q.h
@@ -246,3 +246,13 @@ extern const struct imx_pcie_data imx6q_pcie_data __initconst;
 extern const struct imx_imx_keypad_data imx6sl_imx_keypad_data;
 #define imx6sl_add_imx_keypad(pdata)	\
 	imx_add_imx_keypad(&imx6sl_imx_keypad_data, pdata)
+
+extern const struct imx_dcp_data imx6sl_dcp_data __initconst;
+#define imx6sl_add_dcp() \
+	imx_add_dcp(&imx6sl_dcp_data);
+
+extern const struct imx_rngb_data imx6sl_rngb_data __initconst;
+#define imx6sl_add_rngb() \
+	imx_add_rngb(&imx6sl_rngb_data);
+
+#define imx6_add_armpmu() imx_add_imx_armpmu()
diff --git a/arch/arm/mach-mx6/mx6_anatop_regulator.c b/arch/arm/mach-mx6/mx6_anatop_regulator.c
index fd7e0c3fbdee..06755dc7a4ee 100644
--- a/arch/arm/mach-mx6/mx6_anatop_regulator.c
+++ b/arch/arm/mach-mx6/mx6_anatop_regulator.c
@@ -34,9 +34,15 @@
 #include "crm_regs.h"
 #include "regs-anadig.h"
 
+#define GPC_PGC_GPU_PGCR_OFFSET	0x260
+#define GPC_CNTR_OFFSET		0x0
+
 extern struct platform_device sgtl5000_vdda_reg_devices;
 extern struct platform_device sgtl5000_vddio_reg_devices;
 extern struct platform_device sgtl5000_vddd_reg_devices;
+extern void __iomem *gpc_base;
+/* Default PU voltage value set to 1.1V */
+static unsigned int org_ldo = 0x2000;
 
 static int get_voltage(struct anatop_regulator *sreg)
 {
@@ -82,6 +88,108 @@ static int set_voltage(struct anatop_regulator *sreg, int uv)
 	}
 }
 
+static int pu_enable(struct anatop_regulator *sreg)
+{
+	unsigned int reg;
+
+	/* Do not enable PU LDO if it is already enabled */
+	reg = __raw_readl(ANADIG_REG_CORE) & (ANADIG_REG_TARGET_MASK
+		<< ANADIG_REG1_PU_TARGET_OFFSET);
+	if (reg != 0)
+		return 0;
+
+	/* Set the voltage of VDDPU as in normal mode. */
+	__raw_writel(org_ldo | (__raw_readl(ANADIG_REG_CORE) &
+	(~(ANADIG_REG_TARGET_MASK << ANADIG_REG1_PU_TARGET_OFFSET))), ANADIG_REG_CORE);
+
+	/* Need to wait for the regulator to come back up */
+	/*
+	 * Delay time is based on the number of 24MHz clock cycles
+	 * programmed in the ANA_MISC2_BASE_ADDR for each
+	 * 25mV step.
+	 */
+	udelay(150);
+
+	/* enable power up request */
+	reg = __raw_readl(gpc_base + GPC_PGC_GPU_PGCR_OFFSET);
+	__raw_writel(reg | 0x1, gpc_base + GPC_PGC_GPU_PGCR_OFFSET);
+	/* power up request */
+	reg = __raw_readl(gpc_base + GPC_CNTR_OFFSET);
+	__raw_writel(reg | 0x2, gpc_base + GPC_CNTR_OFFSET);
+	/* Wait for the power up bit to clear */
+	while (__raw_readl(gpc_base + GPC_CNTR_OFFSET) & 0x2)
+		;
+
+	/* Enable the Brown Out detection. */
+	reg = __raw_readl(ANA_MISC2_BASE_ADDR);
+	reg |= ANADIG_ANA_MISC2_REG1_BO_EN;
+	__raw_writel(reg, ANA_MISC2_BASE_ADDR);
+
+	/* Unmask the ANATOP brown out interrupt in the GPC. */
+	reg = __raw_readl(gpc_base + 0x14);
+	reg &= ~0x80000000;
+	__raw_writel(reg, gpc_base + 0x14);
+
+	return 0;
+}
+
+static int pu_disable(struct anatop_regulator *sreg)
+{
+	unsigned int reg;
+
+	/* Do not disable PU LDO if it is not enabled */
+	reg = __raw_readl(ANADIG_REG_CORE) & (ANADIG_REG_TARGET_MASK
+		<< ANADIG_REG1_PU_TARGET_OFFSET);
+	if (reg == 0)
+		return 0;
+
+	/* Disable the brown out detection since we are going to be
+	  * disabling the LDO.
+	  */
+	reg = __raw_readl(ANA_MISC2_BASE_ADDR);
+	reg &= ~ANADIG_ANA_MISC2_REG1_BO_EN;
+	__raw_writel(reg, ANA_MISC2_BASE_ADDR);
+
+	/* Power gate the PU LDO. */
+	/* Power gate the PU domain first. */
+	/* enable power down request */
+	reg = __raw_readl(gpc_base + GPC_PGC_GPU_PGCR_OFFSET);
+	__raw_writel(reg | 0x1, gpc_base + GPC_PGC_GPU_PGCR_OFFSET);
+	/* power down request */
+	reg = __raw_readl(gpc_base + GPC_CNTR_OFFSET);
+	__raw_writel(reg | 0x1, gpc_base + GPC_CNTR_OFFSET);
+	/* Wait for power down to complete. */
+	while (__raw_readl(gpc_base + GPC_CNTR_OFFSET) & 0x1)
+			;
+
+	/* Mask the ANATOP brown out interrupt in the GPC. */
+	reg = __raw_readl(gpc_base + 0x14);
+	reg |= 0x80000000;
+	__raw_writel(reg, gpc_base + 0x14);
+
+	/* PU power gating. */
+	reg = __raw_readl(ANADIG_REG_CORE);
+	org_ldo = reg & (ANADIG_REG_TARGET_MASK << ANADIG_REG1_PU_TARGET_OFFSET);
+	reg &= ~(ANADIG_REG_TARGET_MASK << ANADIG_REG1_PU_TARGET_OFFSET);
+	__raw_writel(reg, ANADIG_REG_CORE);
+
+	/* Clear the BO interrupt in the ANATOP. */
+	reg = __raw_readl(ANADIG_MISC1_REG);
+	reg |= 0x80000000;
+	__raw_writel(reg, ANADIG_MISC1_REG);
+	return 0;
+}
+static int is_pu_enabled(struct anatop_regulator *sreg)
+{
+	unsigned int reg;
+
+	reg = __raw_readl(ANADIG_REG_CORE) & (ANADIG_REG_TARGET_MASK
+		<< ANADIG_REG1_PU_TARGET_OFFSET);
+	if (reg == 0)
+		return 0;
+	else
+		return 1;
+}
 static int enable(struct anatop_regulator *sreg)
 {
 	return 0;
@@ -101,9 +209,9 @@ static struct anatop_regulator_data vddpu_data = {
 	.name		= "vddpu",
 	.set_voltage	= set_voltage,
 	.get_voltage	= get_voltage,
-	.enable		= enable,
-	.disable	= disable,
-	.is_enabled	= is_enabled,
+	.enable		= pu_enable,
+	.disable	= pu_disable,
+	.is_enabled	= is_pu_enabled,
 	.control_reg	= (u32)(MXC_PLL_BASE + HW_ANADIG_REG_CORE),
 	.vol_bit_shift	= 9,
 	.vol_bit_mask	= 0x1F,
@@ -193,6 +301,21 @@ static struct regulator_consumer_supply vddcore_consumers[] = {
 		.supply = "cpu_vddgp",
 	}
 };
+/* PU */
+static struct regulator_consumer_supply vddpu_consumers[] = {
+	{
+		.supply = "cpu_vddvpu",
+	},
+	{
+		.supply = "cpu_vddgpu",
+	}
+};
+/* SOC */
+static struct regulator_consumer_supply vddsoc_consumers[] = {
+	{
+		.supply = "cpu_vddsoc",
+	},
+};
 
 static struct regulator_init_data vddpu_init = {
 	.constraints = {
@@ -202,11 +325,11 @@ static struct regulator_init_data vddpu_init = {
 		.valid_modes_mask	= REGULATOR_MODE_FAST |
 					  REGULATOR_MODE_NORMAL,
 		.valid_ops_mask		= REGULATOR_CHANGE_VOLTAGE |
+					  REGULATOR_CHANGE_STATUS |
 					  REGULATOR_CHANGE_MODE,
-		.always_on		= 1,
 	},
-	.num_consumer_supplies = 0,
-	.consumer_supplies = NULL,
+	.num_consumer_supplies = ARRAY_SIZE(vddpu_consumers),
+	.consumer_supplies = vddpu_consumers,
 };
 
 static struct regulator_init_data vddcore_init = {
@@ -235,8 +358,8 @@ static struct regulator_init_data vddsoc_init = {
 					  REGULATOR_CHANGE_MODE,
 		.always_on		= 1,
 	},
-	.num_consumer_supplies = 0,
-	.consumer_supplies = NULL,
+	.num_consumer_supplies = ARRAY_SIZE(vddsoc_consumers),
+	.consumer_supplies = &vddsoc_consumers[0],
 };
 
 static struct regulator_init_data vdd2p5_init = {
diff --git a/arch/arm/mach-mx6/pcie.c b/arch/arm/mach-mx6/pcie.c
index 38e9abcd29cc..f39dd3d4314b 100644
--- a/arch/arm/mach-mx6/pcie.c
+++ b/arch/arm/mach-mx6/pcie.c
@@ -606,6 +606,7 @@ static void imx_pcie_enable_controller(struct device *dev)
 		pr_err("can't enable pcie clock.\n");
 		clk_put(pcie_clk);
 	}
+	imx_pcie_clrset(iomuxc_gpr1_pcie_ref_clk_en, 1 << 16, IOMUXC_GPR1);
 }
 
 static void card_reset(struct device *dev)
@@ -652,6 +653,9 @@ static void __init add_pcie_port(void __iomem *base, void __iomem *dbi_base,
 		clk_disable(pcie_clk);
 		clk_put(pcie_clk);
 
+		imx_pcie_clrset(iomuxc_gpr1_pcie_ref_clk_en, 0 << 16,
+				IOMUXC_GPR1);
+
 		/* Disable PCIE power */
 		gpio_request(pdata->pcie_pwr_en, "PCIE POWER_EN");
 
@@ -669,7 +673,6 @@ static int __devinit imx_pcie_pltfm_probe(struct platform_device *pdev)
 	struct device *dev = &pdev->dev;
 	struct imx_pcie_platform_data *pdata = dev->platform_data;
 
-
 	mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 	if (!mem) {
 		dev_err(dev, "no mmio space\n");
@@ -698,15 +701,13 @@ static int __devinit imx_pcie_pltfm_probe(struct platform_device *pdev)
 
 	imx_pcie_clrset(iomuxc_gpr8_tx_deemph_gen1, 0 << 0, IOMUXC_GPR8);
 	imx_pcie_clrset(iomuxc_gpr8_tx_deemph_gen2_3p5db, 0 << 6, IOMUXC_GPR8);
-	imx_pcie_clrset(iomuxc_gpr8_tx_deemph_gen2_6db, 0 << 12, IOMUXC_GPR8);
+	imx_pcie_clrset(iomuxc_gpr8_tx_deemph_gen2_6db, 20 << 12, IOMUXC_GPR8);
 	imx_pcie_clrset(iomuxc_gpr8_tx_swing_full, 127 << 18, IOMUXC_GPR8);
 	imx_pcie_clrset(iomuxc_gpr8_tx_swing_low, 127 << 25, IOMUXC_GPR8);
 
 	/* Enable the pwr, clks and so on */
 	imx_pcie_enable_controller(dev);
 
-	imx_pcie_clrset(iomuxc_gpr1_pcie_ref_clk_en, 1 << 16, IOMUXC_GPR1);
-
 	/* togle the external card's reset */
 	card_reset(dev) ;
 
@@ -714,13 +715,6 @@ static int __devinit imx_pcie_pltfm_probe(struct platform_device *pdev)
 	imx_pcie_regions_setup(dbi_base);
 	usleep_range(3000, 4000);
 
-	/*
-	 * Force to GEN1 because of PCIE2USB storage stress tests
-	 * would be failed when GEN2 is enabled
-	 */
-	writel(((readl(dbi_base + LNK_CAP) & 0xfffffff0) | 0x1),
-			dbi_base + LNK_CAP);
-
 	/* start link up */
 	imx_pcie_clrset(iomuxc_gpr12_app_ltssm_enable, 1 << 10, IOMUXC_GPR12);
 
@@ -749,6 +743,8 @@ static int __devexit imx_pcie_pltfm_remove(struct platform_device *pdev)
 		clk_put(pcie_clk);
 	}
 
+	imx_pcie_clrset(iomuxc_gpr1_pcie_ref_clk_en, 0 << 16, IOMUXC_GPR1);
+
 	/* Disable PCIE power */
 	gpio_request(pdata->pcie_pwr_en, "PCIE POWER_EN");
 
diff --git a/arch/arm/mach-mx6/system.c b/arch/arm/mach-mx6/system.c
index d16b1eff6cbe..b9efbb64c8f9 100644
--- a/arch/arm/mach-mx6/system.c
+++ b/arch/arm/mach-mx6/system.c
@@ -49,8 +49,6 @@
 
 extern unsigned int gpc_wake_irq[4];
 
-static unsigned int cpu_idle_mask;
-
 static void __iomem *gpc_base = IO_ADDRESS(GPC_BASE_ADDR);
 
 int wait_mode_arm_podf;