diff options
| author | Anson Huang <b20788@freescale.com> | 2012-02-20 10:44:35 +0800 |
|---|---|---|
| committer | Anson Huang <b20788@freescale.com> | 2012-02-20 11:58:19 +0800 |
| commit | 9ad4134a37199519e2083a1cc8cd1d0a64aff8c8 (patch) | |
| tree | 2b006e66e5b293eac4240161764e730d1c56b5db /arch/arm/mach-mx6 | |
| parent | 5c84e33e2f4f9125789517c0767e659a05d6cb13 (diff) | |
ENGR00174824 [MX6]Add workaround for i.MX6DL suspend/resume
To keep i.MX6DL resume work stably, need to open LDO on based
on the current codes.Will continue to optimize power in suspend
state in future codes.
Signed-off-by: Anson Huang <b20788@freescale.com>
Diffstat (limited to 'arch/arm/mach-mx6')
| -rw-r--r-- | arch/arm/mach-mx6/system.c | 29 |
1 files changed, 16 insertions, 13 deletions
diff --git a/arch/arm/mach-mx6/system.c b/arch/arm/mach-mx6/system.c index 185be00db482..0eb6592969dd 100644 --- a/arch/arm/mach-mx6/system.c +++ b/arch/arm/mach-mx6/system.c @@ -125,22 +125,25 @@ void mxc_cpu_lp_set(enum mxc_cpu_pwr_mode mode) __raw_writel(0x1, gpc_base + GPC_PGC_CPU_PDN_OFFSET); __raw_writel(0x1, gpc_base + GPC_PGC_GPU_PGCR_OFFSET); __raw_writel(0x1, gpc_base + GPC_CNTR_OFFSET); - /* Enable weak 2P5 linear regulator */ - anatop_val = __raw_readl(anatop_base + - HW_ANADIG_REG_2P5); - anatop_val |= BM_ANADIG_REG_2P5_ENABLE_WEAK_LINREG; - __raw_writel(anatop_val, anatop_base + - HW_ANADIG_REG_2P5); - if (mx6q_revision() != IMX_CHIP_REVISION_1_0) { - /* Enable fet_odrive */ + if (cpu_is_mx6q()) { + /* Enable weak 2P5 linear regulator */ anatop_val = __raw_readl(anatop_base + - HW_ANADIG_REG_CORE); - anatop_val |= BM_ANADIG_REG_CORE_FET_ODRIVE; + HW_ANADIG_REG_2P5); + anatop_val |= BM_ANADIG_REG_2P5_ENABLE_WEAK_LINREG; __raw_writel(anatop_val, anatop_base + - HW_ANADIG_REG_CORE); + HW_ANADIG_REG_2P5); + if (mx6q_revision() != IMX_CHIP_REVISION_1_0) { + /* Enable fet_odrive */ + anatop_val = __raw_readl(anatop_base + + HW_ANADIG_REG_CORE); + anatop_val |= BM_ANADIG_REG_CORE_FET_ODRIVE; + __raw_writel(anatop_val, anatop_base + + HW_ANADIG_REG_CORE); + } } - __raw_writel(__raw_readl(MXC_CCM_CCR) | - MXC_CCM_CCR_RBC_EN, MXC_CCM_CCR); + if (cpu_is_mx6q()) + __raw_writel(__raw_readl(MXC_CCM_CCR) | + MXC_CCM_CCR_RBC_EN, MXC_CCM_CCR); /* Make sure we clear WB_COUNT and re-config it */ __raw_writel(__raw_readl(MXC_CCM_CCR) & (~MXC_CCM_CCR_WB_COUNT_MASK), MXC_CCM_CCR); |