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authorPaul Walmsley <paul@pwsan.com>2012-09-23 17:16:04 -0600
committerPaul Walmsley <paul@pwsan.com>2012-09-23 17:16:04 -0600
commit1e2ee2a60df5c3ab74dd1c9155fb01b5bc6f807d (patch)
tree2adb98096c4a6dec0ceff4e7e04610a079f14026 /arch/arm/mach-omap2/clkt_dpll.c
parent291852e8791a596195edc3ced96481bfd105f35b (diff)
parent11964f53eb4d9ce59a058be9999d9cfcb1ced878 (diff)
Merge tag 'omap-devel-am33xx-for-v3.7' into test_v3.6-rc6_ocb3.7_cff3.7_odaf3.7
From Paul Walmsley <paul@pwsan.com>: AM33xx hwmod data and miscellaneous clock and hwmod fixes. AM33xx should now boot on mainline after this is applied, according to Vaibhav.
Diffstat (limited to 'arch/arm/mach-omap2/clkt_dpll.c')
-rw-r--r--arch/arm/mach-omap2/clkt_dpll.c4
1 files changed, 2 insertions, 2 deletions
diff --git a/arch/arm/mach-omap2/clkt_dpll.c b/arch/arm/mach-omap2/clkt_dpll.c
index a3b60c7b9aa8..83b658bf385a 100644
--- a/arch/arm/mach-omap2/clkt_dpll.c
+++ b/arch/arm/mach-omap2/clkt_dpll.c
@@ -211,7 +211,7 @@ void omap2_init_dpll_parent(struct clk *clk)
if (v == OMAP3XXX_EN_DPLL_LPBYPASS ||
v == OMAP3XXX_EN_DPLL_FRBYPASS)
clk_reparent(clk, dd->clk_bypass);
- } else if (cpu_is_omap44xx()) {
+ } else if (soc_is_am33xx() || cpu_is_omap44xx()) {
if (v == OMAP4XXX_EN_DPLL_LPBYPASS ||
v == OMAP4XXX_EN_DPLL_FRBYPASS ||
v == OMAP4XXX_EN_DPLL_MNBYPASS)
@@ -257,7 +257,7 @@ u32 omap2_get_dpll_rate(struct clk *clk)
if (v == OMAP3XXX_EN_DPLL_LPBYPASS ||
v == OMAP3XXX_EN_DPLL_FRBYPASS)
return dd->clk_bypass->rate;
- } else if (cpu_is_omap44xx()) {
+ } else if (soc_is_am33xx() || cpu_is_omap44xx()) {
if (v == OMAP4XXX_EN_DPLL_LPBYPASS ||
v == OMAP4XXX_EN_DPLL_FRBYPASS ||
v == OMAP4XXX_EN_DPLL_MNBYPASS)