diff options
author | Rajendra Nayak <rnayak@ti.com> | 2012-04-27 15:53:48 +0530 |
---|---|---|
committer | Paul Walmsley <paul@pwsan.com> | 2012-11-12 19:10:18 -0700 |
commit | b4777a21381fd1f87be8c606a616b7f97f485d2b (patch) | |
tree | af45be72d14dde6fc899ac2ad5f9984f1bfa5cd5 /arch/arm/mach-omap2/clock36xx.c | |
parent | 32cc002116b866151ca24c6e9110ba8a93754753 (diff) |
ARM: OMAP3: clock: Convert to common clk
Convert all OMAP3 specific platform files to use COMMON clk
and keep all the changes under the CONFIG_COMMON_CLK macro check
so it does not break any existing code. At a later point switch
to COMMON clk and get rid of all old/legacy code.
Signed-off-by: Rajendra Nayak <rnayak@ti.com>
Signed-off-by: Mike Turquette <mturquette@ti.com>
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Diffstat (limited to 'arch/arm/mach-omap2/clock36xx.c')
-rw-r--r-- | arch/arm/mach-omap2/clock36xx.c | 25 |
1 files changed, 21 insertions, 4 deletions
diff --git a/arch/arm/mach-omap2/clock36xx.c b/arch/arm/mach-omap2/clock36xx.c index 0e1e9e4e2fa4..9f50e9704891 100644 --- a/arch/arm/mach-omap2/clock36xx.c +++ b/arch/arm/mach-omap2/clock36xx.c @@ -37,34 +37,51 @@ * (Any other value different from the Read value) to the * corresponding CM_CLKSEL register will refresh the dividers. */ +#ifdef CONFIG_COMMON_CLK +int omap36xx_pwrdn_clk_enable_with_hsdiv_restore(struct clk_hw *clk) +{ + struct clk_hw_omap *parent; + struct clk_hw *parent_hw; +#else static int omap36xx_pwrdn_clk_enable_with_hsdiv_restore(struct clk *clk) { + struct clk *parent; +#endif u32 dummy_v, orig_v, clksel_shift; int ret; /* Clear PWRDN bit of HSDIVIDER */ ret = omap2_dflt_clk_enable(clk); +#ifdef CONFIG_COMMON_CLK + parent_hw = __clk_get_hw(__clk_get_parent(clk->clk)); + parent = to_clk_hw_omap(parent_hw); +#else + parent = clk->parent; +#endif + /* Restore the dividers */ if (!ret) { - clksel_shift = __ffs(clk->parent->clksel_mask); - orig_v = __raw_readl(clk->parent->clksel_reg); + clksel_shift = __ffs(parent->clksel_mask); + orig_v = __raw_readl(parent->clksel_reg); dummy_v = orig_v; /* Write any other value different from the Read value */ dummy_v ^= (1 << clksel_shift); - __raw_writel(dummy_v, clk->parent->clksel_reg); + __raw_writel(dummy_v, parent->clksel_reg); /* Write the original divider */ - __raw_writel(orig_v, clk->parent->clksel_reg); + __raw_writel(orig_v, parent->clksel_reg); } return ret; } +#ifndef CONFIG_COMMON_CLK const struct clkops clkops_omap36xx_pwrdn_with_hsdiv_wait_restore = { .enable = omap36xx_pwrdn_clk_enable_with_hsdiv_restore, .disable = omap2_dflt_clk_disable, .find_companion = omap2_clk_dflt_find_companion, .find_idlest = omap2_clk_dflt_find_idlest, }; +#endif |