summaryrefslogtreecommitdiff
path: root/arch/arm/mach-omap2
diff options
context:
space:
mode:
authorAndrii Tseglytskyi <andrii.tseglytskyi@ti.com>2014-05-16 05:45:58 -0500
committerTero Kristo <t-kristo@ti.com>2014-06-06 20:33:38 +0300
commitce369a545aac3da653dd95d8117093a862bf94d3 (patch)
treeb9e2bf7e4ee27f8c09c7116af9ed0c4776bbee52 /arch/arm/mach-omap2
parent81c7e03acbcb68274be770134f8f04f270ffa859 (diff)
ARM: OMAP5+: dpll: support Duty Cycle Correction(DCC)
Duty Cycle Correction(DCC) needs to be enabled if the MPU is to run at frequencies beyond 1.4GHz for OMAP5, DRA75x, DRA72x. MPU DPLL has a limitation on the maximum frequency it can be locked at. Duty Cycle Correction circuit is used to recover a correct duty cycle for achieving higher frequencies (hardware internally switches output to M3 output(CLKOUTHIF) from M2 output (CLKOUT)). For further information, See the note on OMAP5432 Technical Reference Manual(SWPU282U) chapter 3.6.3.3.1 "DPLLs Output Clocks Parameters", and also the "OMAP543x ES2.0 DM Operating Conditions Addendum v0.5" chapter 2.1 "Micro Processor Unit (MPU)". Equivalent information is present in relevant DRA75x, 72x documentation(SPRUHP2E, SPRUHI2P). Signed-off-by: Andrii Tseglytskyi <andrii.tseglytskyi@ti.com> Signed-off-by: Taras Kondratiuk <taras@ti.com> Signed-off-by: J Keerthy <j-keerthy@ti.com> Signed-off-by: Nishanth Menon <nm@ti.com> [t-kristo@ti.com: added TRM / DM references for DCC clock rate] Signed-off-by: Tero Kristo <t-kristo@ti.com>
Diffstat (limited to 'arch/arm/mach-omap2')
-rw-r--r--arch/arm/mach-omap2/dpll3xxx.c9
1 files changed, 9 insertions, 0 deletions
diff --git a/arch/arm/mach-omap2/dpll3xxx.c b/arch/arm/mach-omap2/dpll3xxx.c
index fcd8036af910..6d7ba37e2257 100644
--- a/arch/arm/mach-omap2/dpll3xxx.c
+++ b/arch/arm/mach-omap2/dpll3xxx.c
@@ -319,6 +319,15 @@ static int omap3_noncore_dpll_program(struct clk_hw_omap *clk, u16 freqsel)
/* Set DPLL multiplier, divider */
v = omap2_clk_readl(clk, dd->mult_div1_reg);
+
+ /* Handle Duty Cycle Correction */
+ if (dd->dcc_mask) {
+ if (dd->last_rounded_rate >= dd->dcc_rate)
+ v |= dd->dcc_mask; /* Enable DCC */
+ else
+ v &= ~dd->dcc_mask; /* Disable DCC */
+ }
+
v &= ~(dd->mult_mask | dd->div1_mask);
v |= dd->last_rounded_m << __ffs(dd->mult_mask);
v |= (dd->last_rounded_n - 1) << __ffs(dd->div1_mask);