diff options
| author | Catalin Marinas <catalin.marinas@arm.com> | 2007-02-14 19:14:56 +0100 |
|---|---|---|
| committer | Russell King <rmk+kernel@arm.linux.org.uk> | 2007-02-15 14:44:10 +0000 |
| commit | b3a1bde4db9889feb116330bff21214811c940e4 (patch) | |
| tree | 6b8174332407ac8f4d2c5f6445912b935ff06110 /arch/arm/mach-realview/platsmp.c | |
| parent | ae0a846e411dc0b568e8ccda584896310ee5f369 (diff) | |
[ARM] 4108/2: Allow multiple GIC interrupt controllers in a system
The current implementation only assumes one GIC to be present in the
system. However, there are platforms with more than one cascaded interrupt
controllers (RealView/EB MPCore for example).
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Diffstat (limited to 'arch/arm/mach-realview/platsmp.c')
| -rw-r--r-- | arch/arm/mach-realview/platsmp.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/arm/mach-realview/platsmp.c b/arch/arm/mach-realview/platsmp.c index b8484e15dacb..709a9b1ac634 100644 --- a/arch/arm/mach-realview/platsmp.c +++ b/arch/arm/mach-realview/platsmp.c @@ -52,7 +52,7 @@ void __cpuinit platform_secondary_init(unsigned int cpu) * core (e.g. timer irq), then they will not have been enabled * for us: do so */ - gic_cpu_init(__io_address(REALVIEW_GIC_CPU_BASE)); + gic_cpu_init(0, __io_address(REALVIEW_GIC_CPU_BASE)); /* * let the primary processor know we're out of the |