diff options
| author | Peter Rosin <peda@axentia.se> | 2015-02-05 14:02:09 +0800 |
|---|---|---|
| committer | Nicolas Ferre <nicolas.ferre@atmel.com> | 2015-03-03 19:43:59 +0100 |
| commit | 02f513a0970d97e4fc5f262f5a6c814014af524e (patch) | |
| tree | 1608f7b1eaf9cd1e42df3f021031742bdbf68fcc /arch/arm/mach-s3c24xx/sleep-s3c2410.S | |
| parent | ad4a38d2187720a3d1442d693c99675ccd955f32 (diff) | |
pm: at91: Workaround DDRSDRC self-refresh bug with LPDDR1 memories.
The DDRSDR controller fails miserably to put LPDDR1 memories in
self-refresh. Force the controller to think it has DDR2 memories
during the self-refresh period, as the DDR2 self-refresh spec is
equivalent to LPDDR1, and is correctly implemented in the
controller.
Assume that the second controller has the same fault, but that is
untested.
Signed-off-by: Peter Rosin <peda@axentia.se>
Acked-by: Nicolas Ferre <nicolas.ferre@atmel.com>
Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
Diffstat (limited to 'arch/arm/mach-s3c24xx/sleep-s3c2410.S')
0 files changed, 0 insertions, 0 deletions