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authorSeungwhan Youn <sw.youn@samsung.com>2010-10-19 18:08:08 +0900
committerKukjin Kim <kgene.kim@samsung.com>2010-10-25 16:10:33 +0900
commit06185c07621263ee1665d4a4e27a9782a677bcf9 (patch)
tree7706d9641e742de8ef5c2a37a5b8d6fae33ee9cd /arch/arm/mach-s5p6442
parent8e0e9e295814d3d514bdfdef72ca271ebe862433 (diff)
ARM: S5P6442: Add DMA operation clock
This patch adds DMA operation clock which is disabled as default. Signed-off-by: Seungwhan Youn <sw.youn@samsung.com> Acked-by: Jassi Brar <jassi.brar@samsung.com> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
Diffstat (limited to 'arch/arm/mach-s5p6442')
-rw-r--r--arch/arm/mach-s5p6442/clock.c28
-rw-r--r--arch/arm/mach-s5p6442/include/mach/regs-clock.h1
2 files changed, 29 insertions, 0 deletions
diff --git a/arch/arm/mach-s5p6442/clock.c b/arch/arm/mach-s5p6442/clock.c
index dcd20f17212a..16d6e7e61b50 100644
--- a/arch/arm/mach-s5p6442/clock.c
+++ b/arch/arm/mach-s5p6442/clock.c
@@ -192,6 +192,11 @@ static struct clk clk_pclkd1 = {
.parent = &clk_hclkd1,
};
+int s5p6442_clk_ip0_ctrl(struct clk *clk, int enable)
+{
+ return s5p_gatectrl(S5P_CLKGATE_IP0, clk, enable);
+}
+
int s5p6442_clk_ip3_ctrl(struct clk *clk, int enable)
{
return s5p_gatectrl(S5P_CLKGATE_IP3, clk, enable);
@@ -335,6 +340,16 @@ void __init_or_cpufreq s5p6442_setup_clocks(void)
clk_pclkd1.rate = pclkd1;
}
+static struct clk init_clocks_disable[] = {
+ {
+ .name = "pdma",
+ .id = -1,
+ .parent = &clk_pclkd1,
+ .enable = s5p6442_clk_ip0_ctrl,
+ .ctrlbit = (1 << 3),
+ },
+};
+
static struct clk init_clocks[] = {
{
.name = "systimer",
@@ -393,10 +408,23 @@ static struct clk *clks[] __initdata = {
void __init s5p6442_register_clocks(void)
{
+ struct clk *clkptr;
+ int i, ret;
+
s3c24xx_register_clocks(clks, ARRAY_SIZE(clks));
s3c_register_clksrc(clksrcs, ARRAY_SIZE(clksrcs));
s3c_register_clocks(init_clocks, ARRAY_SIZE(init_clocks));
+ clkptr = init_clocks_disable;
+ for (i = 0; i < ARRAY_SIZE(init_clocks_disable); i++, clkptr++) {
+ ret = s3c24xx_register_clock(clkptr);
+ if (ret < 0) {
+ printk(KERN_ERR "Fail to register clock %s (%d)\n",
+ clkptr->name, ret);
+ } else
+ (clkptr->enable)(clkptr, 0);
+ }
+
s3c_pwmclk_init();
}
diff --git a/arch/arm/mach-s5p6442/include/mach/regs-clock.h b/arch/arm/mach-s5p6442/include/mach/regs-clock.h
index d8360b5d4ece..00828a336991 100644
--- a/arch/arm/mach-s5p6442/include/mach/regs-clock.h
+++ b/arch/arm/mach-s5p6442/include/mach/regs-clock.h
@@ -46,6 +46,7 @@
#define S5P_CLK_DIV5 S5P_CLKREG(0x314)
#define S5P_CLK_DIV6 S5P_CLKREG(0x318)
+#define S5P_CLKGATE_IP0 S5P_CLKREG(0x460)
#define S5P_CLKGATE_IP3 S5P_CLKREG(0x46C)
/* CLK_OUT */