diff options
| author | Marek Szyprowski <m.szyprowski@samsung.com> | 2010-05-20 08:59:05 +0200 |
|---|---|---|
| committer | Ben Dooks <ben-linux@fluff.org> | 2010-05-20 17:48:36 +0900 |
| commit | 999304be1177d42d16bc59c546228c6ac5a3e76a (patch) | |
| tree | ab8ba2b618484e93033bcc53fe0a4e014434d99f /arch/arm/mach-s5pc100 | |
| parent | 504d36e91ac12ccdb0e1193cee7bef9831a1c99e (diff) | |
ARM: SAMSUNG: Add platform support code for OneNAND controller
This patch adds setup code for Samsung OneNAND controller driver. The
driver needs to be aware on which SoC it is running, so the actual
device id is being changed in cpu init code. S3C64xx SoCs have 2 OneNAND
controllers while S5PC100 and S5PC110 has only one.
Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
[ben-linux@fluff.org: sort map.h entries]
Signed-off-by: Ben Dooks <ben-linux@fluff.org>
Diffstat (limited to 'arch/arm/mach-s5pc100')
| -rw-r--r-- | arch/arm/mach-s5pc100/cpu.c | 4 | ||||
| -rw-r--r-- | arch/arm/mach-s5pc100/include/mach/map.h | 8 |
2 files changed, 12 insertions, 0 deletions
diff --git a/arch/arm/mach-s5pc100/cpu.c b/arch/arm/mach-s5pc100/cpu.c index d79e7574a852..cb37ffee05b2 100644 --- a/arch/arm/mach-s5pc100/cpu.c +++ b/arch/arm/mach-s5pc100/cpu.c @@ -41,6 +41,8 @@ #include <plat/clock.h> #include <plat/sdhci.h> #include <plat/iic-core.h> +#include <plat/onenand-core.h> + #include <plat/s5pc100.h> /* Initial IO mappings */ @@ -82,6 +84,8 @@ void __init s5pc100_map_io(void) /* the i2c devices are directly compatible with s3c2440 */ s3c_i2c0_setname("s3c2440-i2c"); s3c_i2c1_setname("s3c2440-i2c"); + + s3c_onenand_setname("s5pc100-onenand"); } void __init s5pc100_init_clocks(int xtal) diff --git a/arch/arm/mach-s5pc100/include/mach/map.h b/arch/arm/mach-s5pc100/include/mach/map.h index 4681ebe8bef6..aba3bb4e3412 100644 --- a/arch/arm/mach-s5pc100/include/mach/map.h +++ b/arch/arm/mach-s5pc100/include/mach/map.h @@ -31,6 +31,9 @@ * */ +#define S5PC100_PA_ONENAND_BUF (0xB0000000) +#define S5PC100_SZ_ONENAND_BUF (SZ_256M - SZ_32M) + /* Chip ID */ #define S5PC100_PA_CHIPID (0xE0000000) #define S5PC1XX_PA_CHIPID S5PC100_PA_CHIPID @@ -60,6 +63,8 @@ #define S5PC1XX_PA_VIC(x) (S5PC100_PA_VIC + ((x) * S5PC100_PA_VIC_OFFSET)) #define S5PC1XX_VA_VIC(x) (S5PC100_VA_VIC + ((x) * S5PC100_VA_VIC_OFFSET)) +#define S5PC100_PA_ONENAND (0xE7100000) + /* DMA */ #define S5PC100_PA_MDMA (0xE8100000) #define S5PC100_PA_PDMA0 (0xE9000000) @@ -146,5 +151,8 @@ #define S3C_PA_HSMMC2 S5PC100_PA_HSMMC2 #define S3C_PA_KEYPAD S5PC100_PA_KEYPAD #define S3C_PA_TSADC S5PC100_PA_TSADC +#define S3C_PA_ONENAND S5PC100_PA_ONENAND +#define S3C_PA_ONENAND_BUF S5PC100_PA_ONENAND_BUF +#define S3C_SZ_ONENAND_BUF S5PC100_SZ_ONENAND_BUF #endif /* __ASM_ARCH_C100_MAP_H */ |