diff options
author | Ben Dooks <ben-linux@fluff.org> | 2010-05-20 20:25:59 +0900 |
---|---|---|
committer | Ben Dooks <ben-linux@fluff.org> | 2010-05-20 20:25:59 +0900 |
commit | 206a1a825dc67060ee319c99569755ba11250907 (patch) | |
tree | e4cdbd7b8b745e0ad4adfd59fa57c3bcabe3daf4 /arch/arm/mach-s5pc100 | |
parent | 6aeaad51aaecc9ebc8c1e8f132655e2ae8141f8c (diff) | |
parent | 999304be1177d42d16bc59c546228c6ac5a3e76a (diff) |
ARM: Merge for-2635-4/onenand
Merge branch 'for-2635-4/onenand' into for-2635-4/partial2
Conflicts:
arch/arm/mach-s5pc100/cpu.c
arch/arm/mach-s5pc100/include/mach/map.h
arch/arm/mach-s5pv210/Makefile
Diffstat (limited to 'arch/arm/mach-s5pc100')
-rw-r--r-- | arch/arm/mach-s5pc100/cpu.c | 4 | ||||
-rw-r--r-- | arch/arm/mach-s5pc100/include/mach/map.h | 68 |
2 files changed, 60 insertions, 12 deletions
diff --git a/arch/arm/mach-s5pc100/cpu.c b/arch/arm/mach-s5pc100/cpu.c index d424a9fda034..816c4d4afef0 100644 --- a/arch/arm/mach-s5pc100/cpu.c +++ b/arch/arm/mach-s5pc100/cpu.c @@ -40,6 +40,8 @@ #include <plat/clock.h> #include <plat/iic-core.h> #include <plat/sdhci.h> +#include <plat/onenand-core.h> + #include <plat/s5pc100.h> /* Initial IO mappings */ @@ -88,6 +90,8 @@ void __init s5pc100_map_io(void) /* the i2c devices are directly compatible with s3c2440 */ s3c_i2c0_setname("s3c2440-i2c"); s3c_i2c1_setname("s3c2440-i2c"); + + s3c_onenand_setname("s5pc100-onenand"); } void __init s5pc100_init_clocks(int xtal) diff --git a/arch/arm/mach-s5pc100/include/mach/map.h b/arch/arm/mach-s5pc100/include/mach/map.h index 88009549ab28..a0b2fee332a1 100644 --- a/arch/arm/mach-s5pc100/include/mach/map.h +++ b/arch/arm/mach-s5pc100/include/mach/map.h @@ -16,6 +16,25 @@ #include <plat/map-base.h> #include <plat/map-s5p.h> +/* + * map-base.h has already defined virtual memory address + * S3C_VA_IRQ S3C_ADDR(0x00000000) irq controller(s) + * S3C_VA_SYS S3C_ADDR(0x00100000) system control + * S3C_VA_MEM S3C_ADDR(0x00200000) system control (not used) + * S3C_VA_TIMER S3C_ADDR(0x00300000) timer block + * S3C_VA_WATCHDOG S3C_ADDR(0x00400000) watchdog + * S3C_VA_UART S3C_ADDR(0x01000000) UART + * + * S5PC100 specific virtual memory address can be defined here + * S5PC1XX_VA_GPIO S3C_ADDR(0x00500000) GPIO + * + */ + +#define S5PC100_PA_ONENAND_BUF (0xB0000000) +#define S5PC100_SZ_ONENAND_BUF (SZ_256M - SZ_32M) + +/* Chip ID */ + #define S5PC100_PA_CHIPID (0xE0000000) #define S5P_PA_CHIPID S5PC100_PA_CHIPID @@ -26,17 +45,26 @@ #define S5PC100_VA_OTHERS (S3C_VA_SYS + 0x10000) #define S5PC100_PA_GPIO (0xE0300000) -#define S5P_PA_GPIO S5PC100_PA_GPIO -#define S5PC100_PA_VIC0 (0xE4000000) -#define S5P_PA_VIC0 S5PC100_PA_VIC0 +#define S5PC1XX_PA_GPIO S5PC100_PA_GPIO +#define S5PC1XX_VA_GPIO S3C_ADDR(0x00500000) + +/* Interrupt */ +#define S5PC100_PA_VIC (0xE4000000) +#define S5PC100_VA_VIC S3C_VA_IRQ +#define S5PC100_PA_VIC_OFFSET 0x100000 +#define S5PC100_VA_VIC_OFFSET 0x10000 +#define S5PC1XX_PA_VIC(x) (S5PC100_PA_VIC + ((x) * S5PC100_PA_VIC_OFFSET)) +#define S5PC1XX_VA_VIC(x) (S5PC100_VA_VIC + ((x) * S5PC100_VA_VIC_OFFSET)) -#define S5PC100_PA_VIC1 (0xE4100000) -#define S5P_PA_VIC1 S5PC100_PA_VIC1 +#define S5PC100_PA_ONENAND (0xE7100000) -#define S5PC100_PA_VIC2 (0xE4200000) -#define S5P_PA_VIC2 S5PC100_PA_VIC2 +/* DMA */ +#define S5PC100_PA_MDMA (0xE8100000) +#define S5PC100_PA_PDMA0 (0xE9000000) +#define S5PC100_PA_PDMA1 (0xE9200000) +/* Timer */ #define S5PC100_PA_TIMER (0xEA000000) #define S5P_PA_TIMER S5PC100_PA_TIMER @@ -83,8 +111,24 @@ #define S3C_PA_IIC S5PC100_PA_IIC0 #define S3C_PA_IIC1 S5PC100_PA_IIC1 #define S3C_PA_FB S5PC100_PA_FB -#define S3C_PA_HSMMC0 S5PC100_PA_HSMMC(0) -#define S3C_PA_HSMMC1 S5PC100_PA_HSMMC(1) -#define S3C_PA_HSMMC2 S5PC100_PA_HSMMC(2) - -#endif /* __ASM_ARCH_MAP_H */ +#define S3C_PA_G2D S5PC100_PA_G2D +#define S3C_PA_G3D S5PC100_PA_G3D +#define S3C_PA_JPEG S5PC100_PA_JPEG +#define S3C_PA_ROTATOR S5PC100_PA_ROTATOR +#define S3C_VA_VIC0 (S3C_VA_IRQ + 0x0) +#define S3C_VA_VIC1 (S3C_VA_IRQ + 0x10000) +#define S3C_VA_VIC2 (S3C_VA_IRQ + 0x20000) +#define S3C_PA_IIC S5PC100_PA_I2C +#define S3C_PA_IIC1 S5PC100_PA_I2C1 +#define S3C_PA_USB_HSOTG S5PC100_PA_USB_HSOTG +#define S3C_PA_USB_HSPHY S5PC100_PA_USB_HSPHY +#define S3C_PA_HSMMC0 S5PC100_PA_HSMMC0 +#define S3C_PA_HSMMC1 S5PC100_PA_HSMMC1 +#define S3C_PA_HSMMC2 S5PC100_PA_HSMMC2 +#define S3C_PA_KEYPAD S5PC100_PA_KEYPAD +#define S3C_PA_TSADC S5PC100_PA_TSADC +#define S3C_PA_ONENAND S5PC100_PA_ONENAND +#define S3C_PA_ONENAND_BUF S5PC100_PA_ONENAND_BUF +#define S3C_SZ_ONENAND_BUF S5PC100_SZ_ONENAND_BUF + +#endif /* __ASM_ARCH_C100_MAP_H */ |