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authorLinus Torvalds <torvalds@linux-foundation.org>2014-12-09 14:38:28 -0800
committerLinus Torvalds <torvalds@linux-foundation.org>2014-12-09 14:38:28 -0800
commit6cd94d5e57ab97ddd672b707ab4bb639672c1727 (patch)
treeb1b301b16433d4deab6bd52e81d04a7b58c239d3 /arch/arm/mach-shmobile
parent6c9e92476bc924ede6d6d2f0bfed2c06ae148d29 (diff)
parent842f7d2c4d392c0571cf72e3eaca26742bebbd1e (diff)
Merge tag 'soc-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc
Pull ARM SoC platform changes from Arnd Bergmann: "New and updated SoC support, notable changes include: - bcm: brcmstb SMP support initial iproc/cygnus support - exynos: Exynos4415 SoC support PMU and suspend support for Exynos5420 PMU support for Exynos3250 pm related maintenance - imx: new LS1021A SoC support vybrid 610 global timer support - integrator: convert to using multiplatform configuration - mediatek: earlyprintk support for mt8127/mt8135 - meson: meson8 soc and l2 cache controller support - mvebu: Armada 38x CPU hotplug support drop support for prerelease Armada 375 Z1 stepping extended suspend support, now works on Armada 370/XP - omap: hwmod related maintenance prcm cleanup - pxa: initial pxa27x DT handling - rockchip: SMP support for rk3288 add cpu frequency scaling support - shmobile: r8a7740 power domain support various small restart, timer, pci apmu changes - sunxi: Allwinner A80 (sun9i) earlyprintk support - ux500: power domain support Overall, a significant chunk of changes, coming mostly from the usual suspects: omap, shmobile, samsung and mvebu, all of which already contain a lot of platform specific code in arch/arm" * tag 'soc-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (187 commits) ARM: mvebu: use the cpufreq-dt platform_data for independent clocks soc: integrator: Add terminating entry for integrator_cm_match ARM: mvebu: add SDRAM controller description for Armada XP ARM: mvebu: adjust mbus controller description on Armada 370/XP ARM: mvebu: add suspend/resume DT information for Armada XP GP ARM: mvebu: synchronize secondary CPU clocks on resume ARM: mvebu: make sure MMU is disabled in armada_370_xp_cpu_resume ARM: mvebu: Armada XP GP specific suspend/resume code ARM: mvebu: reserve the first 10 KB of each memory bank for suspend/resume ARM: mvebu: implement suspend/resume support for Armada XP clk: mvebu: add suspend/resume for gatable clocks bus: mvebu-mbus: provide a mechanism to save SDRAM window configuration bus: mvebu-mbus: suspend/resume support clocksource: time-armada-370-xp: add suspend/resume support irqchip: armada-370-xp: Add suspend/resume support ARM: add lolevel debug support for asm9260 ARM: add mach-asm9260 ARM: EXYNOS: use u8 for val[] in struct exynos_pmu_conf power: reset: imx-snvs-poweroff: add power off driver for i.mx6 ARM: imx: temporarily remove CONFIG_SOC_FSL from LS1021A ...
Diffstat (limited to 'arch/arm/mach-shmobile')
-rw-r--r--arch/arm/mach-shmobile/Kconfig2
-rw-r--r--arch/arm/mach-shmobile/Makefile1
-rw-r--r--arch/arm/mach-shmobile/board-armadillo800eva.c12
-rw-r--r--arch/arm/mach-shmobile/board-kzm9g-reference.c8
-rw-r--r--arch/arm/mach-shmobile/common.h5
-rw-r--r--arch/arm/mach-shmobile/platsmp-apmu.c27
-rw-r--r--arch/arm/mach-shmobile/platsmp-apmu.h32
-rw-r--r--arch/arm/mach-shmobile/pm-r8a7740.c44
-rw-r--r--arch/arm/mach-shmobile/setup-r8a7740.c12
-rw-r--r--arch/arm/mach-shmobile/setup-r8a7779.c1
-rw-r--r--arch/arm/mach-shmobile/setup-rcar-gen2.c72
-rw-r--r--arch/arm/mach-shmobile/setup-sh7372.c2
-rw-r--r--arch/arm/mach-shmobile/setup-sh73a0.c9
-rw-r--r--arch/arm/mach-shmobile/smp-r8a7790.c16
-rw-r--r--arch/arm/mach-shmobile/smp-r8a7791.c12
-rw-r--r--arch/arm/mach-shmobile/timer.c23
16 files changed, 217 insertions, 61 deletions
diff --git a/arch/arm/mach-shmobile/Kconfig b/arch/arm/mach-shmobile/Kconfig
index 0f2539550f1b..1b4fafe524ff 100644
--- a/arch/arm/mach-shmobile/Kconfig
+++ b/arch/arm/mach-shmobile/Kconfig
@@ -1,5 +1,6 @@
config ARCH_SHMOBILE
bool
+ select ZONE_DMA if ARM_LPAE
config PM_RCAR
bool
@@ -18,6 +19,7 @@ config ARCH_RCAR_GEN2
select PM_RCAR if PM || SMP
select RENESAS_IRQC
select SYS_SUPPORTS_SH_CMT
+ select PCI_DOMAINS if PCI
config ARCH_RMOBILE
bool
diff --git a/arch/arm/mach-shmobile/Makefile b/arch/arm/mach-shmobile/Makefile
index 7d68eba53be3..b55cac0e5b2b 100644
--- a/arch/arm/mach-shmobile/Makefile
+++ b/arch/arm/mach-shmobile/Makefile
@@ -35,6 +35,7 @@ cpu-y := platsmp.o headsmp.o
# Shared SoC family objects
obj-$(CONFIG_ARCH_RCAR_GEN2) += setup-rcar-gen2.o platsmp-apmu.o $(cpu-y)
+CFLAGS_setup-rcar-gen2.o += -march=armv7-a
# SMP objects
smp-y := $(cpu-y)
diff --git a/arch/arm/mach-shmobile/board-armadillo800eva.c b/arch/arm/mach-shmobile/board-armadillo800eva.c
index de95181c7de4..6d949f1c850b 100644
--- a/arch/arm/mach-shmobile/board-armadillo800eva.c
+++ b/arch/arm/mach-shmobile/board-armadillo800eva.c
@@ -1229,8 +1229,15 @@ static void __init eva_init(void)
static struct pm_domain_device domain_devices[] __initdata = {
{ "A4LC", &lcdc0_device },
{ "A4LC", &hdmi_lcdc_device },
+ { "A4MP", &hdmi_device },
+ { "A4MP", &fsi_device },
+ { "A4R", &ceu0_device },
+ { "A4S", &sh_eth_device },
+ { "A3SP", &pwm_device },
+ { "A3SP", &sdhi0_device },
+ { "A3SP", &sh_mmcif_device },
};
- struct platform_device *usb = NULL;
+ struct platform_device *usb = NULL, *sdhi1 = NULL;
regulator_register_always_on(0, "fixed-3.3V", fixed3v3_power_consumers,
ARRAY_SIZE(fixed3v3_power_consumers), 3300000);
@@ -1299,6 +1306,7 @@ static void __init eva_init(void)
platform_device_register(&vcc_sdhi1);
platform_device_register(&sdhi1_device);
+ sdhi1 = &sdhi1_device;
}
@@ -1319,6 +1327,8 @@ static void __init eva_init(void)
ARRAY_SIZE(domain_devices));
if (usb)
rmobile_add_device_to_domain("A3SP", usb);
+ if (sdhi1)
+ rmobile_add_device_to_domain("A3SP", sdhi1);
r8a7740_pm_init();
}
diff --git a/arch/arm/mach-shmobile/board-kzm9g-reference.c b/arch/arm/mach-shmobile/board-kzm9g-reference.c
index f2ef759b6e96..2e82e44ab852 100644
--- a/arch/arm/mach-shmobile/board-kzm9g-reference.c
+++ b/arch/arm/mach-shmobile/board-kzm9g-reference.c
@@ -39,6 +39,13 @@ static void __init kzm_init(void)
#endif
}
+#define RESCNT2 IOMEM(0xe6188020)
+static void kzm9g_restart(enum reboot_mode mode, const char *cmd)
+{
+ /* Do soft power on reset */
+ writel((1 << 31), RESCNT2);
+}
+
static const char *kzm9g_boards_compat_dt[] __initdata = {
"renesas,kzm9g-reference",
NULL,
@@ -50,5 +57,6 @@ DT_MACHINE_START(KZM9G_DT, "kzm9g-reference")
.init_early = shmobile_init_delay,
.init_machine = kzm_init,
.init_late = shmobile_init_late,
+ .restart = kzm9g_restart,
.dt_compat = kzm9g_boards_compat_dt,
MACHINE_END
diff --git a/arch/arm/mach-shmobile/common.h b/arch/arm/mach-shmobile/common.h
index 72087c79ad7b..309025efd4cf 100644
--- a/arch/arm/mach-shmobile/common.h
+++ b/arch/arm/mach-shmobile/common.h
@@ -19,11 +19,6 @@ extern void shmobile_boot_scu(void);
extern void shmobile_smp_scu_prepare_cpus(unsigned int max_cpus);
extern void shmobile_smp_scu_cpu_die(unsigned int cpu);
extern int shmobile_smp_scu_cpu_kill(unsigned int cpu);
-extern void shmobile_smp_apmu_prepare_cpus(unsigned int max_cpus);
-extern int shmobile_smp_apmu_boot_secondary(unsigned int cpu,
- struct task_struct *idle);
-extern void shmobile_smp_apmu_cpu_die(unsigned int cpu);
-extern int shmobile_smp_apmu_cpu_kill(unsigned int cpu);
struct clk;
extern int shmobile_clk_init(void);
extern void shmobile_handle_irq_intc(struct pt_regs *);
diff --git a/arch/arm/mach-shmobile/platsmp-apmu.c b/arch/arm/mach-shmobile/platsmp-apmu.c
index 2c06810d3a70..f483b560b066 100644
--- a/arch/arm/mach-shmobile/platsmp-apmu.c
+++ b/arch/arm/mach-shmobile/platsmp-apmu.c
@@ -1,6 +1,7 @@
/*
* SMP support for SoCs with APMU
*
+ * Copyright (C) 2014 Renesas Electronics Corporation
* Copyright (C) 2013 Magnus Damm
*
* This program is free software; you can redistribute it and/or modify
@@ -22,6 +23,7 @@
#include <asm/smp_plat.h>
#include <asm/suspend.h>
#include "common.h"
+#include "platsmp-apmu.h"
static struct {
void __iomem *iomem;
@@ -83,28 +85,15 @@ static void apmu_init_cpu(struct resource *res, int cpu, int bit)
pr_debug("apmu ioremap %d %d %pr\n", cpu, bit, res);
}
-static struct {
- struct resource iomem;
- int cpus[4];
-} apmu_config[] = {
- {
- .iomem = DEFINE_RES_MEM(0xe6152000, 0x88),
- .cpus = { 0, 1, 2, 3 },
- },
- {
- .iomem = DEFINE_RES_MEM(0xe6151000, 0x88),
- .cpus = { 0x100, 0x101, 0x102, 0x103 },
- }
-};
-
-static void apmu_parse_cfg(void (*fn)(struct resource *res, int cpu, int bit))
+static void apmu_parse_cfg(void (*fn)(struct resource *res, int cpu, int bit),
+ struct rcar_apmu_config *apmu_config, int num)
{
u32 id;
int k;
int bit, index;
bool is_allowed;
- for (k = 0; k < ARRAY_SIZE(apmu_config); k++) {
+ for (k = 0; k < num; k++) {
/* only enable the cluster that includes the boot CPU */
is_allowed = false;
for (bit = 0; bit < ARRAY_SIZE(apmu_config[k].cpus); bit++) {
@@ -128,14 +117,16 @@ static void apmu_parse_cfg(void (*fn)(struct resource *res, int cpu, int bit))
}
}
-void __init shmobile_smp_apmu_prepare_cpus(unsigned int max_cpus)
+void __init shmobile_smp_apmu_prepare_cpus(unsigned int max_cpus,
+ struct rcar_apmu_config *apmu_config,
+ int num)
{
/* install boot code shared by all CPUs */
shmobile_boot_fn = virt_to_phys(shmobile_smp_boot);
shmobile_boot_arg = MPIDR_HWID_BITMASK;
/* perform per-cpu setup */
- apmu_parse_cfg(apmu_init_cpu);
+ apmu_parse_cfg(apmu_init_cpu, apmu_config, num);
}
#ifdef CONFIG_SMP
diff --git a/arch/arm/mach-shmobile/platsmp-apmu.h b/arch/arm/mach-shmobile/platsmp-apmu.h
new file mode 100644
index 000000000000..76512c9a2545
--- /dev/null
+++ b/arch/arm/mach-shmobile/platsmp-apmu.h
@@ -0,0 +1,32 @@
+/*
+ * rmobile apmu definition
+ *
+ * Copyright (C) 2014 Renesas Electronics Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef PLATSMP_APMU_H
+#define PLATSMP_APMU_H
+
+struct rcar_apmu_config {
+ struct resource iomem;
+ int cpus[4];
+};
+
+extern void shmobile_smp_apmu_prepare_cpus(unsigned int max_cpus,
+ struct rcar_apmu_config *apmu_config,
+ int num);
+extern int shmobile_smp_apmu_boot_secondary(unsigned int cpu,
+ struct task_struct *idle);
+extern void shmobile_smp_apmu_cpu_die(unsigned int cpu);
+extern int shmobile_smp_apmu_cpu_kill(unsigned int cpu);
+
+#endif /* PLATSMP_APMU_H */
diff --git a/arch/arm/mach-shmobile/pm-r8a7740.c b/arch/arm/mach-shmobile/pm-r8a7740.c
index e3f146448237..ac2eecd6f5ea 100644
--- a/arch/arm/mach-shmobile/pm-r8a7740.c
+++ b/arch/arm/mach-shmobile/pm-r8a7740.c
@@ -14,10 +14,10 @@
#include "pm-rmobile.h"
#if defined(CONFIG_PM) && !defined(CONFIG_ARCH_MULTIPLATFORM)
-static int r8a7740_pd_a4s_suspend(void)
+static int r8a7740_pd_a3sm_suspend(void)
{
/*
- * The A4S domain contains the CPU core and therefore it should
+ * The A3SM domain contains the CPU core and therefore it should
* only be turned off if the CPU is not in use.
*/
return -EBUSY;
@@ -32,29 +32,65 @@ static int r8a7740_pd_a3sp_suspend(void)
return console_suspend_enabled ? 0 : -EBUSY;
}
+static int r8a7740_pd_d4_suspend(void)
+{
+ /*
+ * The D4 domain contains the Coresight-ETM hardware block and
+ * therefore it should only be turned off if the debug module is
+ * not in use.
+ */
+ return -EBUSY;
+}
+
static struct rmobile_pm_domain r8a7740_pm_domains[] = {
{
.genpd.name = "A4LC",
.bit_shift = 1,
}, {
+ .genpd.name = "A4MP",
+ .bit_shift = 2,
+ }, {
+ .genpd.name = "D4",
+ .bit_shift = 3,
+ .gov = &pm_domain_always_on_gov,
+ .suspend = r8a7740_pd_d4_suspend,
+ }, {
+ .genpd.name = "A4R",
+ .bit_shift = 5,
+ }, {
+ .genpd.name = "A3RV",
+ .bit_shift = 6,
+ }, {
.genpd.name = "A4S",
.bit_shift = 10,
- .gov = &pm_domain_always_on_gov,
.no_debug = true,
- .suspend = r8a7740_pd_a4s_suspend,
}, {
.genpd.name = "A3SP",
.bit_shift = 11,
.gov = &pm_domain_always_on_gov,
.no_debug = true,
.suspend = r8a7740_pd_a3sp_suspend,
+ }, {
+ .genpd.name = "A3SM",
+ .bit_shift = 12,
+ .gov = &pm_domain_always_on_gov,
+ .suspend = r8a7740_pd_a3sm_suspend,
+ }, {
+ .genpd.name = "A3SG",
+ .bit_shift = 13,
+ }, {
+ .genpd.name = "A4SU",
+ .bit_shift = 20,
},
};
void __init r8a7740_init_pm_domains(void)
{
rmobile_init_domains(r8a7740_pm_domains, ARRAY_SIZE(r8a7740_pm_domains));
+ pm_genpd_add_subdomain_names("A4R", "A3RV");
pm_genpd_add_subdomain_names("A4S", "A3SP");
+ pm_genpd_add_subdomain_names("A4S", "A3SM");
+ pm_genpd_add_subdomain_names("A4S", "A3SG");
}
#endif /* CONFIG_PM && !CONFIG_ARCH_MULTIPLATFORM */
diff --git a/arch/arm/mach-shmobile/setup-r8a7740.c b/arch/arm/mach-shmobile/setup-r8a7740.c
index fe15dd26d15d..79ad93dfdae4 100644
--- a/arch/arm/mach-shmobile/setup-r8a7740.c
+++ b/arch/arm/mach-shmobile/setup-r8a7740.c
@@ -67,6 +67,7 @@ static struct map_desc r8a7740_io_desc[] __initdata = {
void __init r8a7740_map_io(void)
{
+ debug_ll_io_init();
iotable_init(r8a7740_io_desc, ARRAY_SIZE(r8a7740_io_desc));
}
@@ -742,6 +743,12 @@ static void r8a7740_i2c_workaround(struct platform_device *pdev)
void __init r8a7740_add_standard_devices(void)
{
static struct pm_domain_device domain_devices[] __initdata = {
+ { "A4R", &tmu0_device },
+ { "A4R", &i2c0_device },
+ { "A4S", &irqpin0_device },
+ { "A4S", &irqpin1_device },
+ { "A4S", &irqpin2_device },
+ { "A4S", &irqpin3_device },
{ "A3SP", &scif0_device },
{ "A3SP", &scif1_device },
{ "A3SP", &scif2_device },
@@ -752,6 +759,11 @@ void __init r8a7740_add_standard_devices(void)
{ "A3SP", &scif7_device },
{ "A3SP", &scif8_device },
{ "A3SP", &i2c1_device },
+ { "A3SP", &ipmmu_device },
+ { "A3SP", &dma0_device },
+ { "A3SP", &dma1_device },
+ { "A3SP", &dma2_device },
+ { "A3SP", &usb_dma_device },
};
/* I2C work-around */
diff --git a/arch/arm/mach-shmobile/setup-r8a7779.c b/arch/arm/mach-shmobile/setup-r8a7779.c
index 645d7cca6238..6156d172cf31 100644
--- a/arch/arm/mach-shmobile/setup-r8a7779.c
+++ b/arch/arm/mach-shmobile/setup-r8a7779.c
@@ -66,6 +66,7 @@ static struct map_desc r8a7779_io_desc[] __initdata = {
void __init r8a7779_map_io(void)
{
+ debug_ll_io_init();
iotable_init(r8a7779_io_desc, ARRAY_SIZE(r8a7779_io_desc));
}
diff --git a/arch/arm/mach-shmobile/setup-rcar-gen2.c b/arch/arm/mach-shmobile/setup-rcar-gen2.c
index a669377aea57..3dd6edd9bd1d 100644
--- a/arch/arm/mach-shmobile/setup-rcar-gen2.c
+++ b/arch/arm/mach-shmobile/setup-rcar-gen2.c
@@ -3,6 +3,7 @@
*
* Copyright (C) 2013 Renesas Solutions Corp.
* Copyright (C) 2013 Magnus Damm
+ * Copyright (C) 2014 Ulrich Hecht
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
@@ -20,6 +21,7 @@
#include <linux/dma-contiguous.h>
#include <linux/io.h>
#include <linux/kernel.h>
+#include <linux/of.h>
#include <linux/of_fdt.h>
#include <asm/mach/arch.h>
#include "common.h"
@@ -50,37 +52,61 @@ void __init rcar_gen2_timer_init(void)
{
#if defined(CONFIG_ARM_ARCH_TIMER) || defined(CONFIG_COMMON_CLK)
u32 mode = rcar_gen2_read_mode_pins();
+ bool is_e2 = (bool)of_find_compatible_node(NULL, NULL,
+ "renesas,r8a7794");
#endif
#ifdef CONFIG_ARM_ARCH_TIMER
void __iomem *base;
int extal_mhz = 0;
u32 freq;
- /* At Linux boot time the r8a7790 arch timer comes up
- * with the counter disabled. Moreover, it may also report
- * a potentially incorrect fixed 13 MHz frequency. To be
- * correct these registers need to be updated to use the
- * frequency EXTAL / 2 which can be determined by the MD pins.
- */
-
- switch (mode & (MD(14) | MD(13))) {
- case 0:
- extal_mhz = 15;
- break;
- case MD(13):
- extal_mhz = 20;
- break;
- case MD(14):
- extal_mhz = 26;
- break;
- case MD(13) | MD(14):
- extal_mhz = 30;
- break;
+ if (is_e2) {
+ freq = 260000000 / 8; /* ZS / 8 */
+ /* CNTVOFF has to be initialized either from non-secure
+ * Hypervisor mode or secure Monitor mode with SCR.NS==1.
+ * If TrustZone is enabled then it should be handled by the
+ * secure code.
+ */
+ asm volatile(
+ " cps 0x16\n"
+ " mrc p15, 0, r1, c1, c1, 0\n"
+ " orr r0, r1, #1\n"
+ " mcr p15, 0, r0, c1, c1, 0\n"
+ " isb\n"
+ " mov r0, #0\n"
+ " mcrr p15, 4, r0, r0, c14\n"
+ " isb\n"
+ " mcr p15, 0, r1, c1, c1, 0\n"
+ " isb\n"
+ " cps 0x13\n"
+ : : : "r0", "r1");
+ } else {
+ /* At Linux boot time the r8a7790 arch timer comes up
+ * with the counter disabled. Moreover, it may also report
+ * a potentially incorrect fixed 13 MHz frequency. To be
+ * correct these registers need to be updated to use the
+ * frequency EXTAL / 2 which can be determined by the MD pins.
+ */
+
+ switch (mode & (MD(14) | MD(13))) {
+ case 0:
+ extal_mhz = 15;
+ break;
+ case MD(13):
+ extal_mhz = 20;
+ break;
+ case MD(14):
+ extal_mhz = 26;
+ break;
+ case MD(13) | MD(14):
+ extal_mhz = 30;
+ break;
+ }
+
+ /* The arch timer frequency equals EXTAL / 2 */
+ freq = extal_mhz * (1000000 / 2);
}
- /* The arch timer frequency equals EXTAL / 2 */
- freq = extal_mhz * (1000000 / 2);
-
/* Remap "armgcnt address map" space */
base = ioremap(0xe6080000, PAGE_SIZE);
diff --git a/arch/arm/mach-shmobile/setup-sh7372.c b/arch/arm/mach-shmobile/setup-sh7372.c
index ca2b80b9bc90..458a2cfad417 100644
--- a/arch/arm/mach-shmobile/setup-sh7372.c
+++ b/arch/arm/mach-shmobile/setup-sh7372.c
@@ -56,6 +56,7 @@ static struct map_desc sh7372_io_desc[] __initdata = {
void __init sh7372_map_io(void)
{
+ debug_ll_io_init();
iotable_init(sh7372_io_desc, ARRAY_SIZE(sh7372_io_desc));
}
@@ -1008,6 +1009,7 @@ DT_MACHINE_START(SH7372_DT, "Generic SH7372 (Flattened Device Tree)")
.init_irq = sh7372_init_irq,
.handle_irq = shmobile_handle_irq_intc,
.init_machine = sh7372_add_standard_devices_dt,
+ .init_late = shmobile_init_late,
.dt_compat = sh7372_boards_compat_dt,
MACHINE_END
diff --git a/arch/arm/mach-shmobile/setup-sh73a0.c b/arch/arm/mach-shmobile/setup-sh73a0.c
index 1ff4bd65e647..93ebe3430bfe 100644
--- a/arch/arm/mach-shmobile/setup-sh73a0.c
+++ b/arch/arm/mach-shmobile/setup-sh73a0.c
@@ -55,6 +55,7 @@ static struct map_desc sh73a0_io_desc[] __initdata = {
void __init sh73a0_map_io(void)
{
+ debug_ll_io_init();
iotable_init(sh73a0_io_desc, ARRAY_SIZE(sh73a0_io_desc));
}
@@ -786,6 +787,13 @@ void __init sh73a0_add_standard_devices_dt(void)
of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
}
+#define RESCNT2 IOMEM(0xe6188020)
+static void sh73a0_restart(enum reboot_mode mode, const char *cmd)
+{
+ /* Do soft power on reset */
+ writel((1 << 31), RESCNT2);
+}
+
static const char *sh73a0_boards_compat_dt[] __initdata = {
"renesas,sh73a0",
NULL,
@@ -797,6 +805,7 @@ DT_MACHINE_START(SH73A0_DT, "Generic SH73A0 (Flattened Device Tree)")
.init_early = shmobile_init_delay,
.init_machine = sh73a0_add_standard_devices_dt,
.init_late = shmobile_init_late,
+ .restart = sh73a0_restart,
.dt_compat = sh73a0_boards_compat_dt,
MACHINE_END
#endif /* CONFIG_USE_OF */
diff --git a/arch/arm/mach-shmobile/smp-r8a7790.c b/arch/arm/mach-shmobile/smp-r8a7790.c
index 2311694636e1..9c3da1345b8b 100644
--- a/arch/arm/mach-shmobile/smp-r8a7790.c
+++ b/arch/arm/mach-shmobile/smp-r8a7790.c
@@ -21,6 +21,7 @@
#include <asm/smp_plat.h>
#include "common.h"
+#include "platsmp-apmu.h"
#include "pm-rcar.h"
#include "r8a7790.h"
@@ -34,10 +35,23 @@ static struct rcar_sysc_ch r8a7790_ca7_scu = {
.isr_bit = 21, /* CA7-SCU */
};
+static struct rcar_apmu_config r8a7790_apmu_config[] = {
+ {
+ .iomem = DEFINE_RES_MEM(0xe6152000, 0x88),
+ .cpus = { 0, 1, 2, 3 },
+ },
+ {
+ .iomem = DEFINE_RES_MEM(0xe6151000, 0x88),
+ .cpus = { 0x100, 0x0101, 0x102, 0x103 },
+ }
+};
+
static void __init r8a7790_smp_prepare_cpus(unsigned int max_cpus)
{
/* let APMU code install data related to shmobile_boot_vector */
- shmobile_smp_apmu_prepare_cpus(max_cpus);
+ shmobile_smp_apmu_prepare_cpus(max_cpus,
+ r8a7790_apmu_config,
+ ARRAY_SIZE(r8a7790_apmu_config));
/* turn on power to SCU */
r8a7790_pm_init();
diff --git a/arch/arm/mach-shmobile/smp-r8a7791.c b/arch/arm/mach-shmobile/smp-r8a7791.c
index f743386166fb..7e49e0a52e32 100644
--- a/arch/arm/mach-shmobile/smp-r8a7791.c
+++ b/arch/arm/mach-shmobile/smp-r8a7791.c
@@ -21,13 +21,23 @@
#include <asm/smp_plat.h>
#include "common.h"
+#include "platsmp-apmu.h"
#include "r8a7791.h"
#include "rcar-gen2.h"
+static struct rcar_apmu_config r8a7791_apmu_config[] = {
+ {
+ .iomem = DEFINE_RES_MEM(0xe6152000, 0x88),
+ .cpus = { 0, 1 },
+ }
+};
+
static void __init r8a7791_smp_prepare_cpus(unsigned int max_cpus)
{
/* let APMU code install data related to shmobile_boot_vector */
- shmobile_smp_apmu_prepare_cpus(max_cpus);
+ shmobile_smp_apmu_prepare_cpus(max_cpus,
+ r8a7791_apmu_config,
+ ARRAY_SIZE(r8a7791_apmu_config));
r8a7791_pm_init();
}
diff --git a/arch/arm/mach-shmobile/timer.c b/arch/arm/mach-shmobile/timer.c
index 1081b763e0f3..f1d027aa7a81 100644
--- a/arch/arm/mach-shmobile/timer.c
+++ b/arch/arm/mach-shmobile/timer.c
@@ -40,6 +40,7 @@ void __init shmobile_init_delay(void)
struct device_node *np, *cpus;
bool is_a7_a8_a9 = false;
bool is_a15 = false;
+ bool has_arch_timer = false;
u32 max_freq = 0;
cpus = of_find_node_by_path("/cpus");
@@ -52,12 +53,16 @@ void __init shmobile_init_delay(void)
if (!of_property_read_u32(np, "clock-frequency", &freq))
max_freq = max(max_freq, freq);
- if (of_device_is_compatible(np, "arm,cortex-a7") ||
- of_device_is_compatible(np, "arm,cortex-a8") ||
- of_device_is_compatible(np, "arm,cortex-a9"))
+ if (of_device_is_compatible(np, "arm,cortex-a8") ||
+ of_device_is_compatible(np, "arm,cortex-a9")) {
is_a7_a8_a9 = true;
- else if (of_device_is_compatible(np, "arm,cortex-a15"))
+ } else if (of_device_is_compatible(np, "arm,cortex-a7")) {
+ is_a7_a8_a9 = true;
+ has_arch_timer = true;
+ } else if (of_device_is_compatible(np, "arm,cortex-a15")) {
is_a15 = true;
+ has_arch_timer = true;
+ }
}
of_node_put(cpus);
@@ -65,10 +70,12 @@ void __init shmobile_init_delay(void)
if (!max_freq)
return;
- if (is_a7_a8_a9)
- shmobile_setup_delay_hz(max_freq, 1, 3);
- else if (is_a15 && !IS_ENABLED(CONFIG_ARM_ARCH_TIMER))
- shmobile_setup_delay_hz(max_freq, 2, 4);
+ if (!has_arch_timer || !IS_ENABLED(CONFIG_ARM_ARCH_TIMER)) {
+ if (is_a7_a8_a9)
+ shmobile_setup_delay_hz(max_freq, 1, 3);
+ else if (is_a15)
+ shmobile_setup_delay_hz(max_freq, 2, 4);
+ }
}
static void __init shmobile_late_time_init(void)