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| author | Kerwin Wan <kerwinw@nvidia.com> | 2013-03-20 14:32:21 +0800 |
|---|---|---|
| committer | Dan Willemsen <dwillemsen@nvidia.com> | 2013-09-14 13:07:48 -0700 |
| commit | cf667e497194bb7e1202c9417ac89ec98136b939 (patch) | |
| tree | 56cc560f7de8fd2bfec8f3e2024f8e9fafea321c /arch/arm/mach-tegra/Makefile | |
| parent | 97451472566700e4d8c24b4298817904574e2c36 (diff) | |
arm: tegra: macallan: set vdd_rtc to 950mV during lp0
This commit combines f983c88bf407f and 599cee8c196fa
On macallan, vdd_rtc can not be set to 900mV during lp0.
Because when vdd_rtc is set to 900mV, cpu will meet hard hang after
wake up from lp0. Hardware team should do WAT to get the proper margin
for vdd_rtc. Set vdd_rtc to 950mV to avoid this issue now.
Bug 1262674
Change-Id: Ic3ddfeb586a78e6731178bb6bd672dda0ae49566
Signed-off-by: Kerwin Wan <kerwinw@nvidia.com>
Reviewed-on: http://git-master/r/217259
Reviewed-by: Riham Haidar <rhaidar@nvidia.com>
Tested-by: Riham Haidar <rhaidar@nvidia.com>
Diffstat (limited to 'arch/arm/mach-tegra/Makefile')
0 files changed, 0 insertions, 0 deletions