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authorVladislav Sahnovich <vsahnovich@nvidia.com>2013-12-15 18:47:31 -0800
committerMitch Luban <mluban@nvidia.com>2013-12-26 16:30:35 -0800
commit8eb077c571c27fe2eb6b2a0ec4ba4e5100676188 (patch)
treeb428165cc0787424b2da587aed23c8616938ee14 /arch/arm/mach-tegra/board-ardbeg-memory.c
parentd6046dc16069525c02b0c20b85e6406bb47ded4b (diff)
arm: tegra: update dvfs table to 5.0.12 (E1780) 2G
Change-Id: I710e6f04758a4dcd8c62dbb9c2dd79bf73e8e63a Signed-off-by: Vladislav Sahnovich <vsahnovich@nvidia.com> Reviewed-on: http://git-master/r/345638 Reviewed-by: Mitch Luban <mluban@nvidia.com> Tested-by: Mitch Luban <mluban@nvidia.com>
Diffstat (limited to 'arch/arm/mach-tegra/board-ardbeg-memory.c')
-rw-r--r--arch/arm/mach-tegra/board-ardbeg-memory.c663
1 files changed, 219 insertions, 444 deletions
diff --git a/arch/arm/mach-tegra/board-ardbeg-memory.c b/arch/arm/mach-tegra/board-ardbeg-memory.c
index 47acac374e3e..62d15b5e2dd9 100644
--- a/arch/arm/mach-tegra/board-ardbeg-memory.c
+++ b/arch/arm/mach-tegra/board-ardbeg-memory.c
@@ -2731,8 +2731,8 @@ static struct tegra12_emc_table ardbeg_ddr3_emc_table_pm358[] = {
static struct tegra12_emc_table ardbeg_emc_table[] = {
{
- 0x18, /* V5.0.10 */
- "07_12750_02_V5.0.10_V0.8", /* DVFS table version */
+ 0x18, /* V5.0.12 */
+ "02_12750_01_V5.0.12_V0.9", /* DVFS table version */
12750, /* SDRAM frequency */
800, /* min voltage */
800, /* gpu min voltage */
@@ -2742,7 +2742,7 @@ static struct tegra12_emc_table ardbeg_emc_table[] = {
31, /* number of up_down_regs */
{
0x00000000, /* EMC_RC */
- 0x00000003, /* EMC_RFC */
+ 0x00000004, /* EMC_RFC */
0x00000000, /* EMC_RFC_SLR */
0x00000000, /* EMC_RAS */
0x00000000, /* EMC_RP */
@@ -2950,14 +2950,14 @@ static struct tegra12_emc_table ardbeg_emc_table[] = {
0x00000000, /* EMC_AUTO_CAL_CONFIG2 */
0x00000000, /* EMC_AUTO_CAL_CONFIG3 */
0xa1430000, /* EMC_AUTO_CAL_CONFIG */
- 0x80001221, /* Mode Register 0 */
- 0x80100003, /* Mode Register 1 */
- 0x80200008, /* Mode Register 2 */
+ 0x00001221, /* Mode Register 0 */
+ 0x00100003, /* Mode Register 1 */
+ 0x00200008, /* Mode Register 2 */
0x00000000, /* Mode Register 4 */
},
{
- 0x18, /* V5.0.10 */
- "07_20400_02_V5.0.10_V0.8", /* DVFS table version */
+ 0x18, /* V5.0.12 */
+ "02_20400_01_V5.0.12_V0.9", /* DVFS table version */
20400, /* SDRAM frequency */
800, /* min voltage */
800, /* gpu min voltage */
@@ -2967,7 +2967,7 @@ static struct tegra12_emc_table ardbeg_emc_table[] = {
31, /* number of up_down_regs */
{
0x00000000, /* EMC_RC */
- 0x00000005, /* EMC_RFC */
+ 0x00000007, /* EMC_RFC */
0x00000000, /* EMC_RFC_SLR */
0x00000000, /* EMC_RAS */
0x00000000, /* EMC_RP */
@@ -3006,8 +3006,8 @@ static struct tegra12_emc_table ardbeg_emc_table[] = {
0x00000000, /* EMC_ACT2PDEN */
0x00000007, /* EMC_AR2PDEN */
0x0000000f, /* EMC_RW2PDEN */
- 0x00000006, /* EMC_TXSR */
- 0x00000006, /* EMC_TXSRDLL */
+ 0x00000008, /* EMC_TXSR */
+ 0x00000008, /* EMC_TXSRDLL */
0x00000004, /* EMC_TCKE */
0x00000005, /* EMC_TCKESR */
0x00000004, /* EMC_TPD */
@@ -3128,7 +3128,7 @@ static struct tegra12_emc_table ardbeg_emc_table[] = {
0x00000006, /* MC_EMEM_ARB_TIMING_W2R */
0x06030203, /* MC_EMEM_ARB_DA_TURNS */
0x000a0402, /* MC_EMEM_ARB_DA_COVERS */
- 0x76230303, /* MC_EMEM_ARB_MISC0 */
+ 0x77430303, /* MC_EMEM_ARB_MISC0 */
0x001f0000, /* MC_EMEM_ARB_RING1_THROTTLE */
},
{
@@ -3175,14 +3175,14 @@ static struct tegra12_emc_table ardbeg_emc_table[] = {
0x00000000, /* EMC_AUTO_CAL_CONFIG2 */
0x00000000, /* EMC_AUTO_CAL_CONFIG3 */
0xa1430000, /* EMC_AUTO_CAL_CONFIG */
- 0x80001221, /* Mode Register 0 */
- 0x80100003, /* Mode Register 1 */
- 0x80200008, /* Mode Register 2 */
+ 0x00001221, /* Mode Register 0 */
+ 0x00100003, /* Mode Register 1 */
+ 0x00200008, /* Mode Register 2 */
0x00000000, /* Mode Register 4 */
},
{
- 0x18, /* V5.0.10 */
- "07_40800_02_V5.0.10_V0.8", /* DVFS table version */
+ 0x18, /* V5.0.12 */
+ "02_40800_01_V5.0.12_V0.9", /* DVFS table version */
40800, /* SDRAM frequency */
800, /* min voltage */
800, /* gpu min voltage */
@@ -3192,7 +3192,7 @@ static struct tegra12_emc_table ardbeg_emc_table[] = {
31, /* number of up_down_regs */
{
0x00000001, /* EMC_RC */
- 0x0000000a, /* EMC_RFC */
+ 0x0000000e, /* EMC_RFC */
0x00000000, /* EMC_RFC_SLR */
0x00000001, /* EMC_RAS */
0x00000000, /* EMC_RP */
@@ -3229,10 +3229,10 @@ static struct tegra12_emc_table ardbeg_emc_table[] = {
0x00000002, /* EMC_PDEX2RD */
0x00000001, /* EMC_PCHG2PDEN */
0x00000000, /* EMC_ACT2PDEN */
- 0x00000008, /* EMC_AR2PDEN */
+ 0x0000000c, /* EMC_AR2PDEN */
0x0000000f, /* EMC_RW2PDEN */
- 0x0000000c, /* EMC_TXSR */
- 0x0000000c, /* EMC_TXSRDLL */
+ 0x0000000f, /* EMC_TXSR */
+ 0x0000000f, /* EMC_TXSRDLL */
0x00000004, /* EMC_TCKE */
0x00000005, /* EMC_TCKESR */
0x00000004, /* EMC_TPD */
@@ -3353,7 +3353,7 @@ static struct tegra12_emc_table ardbeg_emc_table[] = {
0x00000006, /* MC_EMEM_ARB_TIMING_W2R */
0x06030203, /* MC_EMEM_ARB_DA_TURNS */
0x000a0402, /* MC_EMEM_ARB_DA_COVERS */
- 0x74a30303, /* MC_EMEM_ARB_MISC0 */
+ 0x75e30303, /* MC_EMEM_ARB_MISC0 */
0x001f0000, /* MC_EMEM_ARB_RING1_THROTTLE */
},
{
@@ -3400,14 +3400,14 @@ static struct tegra12_emc_table ardbeg_emc_table[] = {
0x00000000, /* EMC_AUTO_CAL_CONFIG2 */
0x00000000, /* EMC_AUTO_CAL_CONFIG3 */
0xa1430000, /* EMC_AUTO_CAL_CONFIG */
- 0x80001221, /* Mode Register 0 */
- 0x80100003, /* Mode Register 1 */
- 0x80200008, /* Mode Register 2 */
+ 0x00001221, /* Mode Register 0 */
+ 0x00100003, /* Mode Register 1 */
+ 0x00200008, /* Mode Register 2 */
0x00000000, /* Mode Register 4 */
},
{
- 0x18, /* V5.0.10 */
- "07_68000_02_V5.0.10_V0.8", /* DVFS table version */
+ 0x18, /* V5.0.12 */
+ "02_68000_01_V5.0.12_V0.9", /* DVFS table version */
68000, /* SDRAM frequency */
800, /* min voltage */
800, /* gpu min voltage */
@@ -3417,7 +3417,7 @@ static struct tegra12_emc_table ardbeg_emc_table[] = {
31, /* number of up_down_regs */
{
0x00000003, /* EMC_RC */
- 0x00000011, /* EMC_RFC */
+ 0x00000017, /* EMC_RFC */
0x00000000, /* EMC_RFC_SLR */
0x00000002, /* EMC_RAS */
0x00000000, /* EMC_RP */
@@ -3454,10 +3454,10 @@ static struct tegra12_emc_table ardbeg_emc_table[] = {
0x00000002, /* EMC_PDEX2RD */
0x00000001, /* EMC_PCHG2PDEN */
0x00000000, /* EMC_ACT2PDEN */
- 0x0000000f, /* EMC_AR2PDEN */
+ 0x00000015, /* EMC_AR2PDEN */
0x0000000f, /* EMC_RW2PDEN */
- 0x00000013, /* EMC_TXSR */
- 0x00000013, /* EMC_TXSRDLL */
+ 0x00000019, /* EMC_TXSR */
+ 0x00000019, /* EMC_TXSRDLL */
0x00000004, /* EMC_TCKE */
0x00000005, /* EMC_TCKESR */
0x00000004, /* EMC_TPD */
@@ -3578,7 +3578,7 @@ static struct tegra12_emc_table ardbeg_emc_table[] = {
0x00000006, /* MC_EMEM_ARB_TIMING_W2R */
0x06030203, /* MC_EMEM_ARB_DA_TURNS */
0x000a0402, /* MC_EMEM_ARB_DA_COVERS */
- 0x74230403, /* MC_EMEM_ARB_MISC0 */
+ 0x75430403, /* MC_EMEM_ARB_MISC0 */
0x001f0000, /* MC_EMEM_ARB_RING1_THROTTLE */
},
{
@@ -3625,14 +3625,14 @@ static struct tegra12_emc_table ardbeg_emc_table[] = {
0x00000000, /* EMC_AUTO_CAL_CONFIG2 */
0x00000000, /* EMC_AUTO_CAL_CONFIG3 */
0xa1430000, /* EMC_AUTO_CAL_CONFIG */
- 0x80001221, /* Mode Register 0 */
- 0x80100003, /* Mode Register 1 */
- 0x80200008, /* Mode Register 2 */
+ 0x00001221, /* Mode Register 0 */
+ 0x00100003, /* Mode Register 1 */
+ 0x00200008, /* Mode Register 2 */
0x00000000, /* Mode Register 4 */
},
{
- 0x18, /* V5.0.10 */
- "07_102000_02_V5.0.10_V0.8", /* DVFS table version */
+ 0x18, /* V5.0.12 */
+ "02_102000_02_V5.0.12_V0.9", /* DVFS table version */
102000, /* SDRAM frequency */
800, /* min voltage */
800, /* gpu min voltage */
@@ -3642,7 +3642,7 @@ static struct tegra12_emc_table ardbeg_emc_table[] = {
31, /* number of up_down_regs */
{
0x00000004, /* EMC_RC */
- 0x0000001a, /* EMC_RFC */
+ 0x00000023, /* EMC_RFC */
0x00000000, /* EMC_RFC_SLR */
0x00000003, /* EMC_RAS */
0x00000001, /* EMC_RP */
@@ -3679,10 +3679,10 @@ static struct tegra12_emc_table ardbeg_emc_table[] = {
0x00000002, /* EMC_PDEX2RD */
0x00000001, /* EMC_PCHG2PDEN */
0x00000000, /* EMC_ACT2PDEN */
- 0x00000018, /* EMC_AR2PDEN */
+ 0x00000021, /* EMC_AR2PDEN */
0x0000000f, /* EMC_RW2PDEN */
- 0x0000001c, /* EMC_TXSR */
- 0x0000001c, /* EMC_TXSRDLL */
+ 0x00000025, /* EMC_TXSR */
+ 0x00000025, /* EMC_TXSRDLL */
0x00000004, /* EMC_TCKE */
0x00000005, /* EMC_TCKESR */
0x00000004, /* EMC_TPD */
@@ -3803,7 +3803,7 @@ static struct tegra12_emc_table ardbeg_emc_table[] = {
0x00000006, /* MC_EMEM_ARB_TIMING_W2R */
0x06030203, /* MC_EMEM_ARB_DA_TURNS */
0x000a0403, /* MC_EMEM_ARB_DA_COVERS */
- 0x73c30504, /* MC_EMEM_ARB_MISC0 */
+ 0x74e30504, /* MC_EMEM_ARB_MISC0 */
0x001f0000, /* MC_EMEM_ARB_RING1_THROTTLE */
},
{
@@ -3850,14 +3850,14 @@ static struct tegra12_emc_table ardbeg_emc_table[] = {
0x00000000, /* EMC_AUTO_CAL_CONFIG2 */
0x00000000, /* EMC_AUTO_CAL_CONFIG3 */
0xa1430000, /* EMC_AUTO_CAL_CONFIG */
- 0x80001221, /* Mode Register 0 */
- 0x80100003, /* Mode Register 1 */
- 0x80200008, /* Mode Register 2 */
+ 0x00001221, /* Mode Register 0 */
+ 0x00100003, /* Mode Register 1 */
+ 0x00200008, /* Mode Register 2 */
0x00000000, /* Mode Register 4 */
},
{
- 0x18, /* V5.0.10 */
- "07_204000_03_V5.0.10_V0.8", /* DVFS table version */
+ 0x18, /* V5.0.12 */
+ "02_204000_02_V5.0.12_V0.9", /* DVFS table version */
204000, /* SDRAM frequency */
800, /* min voltage */
800, /* gpu min voltage */
@@ -3867,7 +3867,7 @@ static struct tegra12_emc_table ardbeg_emc_table[] = {
31, /* number of up_down_regs */
{
0x00000009, /* EMC_RC */
- 0x00000035, /* EMC_RFC */
+ 0x00000047, /* EMC_RFC */
0x00000000, /* EMC_RFC_SLR */
0x00000006, /* EMC_RAS */
0x00000002, /* EMC_RP */
@@ -3904,10 +3904,10 @@ static struct tegra12_emc_table ardbeg_emc_table[] = {
0x00000002, /* EMC_PDEX2RD */
0x00000001, /* EMC_PCHG2PDEN */
0x00000000, /* EMC_ACT2PDEN */
- 0x00000032, /* EMC_AR2PDEN */
+ 0x00000044, /* EMC_AR2PDEN */
0x0000000f, /* EMC_RW2PDEN */
- 0x00000038, /* EMC_TXSR */
- 0x00000038, /* EMC_TXSRDLL */
+ 0x0000004a, /* EMC_TXSR */
+ 0x0000004a, /* EMC_TXSRDLL */
0x00000004, /* EMC_TCKE */
0x00000005, /* EMC_TCKESR */
0x00000004, /* EMC_TPD */
@@ -3922,22 +3922,22 @@ static struct tegra12_emc_table ardbeg_emc_table[] = {
0x1069a298, /* EMC_FBIO_CFG5 */
0x002c00a0, /* EMC_CFG_DIG_DLL */
0x00008000, /* EMC_CFG_DIG_DLL_PERIOD */
- 0x00064000, /* EMC_DLL_XFORM_DQS0 */
- 0x00064000, /* EMC_DLL_XFORM_DQS1 */
- 0x00064000, /* EMC_DLL_XFORM_DQS2 */
- 0x00064000, /* EMC_DLL_XFORM_DQS3 */
- 0x00064000, /* EMC_DLL_XFORM_DQS4 */
- 0x00064000, /* EMC_DLL_XFORM_DQS5 */
- 0x00064000, /* EMC_DLL_XFORM_DQS6 */
- 0x00064000, /* EMC_DLL_XFORM_DQS7 */
- 0x00064000, /* EMC_DLL_XFORM_DQS8 */
- 0x00064000, /* EMC_DLL_XFORM_DQS9 */
- 0x00064000, /* EMC_DLL_XFORM_DQS10 */
- 0x00064000, /* EMC_DLL_XFORM_DQS11 */
- 0x00064000, /* EMC_DLL_XFORM_DQS12 */
- 0x00064000, /* EMC_DLL_XFORM_DQS13 */
- 0x00064000, /* EMC_DLL_XFORM_DQS14 */
- 0x00064000, /* EMC_DLL_XFORM_DQS15 */
+ 0x00070000, /* EMC_DLL_XFORM_DQS0 */
+ 0x00070000, /* EMC_DLL_XFORM_DQS1 */
+ 0x00070000, /* EMC_DLL_XFORM_DQS2 */
+ 0x00070000, /* EMC_DLL_XFORM_DQS3 */
+ 0x00070000, /* EMC_DLL_XFORM_DQS4 */
+ 0x00070000, /* EMC_DLL_XFORM_DQS5 */
+ 0x00070000, /* EMC_DLL_XFORM_DQS6 */
+ 0x00070000, /* EMC_DLL_XFORM_DQS7 */
+ 0x00070000, /* EMC_DLL_XFORM_DQS8 */
+ 0x00070000, /* EMC_DLL_XFORM_DQS9 */
+ 0x00070000, /* EMC_DLL_XFORM_DQS10 */
+ 0x00070000, /* EMC_DLL_XFORM_DQS11 */
+ 0x00070000, /* EMC_DLL_XFORM_DQS12 */
+ 0x00070000, /* EMC_DLL_XFORM_DQS13 */
+ 0x00070000, /* EMC_DLL_XFORM_DQS14 */
+ 0x00070000, /* EMC_DLL_XFORM_DQS15 */
0x00000000, /* EMC_DLL_XFORM_QUSE0 */
0x00000000, /* EMC_DLL_XFORM_QUSE1 */
0x00000000, /* EMC_DLL_XFORM_QUSE2 */
@@ -3976,14 +3976,14 @@ static struct tegra12_emc_table ardbeg_emc_table[] = {
0x00000000, /* EMC_DLI_TRIM_TXDQS13 */
0x00000000, /* EMC_DLI_TRIM_TXDQS14 */
0x00000000, /* EMC_DLI_TRIM_TXDQS15 */
- 0x00060000, /* EMC_DLL_XFORM_DQ0 */
- 0x00060000, /* EMC_DLL_XFORM_DQ1 */
- 0x00060000, /* EMC_DLL_XFORM_DQ2 */
- 0x00060000, /* EMC_DLL_XFORM_DQ3 */
- 0x00006000, /* EMC_DLL_XFORM_DQ4 */
- 0x00006000, /* EMC_DLL_XFORM_DQ5 */
- 0x00006000, /* EMC_DLL_XFORM_DQ6 */
- 0x00006000, /* EMC_DLL_XFORM_DQ7 */
+ 0x00070000, /* EMC_DLL_XFORM_DQ0 */
+ 0x00070000, /* EMC_DLL_XFORM_DQ1 */
+ 0x00070000, /* EMC_DLL_XFORM_DQ2 */
+ 0x00070000, /* EMC_DLL_XFORM_DQ3 */
+ 0x00007000, /* EMC_DLL_XFORM_DQ4 */
+ 0x00007000, /* EMC_DLL_XFORM_DQ5 */
+ 0x00007000, /* EMC_DLL_XFORM_DQ6 */
+ 0x00007000, /* EMC_DLL_XFORM_DQ7 */
0x10000280, /* EMC_XM2CMDPADCTRL */
0x00000000, /* EMC_XM2CMDPADCTRL4 */
0x00111111, /* EMC_XM2CMDPADCTRL5 */
@@ -4028,7 +4028,7 @@ static struct tegra12_emc_table ardbeg_emc_table[] = {
0x00000006, /* MC_EMEM_ARB_TIMING_W2R */
0x06040203, /* MC_EMEM_ARB_DA_TURNS */
0x000a0404, /* MC_EMEM_ARB_DA_COVERS */
- 0x73840a05, /* MC_EMEM_ARB_MISC0 */
+ 0x74a40a05, /* MC_EMEM_ARB_MISC0 */
0x001f0000, /* MC_EMEM_ARB_RING1_THROTTLE */
},
{
@@ -4075,16 +4075,16 @@ static struct tegra12_emc_table ardbeg_emc_table[] = {
0x00000000, /* EMC_AUTO_CAL_CONFIG2 */
0x00000000, /* EMC_AUTO_CAL_CONFIG3 */
0xa1430000, /* EMC_AUTO_CAL_CONFIG */
- 0x80001221, /* Mode Register 0 */
- 0x80100003, /* Mode Register 1 */
- 0x80200008, /* Mode Register 2 */
+ 0x00001221, /* Mode Register 0 */
+ 0x00100003, /* Mode Register 1 */
+ 0x00200008, /* Mode Register 2 */
0x00000000, /* Mode Register 4 */
},
{
- 0x18, /* V5.0.10 */
- "07_300000_03_V5.0.10_V0.8", /* DVFS table version */
+ 0x18, /* V5.0.12 */
+ "02_300000_02_V5.0.12_V0.9", /* DVFS table version */
300000, /* SDRAM frequency */
- 810, /* min voltage */
+ 820, /* min voltage */
800, /* gpu min voltage */
"pllc_out0", /* clock source id */
0x20000002, /* CLK_SOURCE_EMC */
@@ -4092,7 +4092,7 @@ static struct tegra12_emc_table ardbeg_emc_table[] = {
31, /* number of up_down_regs */
{
0x0000000d, /* EMC_RC */
- 0x0000004d, /* EMC_RFC */
+ 0x00000067, /* EMC_RFC */
0x00000000, /* EMC_RFC_SLR */
0x00000009, /* EMC_RAS */
0x00000003, /* EMC_RP */
@@ -4129,9 +4129,9 @@ static struct tegra12_emc_table ardbeg_emc_table[] = {
0x00000008, /* EMC_PDEX2RD */
0x00000001, /* EMC_PCHG2PDEN */
0x00000000, /* EMC_ACT2PDEN */
- 0x0000004b, /* EMC_AR2PDEN */
+ 0x00000065, /* EMC_AR2PDEN */
0x0000000e, /* EMC_RW2PDEN */
- 0x00000052, /* EMC_TXSR */
+ 0x0000006c, /* EMC_TXSR */
0x00000200, /* EMC_TXSRDLL */
0x00000004, /* EMC_TCKE */
0x00000005, /* EMC_TCKESR */
@@ -4171,11 +4171,11 @@ static struct tegra12_emc_table ardbeg_emc_table[] = {
0x00000000, /* EMC_DLL_XFORM_QUSE5 */
0x00000000, /* EMC_DLL_XFORM_QUSE6 */
0x00000000, /* EMC_DLL_XFORM_QUSE7 */
- 0x00040000, /* EMC_DLL_XFORM_ADDR0 */
- 0x00040000, /* EMC_DLL_XFORM_ADDR1 */
+ 0x00098000, /* EMC_DLL_XFORM_ADDR0 */
+ 0x00098000, /* EMC_DLL_XFORM_ADDR1 */
0x00000000, /* EMC_DLL_XFORM_ADDR2 */
- 0x00040000, /* EMC_DLL_XFORM_ADDR3 */
- 0x00040000, /* EMC_DLL_XFORM_ADDR4 */
+ 0x00098000, /* EMC_DLL_XFORM_ADDR3 */
+ 0x00098000, /* EMC_DLL_XFORM_ADDR4 */
0x00000000, /* EMC_DLL_XFORM_ADDR5 */
0x00000000, /* EMC_DLL_XFORM_QUSE8 */
0x00000000, /* EMC_DLL_XFORM_QUSE9 */
@@ -4230,8 +4230,8 @@ static struct tegra12_emc_table ardbeg_emc_table[] = {
0x00000000, /* EMC_FBIO_SPARE */
0x00020000, /* EMC_ZCAL_INTERVAL */
0x00000100, /* EMC_ZCAL_WAIT_CNT */
- 0x0173000e, /* EMC_MRS_WAIT_CNT */
- 0x0173000e, /* EMC_MRS_WAIT_CNT2 */
+ 0x0117000e, /* EMC_MRS_WAIT_CNT */
+ 0x0117000e, /* EMC_MRS_WAIT_CNT2 */
0x00000000, /* EMC_CTT */
0x00000003, /* EMC_CTT_DURATION */
0x0000d3b3, /* EMC_CFG_PIPE */
@@ -4300,16 +4300,16 @@ static struct tegra12_emc_table ardbeg_emc_table[] = {
0x00000000, /* EMC_AUTO_CAL_CONFIG2 */
0x00000000, /* EMC_AUTO_CAL_CONFIG3 */
0xa1430000, /* EMC_AUTO_CAL_CONFIG */
- 0x80000321, /* Mode Register 0 */
- 0x80100002, /* Mode Register 1 */
- 0x80200000, /* Mode Register 2 */
+ 0x00000321, /* Mode Register 0 */
+ 0x00100002, /* Mode Register 1 */
+ 0x00200000, /* Mode Register 2 */
0x00000000, /* Mode Register 4 */
},
{
- 0x18, /* V5.0.10 */
- "07_396000_04_V5.0.10_V0.8", /* DVFS table version */
+ 0x18, /* V5.0.12 */
+ "02_396000_02_V5.0.12_V0.9", /* DVFS table version */
396000, /* SDRAM frequency */
- 860, /* min voltage */
+ 850, /* min voltage */
900, /* gpu min voltage */
"pllm_out0", /* clock source id */
0x00000002, /* CLK_SOURCE_EMC */
@@ -4317,7 +4317,7 @@ static struct tegra12_emc_table ardbeg_emc_table[] = {
31, /* number of up_down_regs */
{
0x00000011, /* EMC_RC */
- 0x00000066, /* EMC_RFC */
+ 0x00000089, /* EMC_RFC */
0x00000000, /* EMC_RFC_SLR */
0x0000000c, /* EMC_RAS */
0x00000004, /* EMC_RP */
@@ -4345,8 +4345,8 @@ static struct tegra12_emc_table ardbeg_emc_table[] = {
0x00000000, /* EMC_CDB_CNTL_3 */
0x00000000, /* EMC_QRST */
0x0000000f, /* EMC_QSAFE */
- 0x0000000e, /* EMC_RDV */
- 0x00000010, /* EMC_RDV_MASK */
+ 0x00000010, /* EMC_RDV */
+ 0x00000012, /* EMC_RDV_MASK */
0x00000bd1, /* EMC_REFRESH */
0x00000000, /* EMC_BURST_REFRESH_NUM */
0x000002f4, /* EMC_PRE_REFRESH_REQ_CNT */
@@ -4354,9 +4354,9 @@ static struct tegra12_emc_table ardbeg_emc_table[] = {
0x00000008, /* EMC_PDEX2RD */
0x00000001, /* EMC_PCHG2PDEN */
0x00000000, /* EMC_ACT2PDEN */
- 0x00000063, /* EMC_AR2PDEN */
+ 0x00000087, /* EMC_AR2PDEN */
0x0000000f, /* EMC_RW2PDEN */
- 0x0000006c, /* EMC_TXSR */
+ 0x0000008f, /* EMC_TXSR */
0x00000200, /* EMC_TXSRDLL */
0x00000004, /* EMC_TCKE */
0x00000005, /* EMC_TCKESR */
@@ -4396,11 +4396,11 @@ static struct tegra12_emc_table ardbeg_emc_table[] = {
0x00000000, /* EMC_DLL_XFORM_QUSE5 */
0x00000000, /* EMC_DLL_XFORM_QUSE6 */
0x00000000, /* EMC_DLL_XFORM_QUSE7 */
- 0x00040000, /* EMC_DLL_XFORM_ADDR0 */
- 0x00040000, /* EMC_DLL_XFORM_ADDR1 */
+ 0x00070000, /* EMC_DLL_XFORM_ADDR0 */
+ 0x00070000, /* EMC_DLL_XFORM_ADDR1 */
0x00000000, /* EMC_DLL_XFORM_ADDR2 */
- 0x00040000, /* EMC_DLL_XFORM_ADDR3 */
- 0x00040000, /* EMC_DLL_XFORM_ADDR4 */
+ 0x00070000, /* EMC_DLL_XFORM_ADDR3 */
+ 0x00070000, /* EMC_DLL_XFORM_ADDR4 */
0x00000000, /* EMC_DLL_XFORM_ADDR5 */
0x00000000, /* EMC_DLL_XFORM_QUSE8 */
0x00000000, /* EMC_DLL_XFORM_QUSE9 */
@@ -4455,11 +4455,11 @@ static struct tegra12_emc_table ardbeg_emc_table[] = {
0x00000000, /* EMC_FBIO_SPARE */
0x00020000, /* EMC_ZCAL_INTERVAL */
0x00000100, /* EMC_ZCAL_WAIT_CNT */
- 0x015b000e, /* EMC_MRS_WAIT_CNT */
- 0x015b000e, /* EMC_MRS_WAIT_CNT2 */
+ 0x00f5000e, /* EMC_MRS_WAIT_CNT */
+ 0x00f5000e, /* EMC_MRS_WAIT_CNT2 */
0x00000000, /* EMC_CTT */
0x00000003, /* EMC_CTT_DURATION */
- 0x0000d3b3, /* EMC_CFG_PIPE */
+ 0x000052a3, /* EMC_CFG_PIPE */
0x8000188b, /* EMC_DYN_SELF_REF_CONTROL */
0x00000009, /* EMC_QPOP */
0x0f000005, /* MC_EMEM_ARB_CFG */
@@ -4518,23 +4518,23 @@ static struct tegra12_emc_table ardbeg_emc_table[] = {
0x001fffff, /* EMC_AUTO_CAL_INTERVAL */
0x00000802, /* EMC_CTT_TERM_CTRL */
0x73340000, /* EMC_CFG */
- 0x0000088d, /* EMC_CFG_2 */
+ 0x00000895, /* EMC_CFG_2 */
0x00040008, /* EMC_SEL_DPD_CTRL */
0x002c0068, /* EMC_CFG_DIG_DLL */
0x00000000, /* EMC_BGBIAS_CTL0 */
0x00000000, /* EMC_AUTO_CAL_CONFIG2 */
0x00000000, /* EMC_AUTO_CAL_CONFIG3 */
0xa1430000, /* EMC_AUTO_CAL_CONFIG */
- 0x80000521, /* Mode Register 0 */
- 0x80100002, /* Mode Register 1 */
- 0x80200000, /* Mode Register 2 */
+ 0x00000521, /* Mode Register 0 */
+ 0x00100002, /* Mode Register 1 */
+ 0x00200000, /* Mode Register 2 */
0x00000000, /* Mode Register 4 */
},
{
- 0x18, /* V5.0.10 */
- "07_528000_03_V5.0.10_V0.8", /* DVFS table version */
+ 0x18, /* V5.0.12 */
+ "02_528000_02_V5.0.12_V0.9", /* DVFS table version */
528000, /* SDRAM frequency */
- 900, /* min voltage */
+ 870, /* min voltage */
900, /* gpu min voltage */
"pllm_ud", /* clock source id */
0x80000000, /* CLK_SOURCE_EMC */
@@ -4542,7 +4542,7 @@ static struct tegra12_emc_table ardbeg_emc_table[] = {
31, /* number of up_down_regs */
{
0x00000018, /* EMC_RC */
- 0x00000088, /* EMC_RFC */
+ 0x000000b7, /* EMC_RFC */
0x00000000, /* EMC_RFC_SLR */
0x00000010, /* EMC_RAS */
0x00000006, /* EMC_RP */
@@ -4555,20 +4555,20 @@ static struct tegra12_emc_table ardbeg_emc_table[] = {
0x00000002, /* EMC_RRD */
0x00000002, /* EMC_REXT */
0x00000000, /* EMC_WEXT */
- 0x00000004, /* EMC_WDV */
- 0x00000004, /* EMC_WDV_MASK */
- 0x00000008, /* EMC_QUSE */
+ 0x00000003, /* EMC_WDV */
+ 0x00000003, /* EMC_WDV_MASK */
+ 0x00000007, /* EMC_QUSE */
0x00000002, /* EMC_QUSE_WIDTH */
0x00000000, /* EMC_IBDLY */
- 0x00000003, /* EMC_EINPUT */
+ 0x00000002, /* EMC_EINPUT */
0x00000009, /* EMC_EINPUT_DURATION */
- 0x00050000, /* EMC_PUTERM_EXTRA */
+ 0x00040000, /* EMC_PUTERM_EXTRA */
0x00000003, /* EMC_PUTERM_WIDTH */
0x00000000, /* EMC_PUTERM_ADJ */
0x00000000, /* EMC_CDB_CNTL_1 */
0x00000000, /* EMC_CDB_CNTL_2 */
0x00000000, /* EMC_CDB_CNTL_3 */
- 0x00000002, /* EMC_QRST */
+ 0x00000001, /* EMC_QRST */
0x00000010, /* EMC_QSAFE */
0x00000013, /* EMC_RDV */
0x00000015, /* EMC_RDV_MASK */
@@ -4579,9 +4579,9 @@ static struct tegra12_emc_table ardbeg_emc_table[] = {
0x0000000b, /* EMC_PDEX2RD */
0x00000001, /* EMC_PCHG2PDEN */
0x00000000, /* EMC_ACT2PDEN */
- 0x00000085, /* EMC_AR2PDEN */
+ 0x000000b4, /* EMC_AR2PDEN */
0x00000012, /* EMC_RW2PDEN */
- 0x00000090, /* EMC_TXSR */
+ 0x000000bf, /* EMC_TXSR */
0x00000200, /* EMC_TXSRDLL */
0x00000004, /* EMC_TCKE */
0x00000005, /* EMC_TCKESR */
@@ -4680,13 +4680,13 @@ static struct tegra12_emc_table ardbeg_emc_table[] = {
0x00000000, /* EMC_FBIO_SPARE */
0x00020000, /* EMC_ZCAL_INTERVAL */
0x00000100, /* EMC_ZCAL_WAIT_CNT */
- 0x0139000e, /* EMC_MRS_WAIT_CNT */
- 0x0139000e, /* EMC_MRS_WAIT_CNT2 */
+ 0x00c8000e, /* EMC_MRS_WAIT_CNT */
+ 0x00c8000e, /* EMC_MRS_WAIT_CNT2 */
0x00000000, /* EMC_CTT */
0x00000003, /* EMC_CTT_DURATION */
- 0x000052a0, /* EMC_CFG_PIPE */
+ 0x000042a0, /* EMC_CFG_PIPE */
0x80002062, /* EMC_DYN_SELF_REF_CONTROL */
- 0x0000000c, /* EMC_QPOP */
+ 0x0000000b, /* EMC_QPOP */
0x0f000007, /* MC_EMEM_ARB_CFG */
0x80000040, /* MC_EMEM_ARB_OUTSTANDING_REQ */
0x00000002, /* MC_EMEM_ARB_TIMING_RCD */
@@ -4703,7 +4703,7 @@ static struct tegra12_emc_table ardbeg_emc_table[] = {
0x00000006, /* MC_EMEM_ARB_TIMING_W2R */
0x06050202, /* MC_EMEM_ARB_DA_TURNS */
0x0010090c, /* MC_EMEM_ARB_DA_COVERS */
- 0x7428180d, /* MC_EMEM_ARB_MISC0 */
+ 0x7488180d, /* MC_EMEM_ARB_MISC0 */
0x001f0000, /* MC_EMEM_ARB_RING1_THROTTLE */
},
{
@@ -4743,21 +4743,21 @@ static struct tegra12_emc_table ardbeg_emc_table[] = {
0x001fffff, /* EMC_AUTO_CAL_INTERVAL */
0x00000802, /* EMC_CTT_TERM_CTRL */
0x73300000, /* EMC_CFG */
- 0x00000895, /* EMC_CFG_2 */
+ 0x0000089d, /* EMC_CFG_2 */
0x00040008, /* EMC_SEL_DPD_CTRL */
0xe0120069, /* EMC_CFG_DIG_DLL */
0x00000000, /* EMC_BGBIAS_CTL0 */
0x00000000, /* EMC_AUTO_CAL_CONFIG2 */
0x00000000, /* EMC_AUTO_CAL_CONFIG3 */
0xa1430000, /* EMC_AUTO_CAL_CONFIG */
- 0x80000941, /* Mode Register 0 */
- 0x80100002, /* Mode Register 1 */
- 0x80200008, /* Mode Register 2 */
+ 0x00000941, /* Mode Register 0 */
+ 0x00100002, /* Mode Register 1 */
+ 0x00200008, /* Mode Register 2 */
0x00000000, /* Mode Register 4 */
},
{
- 0x18, /* V5.0.10 */
- "07_600000_04_V5.0.10_V0.8", /* DVFS table version */
+ 0x18, /* V5.0.12 */
+ "02_600000_01_V5.0.12_V0.9", /* DVFS table version */
600000, /* SDRAM frequency */
910, /* min voltage */
900, /* gpu min voltage */
@@ -4767,7 +4767,7 @@ static struct tegra12_emc_table ardbeg_emc_table[] = {
31, /* number of up_down_regs */
{
0x0000001b, /* EMC_RC */
- 0x0000009b, /* EMC_RFC */
+ 0x000000d0, /* EMC_RFC */
0x00000000, /* EMC_RFC_SLR */
0x00000013, /* EMC_RAS */
0x00000007, /* EMC_RP */
@@ -4804,9 +4804,9 @@ static struct tegra12_emc_table ardbeg_emc_table[] = {
0x0000000d, /* EMC_PDEX2RD */
0x00000001, /* EMC_PCHG2PDEN */
0x00000000, /* EMC_ACT2PDEN */
- 0x00000097, /* EMC_AR2PDEN */
+ 0x000000cc, /* EMC_AR2PDEN */
0x00000015, /* EMC_RW2PDEN */
- 0x000000a3, /* EMC_TXSR */
+ 0x000000d8, /* EMC_TXSR */
0x00000200, /* EMC_TXSRDLL */
0x00000004, /* EMC_TCKE */
0x00000005, /* EMC_TCKESR */
@@ -4822,22 +4822,22 @@ static struct tegra12_emc_table ardbeg_emc_table[] = {
0x1049b098, /* EMC_FBIO_CFG5 */
0xe00e00b1, /* EMC_CFG_DIG_DLL */
0x00008000, /* EMC_CFG_DIG_DLL_PERIOD */
- 0x0000000a, /* EMC_DLL_XFORM_DQS0 */
- 0x0000000a, /* EMC_DLL_XFORM_DQS1 */
- 0x0000000a, /* EMC_DLL_XFORM_DQS2 */
- 0x0000000a, /* EMC_DLL_XFORM_DQS3 */
- 0x0000000a, /* EMC_DLL_XFORM_DQS4 */
- 0x0000000a, /* EMC_DLL_XFORM_DQS5 */
- 0x0000000a, /* EMC_DLL_XFORM_DQS6 */
- 0x0000000a, /* EMC_DLL_XFORM_DQS7 */
- 0x0000000a, /* EMC_DLL_XFORM_DQS8 */
- 0x0000000a, /* EMC_DLL_XFORM_DQS9 */
- 0x0000000a, /* EMC_DLL_XFORM_DQS10 */
- 0x0000000a, /* EMC_DLL_XFORM_DQS11 */
- 0x0000000a, /* EMC_DLL_XFORM_DQS12 */
- 0x0000000a, /* EMC_DLL_XFORM_DQS13 */
- 0x0000000a, /* EMC_DLL_XFORM_DQS14 */
- 0x0000000a, /* EMC_DLL_XFORM_DQS15 */
+ 0x00000008, /* EMC_DLL_XFORM_DQS0 */
+ 0x00000008, /* EMC_DLL_XFORM_DQS1 */
+ 0x00000008, /* EMC_DLL_XFORM_DQS2 */
+ 0x00000008, /* EMC_DLL_XFORM_DQS3 */
+ 0x00000008, /* EMC_DLL_XFORM_DQS4 */
+ 0x00000008, /* EMC_DLL_XFORM_DQS5 */
+ 0x00000008, /* EMC_DLL_XFORM_DQS6 */
+ 0x00000008, /* EMC_DLL_XFORM_DQS7 */
+ 0x00000008, /* EMC_DLL_XFORM_DQS8 */
+ 0x00000008, /* EMC_DLL_XFORM_DQS9 */
+ 0x00000008, /* EMC_DLL_XFORM_DQS10 */
+ 0x00000008, /* EMC_DLL_XFORM_DQS11 */
+ 0x00000008, /* EMC_DLL_XFORM_DQS12 */
+ 0x00000008, /* EMC_DLL_XFORM_DQS13 */
+ 0x00000008, /* EMC_DLL_XFORM_DQS14 */
+ 0x00000008, /* EMC_DLL_XFORM_DQS15 */
0x00000000, /* EMC_DLL_XFORM_QUSE0 */
0x00000000, /* EMC_DLL_XFORM_QUSE1 */
0x00000000, /* EMC_DLL_XFORM_QUSE2 */
@@ -4846,11 +4846,11 @@ static struct tegra12_emc_table ardbeg_emc_table[] = {
0x00000000, /* EMC_DLL_XFORM_QUSE5 */
0x00000000, /* EMC_DLL_XFORM_QUSE6 */
0x00000000, /* EMC_DLL_XFORM_QUSE7 */
- 0x0004c000, /* EMC_DLL_XFORM_ADDR0 */
- 0x0004c000, /* EMC_DLL_XFORM_ADDR1 */
+ 0x00048000, /* EMC_DLL_XFORM_ADDR0 */
+ 0x00048000, /* EMC_DLL_XFORM_ADDR1 */
0x00000000, /* EMC_DLL_XFORM_ADDR2 */
- 0x0004c000, /* EMC_DLL_XFORM_ADDR3 */
- 0x0004c000, /* EMC_DLL_XFORM_ADDR4 */
+ 0x00048000, /* EMC_DLL_XFORM_ADDR3 */
+ 0x00048000, /* EMC_DLL_XFORM_ADDR4 */
0x00000000, /* EMC_DLL_XFORM_ADDR5 */
0x00000000, /* EMC_DLL_XFORM_QUSE8 */
0x00000000, /* EMC_DLL_XFORM_QUSE9 */
@@ -4876,14 +4876,14 @@ static struct tegra12_emc_table ardbeg_emc_table[] = {
0x00000000, /* EMC_DLI_TRIM_TXDQS13 */
0x00000000, /* EMC_DLI_TRIM_TXDQS14 */
0x00000000, /* EMC_DLI_TRIM_TXDQS15 */
- 0x0000000a, /* EMC_DLL_XFORM_DQ0 */
- 0x0000000a, /* EMC_DLL_XFORM_DQ1 */
- 0x0000000a, /* EMC_DLL_XFORM_DQ2 */
- 0x0000000a, /* EMC_DLL_XFORM_DQ3 */
- 0x0000000a, /* EMC_DLL_XFORM_DQ4 */
- 0x0000000a, /* EMC_DLL_XFORM_DQ5 */
- 0x0000000a, /* EMC_DLL_XFORM_DQ6 */
- 0x0000000a, /* EMC_DLL_XFORM_DQ7 */
+ 0x0000000b, /* EMC_DLL_XFORM_DQ0 */
+ 0x0000000b, /* EMC_DLL_XFORM_DQ1 */
+ 0x0000000b, /* EMC_DLL_XFORM_DQ2 */
+ 0x0000000b, /* EMC_DLL_XFORM_DQ3 */
+ 0x0000000b, /* EMC_DLL_XFORM_DQ4 */
+ 0x0000000b, /* EMC_DLL_XFORM_DQ5 */
+ 0x0000000b, /* EMC_DLL_XFORM_DQ6 */
+ 0x0000000b, /* EMC_DLL_XFORM_DQ7 */
0x100002a0, /* EMC_XM2CMDPADCTRL */
0x00000000, /* EMC_XM2CMDPADCTRL4 */
0x00111111, /* EMC_XM2CMDPADCTRL5 */
@@ -4891,7 +4891,7 @@ static struct tegra12_emc_table ardbeg_emc_table[] = {
0x00000000, /* EMC_XM2DQPADCTRL2 */
0x00000000, /* EMC_XM2DQPADCTRL3 */
0x77ffc085, /* EMC_XM2CLKPADCTRL */
- 0x00000404, /* EMC_XM2CLKPADCTRL2 */
+ 0x00000505, /* EMC_XM2CLKPADCTRL2 */
0x81f1f108, /* EMC_XM2COMPPADCTRL */
0x07070004, /* EMC_XM2VTTGENPADCTRL */
0x00000000, /* EMC_XM2VTTGENPADCTRL2 */
@@ -4905,8 +4905,8 @@ static struct tegra12_emc_table ardbeg_emc_table[] = {
0x00000000, /* EMC_FBIO_SPARE */
0x00020000, /* EMC_ZCAL_INTERVAL */
0x00000100, /* EMC_ZCAL_WAIT_CNT */
- 0x0127000e, /* EMC_MRS_WAIT_CNT */
- 0x0127000e, /* EMC_MRS_WAIT_CNT2 */
+ 0x00b0000e, /* EMC_MRS_WAIT_CNT */
+ 0x00b0000e, /* EMC_MRS_WAIT_CNT2 */
0x00000000, /* EMC_CTT */
0x00000003, /* EMC_CTT_DURATION */
0x000040a0, /* EMC_CFG_PIPE */
@@ -4928,7 +4928,7 @@ static struct tegra12_emc_table ardbeg_emc_table[] = {
0x00000007, /* MC_EMEM_ARB_TIMING_W2R */
0x07050202, /* MC_EMEM_ARB_DA_TURNS */
0x00130b0e, /* MC_EMEM_ARB_DA_COVERS */
- 0x73a91b0f, /* MC_EMEM_ARB_MISC0 */
+ 0x74891b0f, /* MC_EMEM_ARB_MISC0 */
0x001f0000, /* MC_EMEM_ARB_RING1_THROTTLE */
},
{
@@ -4975,16 +4975,16 @@ static struct tegra12_emc_table ardbeg_emc_table[] = {
0x00000000, /* EMC_AUTO_CAL_CONFIG2 */
0x00000000, /* EMC_AUTO_CAL_CONFIG3 */
0xa1430000, /* EMC_AUTO_CAL_CONFIG */
- 0x80000b61, /* Mode Register 0 */
- 0x80100002, /* Mode Register 1 */
- 0x80200010, /* Mode Register 2 */
+ 0x00000b61, /* Mode Register 0 */
+ 0x00100002, /* Mode Register 1 */
+ 0x00200010, /* Mode Register 2 */
0x00000000, /* Mode Register 4 */
},
{
- 0x18, /* V5.0.10 */
- "07_792000_05_V5.0.10_V0.8", /* DVFS table version */
+ 0x18, /* V5.0.12 */
+ "02_792000_04_V5.0.12_V0.9", /* DVFS table version */
792000, /* SDRAM frequency */
- 1000, /* min voltage */
+ 980, /* min voltage */
1100, /* gpu min voltage */
"pllm_ud", /* clock source id */
0x80000000, /* CLK_SOURCE_EMC */
@@ -4992,7 +4992,7 @@ static struct tegra12_emc_table ardbeg_emc_table[] = {
31, /* number of up_down_regs */
{
0x00000024, /* EMC_RC */
- 0x000000cd, /* EMC_RFC */
+ 0x00000114, /* EMC_RFC */
0x00000000, /* EMC_RFC_SLR */
0x00000019, /* EMC_RAS */
0x0000000a, /* EMC_RP */
@@ -5020,8 +5020,8 @@ static struct tegra12_emc_table ardbeg_emc_table[] = {
0x00000000, /* EMC_CDB_CNTL_3 */
0x00000001, /* EMC_QRST */
0x00000014, /* EMC_QSAFE */
- 0x00000017, /* EMC_RDV */
- 0x00000019, /* EMC_RDV_MASK */
+ 0x00000018, /* EMC_RDV */
+ 0x0000001a, /* EMC_RDV_MASK */
0x000017e2, /* EMC_REFRESH */
0x00000000, /* EMC_BURST_REFRESH_NUM */
0x000005f8, /* EMC_PRE_REFRESH_REQ_CNT */
@@ -5029,9 +5029,9 @@ static struct tegra12_emc_table ardbeg_emc_table[] = {
0x00000011, /* EMC_PDEX2RD */
0x00000001, /* EMC_PCHG2PDEN */
0x00000000, /* EMC_ACT2PDEN */
- 0x000000c7, /* EMC_AR2PDEN */
+ 0x0000010d, /* EMC_AR2PDEN */
0x00000018, /* EMC_RW2PDEN */
- 0x000000d7, /* EMC_TXSR */
+ 0x0000011e, /* EMC_TXSR */
0x00000200, /* EMC_TXSRDLL */
0x00000005, /* EMC_TCKE */
0x00000006, /* EMC_TCKESR */
@@ -5047,22 +5047,22 @@ static struct tegra12_emc_table ardbeg_emc_table[] = {
0x1049b098, /* EMC_FBIO_CFG5 */
0xe00700b1, /* EMC_CFG_DIG_DLL */
0x00008000, /* EMC_CFG_DIG_DLL_PERIOD */
- 0x00000006, /* EMC_DLL_XFORM_DQS0 */
- 0x00000006, /* EMC_DLL_XFORM_DQS1 */
- 0x00000006, /* EMC_DLL_XFORM_DQS2 */
- 0x00000006, /* EMC_DLL_XFORM_DQS3 */
- 0x00000006, /* EMC_DLL_XFORM_DQS4 */
- 0x00000006, /* EMC_DLL_XFORM_DQS5 */
- 0x00000006, /* EMC_DLL_XFORM_DQS6 */
- 0x00000006, /* EMC_DLL_XFORM_DQS7 */
- 0x00000006, /* EMC_DLL_XFORM_DQS8 */
- 0x00000006, /* EMC_DLL_XFORM_DQS9 */
- 0x00000006, /* EMC_DLL_XFORM_DQS10 */
- 0x00000006, /* EMC_DLL_XFORM_DQS11 */
- 0x00000006, /* EMC_DLL_XFORM_DQS12 */
- 0x00000006, /* EMC_DLL_XFORM_DQS13 */
- 0x00000006, /* EMC_DLL_XFORM_DQS14 */
- 0x00000006, /* EMC_DLL_XFORM_DQS15 */
+ 0x00000004, /* EMC_DLL_XFORM_DQS0 */
+ 0x00000004, /* EMC_DLL_XFORM_DQS1 */
+ 0x00000004, /* EMC_DLL_XFORM_DQS2 */
+ 0x00000004, /* EMC_DLL_XFORM_DQS3 */
+ 0x00000004, /* EMC_DLL_XFORM_DQS4 */
+ 0x00000004, /* EMC_DLL_XFORM_DQS5 */
+ 0x00000004, /* EMC_DLL_XFORM_DQS6 */
+ 0x00000004, /* EMC_DLL_XFORM_DQS7 */
+ 0x00000004, /* EMC_DLL_XFORM_DQS8 */
+ 0x00000004, /* EMC_DLL_XFORM_DQS9 */
+ 0x00000004, /* EMC_DLL_XFORM_DQS10 */
+ 0x00000004, /* EMC_DLL_XFORM_DQS11 */
+ 0x00000004, /* EMC_DLL_XFORM_DQS12 */
+ 0x00000004, /* EMC_DLL_XFORM_DQS13 */
+ 0x00000004, /* EMC_DLL_XFORM_DQS14 */
+ 0x00000004, /* EMC_DLL_XFORM_DQS15 */
0x00000000, /* EMC_DLL_XFORM_QUSE0 */
0x00000000, /* EMC_DLL_XFORM_QUSE1 */
0x00000000, /* EMC_DLL_XFORM_QUSE2 */
@@ -5071,11 +5071,11 @@ static struct tegra12_emc_table ardbeg_emc_table[] = {
0x00000000, /* EMC_DLL_XFORM_QUSE5 */
0x00000000, /* EMC_DLL_XFORM_QUSE6 */
0x00000000, /* EMC_DLL_XFORM_QUSE7 */
- 0x00030000, /* EMC_DLL_XFORM_ADDR0 */
- 0x00030000, /* EMC_DLL_XFORM_ADDR1 */
+ 0x00034000, /* EMC_DLL_XFORM_ADDR0 */
+ 0x00034000, /* EMC_DLL_XFORM_ADDR1 */
0x00000000, /* EMC_DLL_XFORM_ADDR2 */
- 0x00030000, /* EMC_DLL_XFORM_ADDR3 */
- 0x00030000, /* EMC_DLL_XFORM_ADDR4 */
+ 0x00034000, /* EMC_DLL_XFORM_ADDR3 */
+ 0x00034000, /* EMC_DLL_XFORM_ADDR4 */
0x00000000, /* EMC_DLL_XFORM_ADDR5 */
0x00000000, /* EMC_DLL_XFORM_QUSE8 */
0x00000000, /* EMC_DLL_XFORM_QUSE9 */
@@ -5101,14 +5101,14 @@ static struct tegra12_emc_table ardbeg_emc_table[] = {
0x00000000, /* EMC_DLI_TRIM_TXDQS13 */
0x00000000, /* EMC_DLI_TRIM_TXDQS14 */
0x00000000, /* EMC_DLI_TRIM_TXDQS15 */
- 0x00000009, /* EMC_DLL_XFORM_DQ0 */
- 0x00000009, /* EMC_DLL_XFORM_DQ1 */
- 0x00000009, /* EMC_DLL_XFORM_DQ2 */
- 0x00000009, /* EMC_DLL_XFORM_DQ3 */
- 0x00000009, /* EMC_DLL_XFORM_DQ4 */
- 0x00000009, /* EMC_DLL_XFORM_DQ5 */
- 0x00000009, /* EMC_DLL_XFORM_DQ6 */
- 0x00000009, /* EMC_DLL_XFORM_DQ7 */
+ 0x0000000b, /* EMC_DLL_XFORM_DQ0 */
+ 0x0000000b, /* EMC_DLL_XFORM_DQ1 */
+ 0x0000000b, /* EMC_DLL_XFORM_DQ2 */
+ 0x0000000b, /* EMC_DLL_XFORM_DQ3 */
+ 0x0000000b, /* EMC_DLL_XFORM_DQ4 */
+ 0x0000000b, /* EMC_DLL_XFORM_DQ5 */
+ 0x0000000b, /* EMC_DLL_XFORM_DQ6 */
+ 0x0000000b, /* EMC_DLL_XFORM_DQ7 */
0x100002a0, /* EMC_XM2CMDPADCTRL */
0x00000000, /* EMC_XM2CMDPADCTRL4 */
0x00111111, /* EMC_XM2CMDPADCTRL5 */
@@ -5121,20 +5121,20 @@ static struct tegra12_emc_table ardbeg_emc_table[] = {
0x07070004, /* EMC_XM2VTTGENPADCTRL */
0x00000000, /* EMC_XM2VTTGENPADCTRL2 */
0x016eeeee, /* EMC_XM2VTTGENPADCTRL3 */
- 0x61861820, /* EMC_XM2DQSPADCTRL3 */
+ 0x69a69a20, /* EMC_XM2DQSPADCTRL3 */
0x00514514, /* EMC_XM2DQSPADCTRL4 */
0x00514514, /* EMC_XM2DQSPADCTRL5 */
- 0x61861800, /* EMC_XM2DQSPADCTRL6 */
+ 0x69a69a00, /* EMC_XM2DQSPADCTRL6 */
0x0606003f, /* EMC_DSR_VTTGEN_DRV */
0x00000000, /* EMC_TXDSRVTTGEN */
0x00000000, /* EMC_FBIO_SPARE */
0x00020000, /* EMC_ZCAL_INTERVAL */
0x00000100, /* EMC_ZCAL_WAIT_CNT */
- 0x00f7000e, /* EMC_MRS_WAIT_CNT */
- 0x00f7000e, /* EMC_MRS_WAIT_CNT2 */
+ 0x006f000e, /* EMC_MRS_WAIT_CNT */
+ 0x006f000e, /* EMC_MRS_WAIT_CNT2 */
0x00000000, /* EMC_CTT */
0x00000004, /* EMC_CTT_DURATION */
- 0x000040a0, /* EMC_CFG_PIPE */
+ 0x00004080, /* EMC_CFG_PIPE */
0x80003012, /* EMC_DYN_SELF_REF_CONTROL */
0x0000000f, /* EMC_QPOP */
0x0e00000b, /* MC_EMEM_ARB_CFG */
@@ -5153,7 +5153,7 @@ static struct tegra12_emc_table ardbeg_emc_table[] = {
0x00000008, /* MC_EMEM_ARB_TIMING_W2R */
0x08060202, /* MC_EMEM_ARB_DA_TURNS */
0x00170e13, /* MC_EMEM_ARB_DA_COVERS */
- 0x736c2414, /* MC_EMEM_ARB_MISC0 */
+ 0x746c2414, /* MC_EMEM_ARB_MISC0 */
0x001f0000, /* MC_EMEM_ARB_RING1_THROTTLE */
},
{
@@ -5200,234 +5200,9 @@ static struct tegra12_emc_table ardbeg_emc_table[] = {
0x00000000, /* EMC_AUTO_CAL_CONFIG2 */
0x00000000, /* EMC_AUTO_CAL_CONFIG3 */
0xa1430000, /* EMC_AUTO_CAL_CONFIG */
- 0x80000d71, /* Mode Register 0 */
- 0x80100002, /* Mode Register 1 */
- 0x80200018, /* Mode Register 2 */
- 0x00000000, /* Mode Register 4 */
- },
- {
- 0x18, /* V5.0.10 */
- "07_924000_06_V5.0.10_V0.8", /* DVFS table version */
- 924000, /* SDRAM frequency */
- 1010, /* min voltage */
- 1100, /* gpu min voltage */
- "pllm_ud", /* clock source id */
- 0x80000000, /* CLK_SOURCE_EMC */
- 164, /* number of burst_regs */
- 31, /* number of up_down_regs */
- {
- 0x0000002b, /* EMC_RC */
- 0x000000f0, /* EMC_RFC */
- 0x00000000, /* EMC_RFC_SLR */
- 0x0000001e, /* EMC_RAS */
- 0x0000000b, /* EMC_RP */
- 0x0000000a, /* EMC_R2W */
- 0x0000000f, /* EMC_W2R */
- 0x00000005, /* EMC_R2P */
- 0x00000016, /* EMC_W2P */
- 0x0000000b, /* EMC_RD_RCD */
- 0x0000000b, /* EMC_WR_RCD */
- 0x00000004, /* EMC_RRD */
- 0x00000002, /* EMC_REXT */
- 0x00000000, /* EMC_WEXT */
- 0x00000007, /* EMC_WDV */
- 0x00000007, /* EMC_WDV_MASK */
- 0x0000000d, /* EMC_QUSE */
- 0x00000002, /* EMC_QUSE_WIDTH */
- 0x00000000, /* EMC_IBDLY */
- 0x00000002, /* EMC_EINPUT */
- 0x0000000f, /* EMC_EINPUT_DURATION */
- 0x000a0000, /* EMC_PUTERM_EXTRA */
- 0x00000004, /* EMC_PUTERM_WIDTH */
- 0x00000000, /* EMC_PUTERM_ADJ */
- 0x00000000, /* EMC_CDB_CNTL_1 */
- 0x00000000, /* EMC_CDB_CNTL_2 */
- 0x00000000, /* EMC_CDB_CNTL_3 */
- 0x00000001, /* EMC_QRST */
- 0x00000016, /* EMC_QSAFE */
- 0x0000001a, /* EMC_RDV */
- 0x0000001c, /* EMC_RDV_MASK */
- 0x00001be7, /* EMC_REFRESH */
- 0x00000000, /* EMC_BURST_REFRESH_NUM */
- 0x000006f9, /* EMC_PRE_REFRESH_REQ_CNT */
- 0x00000004, /* EMC_PDEX2WR */
- 0x00000015, /* EMC_PDEX2RD */
- 0x00000001, /* EMC_PCHG2PDEN */
- 0x00000000, /* EMC_ACT2PDEN */
- 0x000000e7, /* EMC_AR2PDEN */
- 0x0000001b, /* EMC_RW2PDEN */
- 0x000000fb, /* EMC_TXSR */
- 0x00000200, /* EMC_TXSRDLL */
- 0x00000006, /* EMC_TCKE */
- 0x00000007, /* EMC_TCKESR */
- 0x00000006, /* EMC_TPD */
- 0x00000022, /* EMC_TFAW */
- 0x00000000, /* EMC_TRPAB */
- 0x0000000a, /* EMC_TCLKSTABLE */
- 0x0000000a, /* EMC_TCLKSTOP */
- 0x00001c28, /* EMC_TREFBW */
- 0x00000000, /* EMC_FBIO_CFG6 */
- 0x00000000, /* EMC_ODT_WRITE */
- 0x00000000, /* EMC_ODT_READ */
- 0x1049b898, /* EMC_FBIO_CFG5 */
- 0xe00400b1, /* EMC_CFG_DIG_DLL */
- 0x00008000, /* EMC_CFG_DIG_DLL_PERIOD */
- 0x00000003, /* EMC_DLL_XFORM_DQS0 */
- 0x00000003, /* EMC_DLL_XFORM_DQS1 */
- 0x00000003, /* EMC_DLL_XFORM_DQS2 */
- 0x00000003, /* EMC_DLL_XFORM_DQS3 */
- 0x00000003, /* EMC_DLL_XFORM_DQS4 */
- 0x00000003, /* EMC_DLL_XFORM_DQS5 */
- 0x00000003, /* EMC_DLL_XFORM_DQS6 */
- 0x00000003, /* EMC_DLL_XFORM_DQS7 */
- 0x00000003, /* EMC_DLL_XFORM_DQS8 */
- 0x00000003, /* EMC_DLL_XFORM_DQS9 */
- 0x00000003, /* EMC_DLL_XFORM_DQS10 */
- 0x00000003, /* EMC_DLL_XFORM_DQS11 */
- 0x00000003, /* EMC_DLL_XFORM_DQS12 */
- 0x00000003, /* EMC_DLL_XFORM_DQS13 */
- 0x00000003, /* EMC_DLL_XFORM_DQS14 */
- 0x00000003, /* EMC_DLL_XFORM_DQS15 */
- 0x00000000, /* EMC_DLL_XFORM_QUSE0 */
- 0x00000000, /* EMC_DLL_XFORM_QUSE1 */
- 0x00000000, /* EMC_DLL_XFORM_QUSE2 */
- 0x00000000, /* EMC_DLL_XFORM_QUSE3 */
- 0x00000000, /* EMC_DLL_XFORM_QUSE4 */
- 0x00000000, /* EMC_DLL_XFORM_QUSE5 */
- 0x00000000, /* EMC_DLL_XFORM_QUSE6 */
- 0x00000000, /* EMC_DLL_XFORM_QUSE7 */
- 0x00030000, /* EMC_DLL_XFORM_ADDR0 */
- 0x00030000, /* EMC_DLL_XFORM_ADDR1 */
- 0x00000000, /* EMC_DLL_XFORM_ADDR2 */
- 0x00030000, /* EMC_DLL_XFORM_ADDR3 */
- 0x00030000, /* EMC_DLL_XFORM_ADDR4 */
- 0x00000000, /* EMC_DLL_XFORM_ADDR5 */
- 0x00000000, /* EMC_DLL_XFORM_QUSE8 */
- 0x00000000, /* EMC_DLL_XFORM_QUSE9 */
- 0x00000000, /* EMC_DLL_XFORM_QUSE10 */
- 0x00000000, /* EMC_DLL_XFORM_QUSE11 */
- 0x00000000, /* EMC_DLL_XFORM_QUSE12 */
- 0x00000000, /* EMC_DLL_XFORM_QUSE13 */
- 0x00000000, /* EMC_DLL_XFORM_QUSE14 */
- 0x00000000, /* EMC_DLL_XFORM_QUSE15 */
- 0x00000000, /* EMC_DLI_TRIM_TXDQS0 */
- 0x00000000, /* EMC_DLI_TRIM_TXDQS1 */
- 0x00000000, /* EMC_DLI_TRIM_TXDQS2 */
- 0x00000000, /* EMC_DLI_TRIM_TXDQS3 */
- 0x00000000, /* EMC_DLI_TRIM_TXDQS4 */
- 0x00000000, /* EMC_DLI_TRIM_TXDQS5 */
- 0x00000000, /* EMC_DLI_TRIM_TXDQS6 */
- 0x00000000, /* EMC_DLI_TRIM_TXDQS7 */
- 0x00000000, /* EMC_DLI_TRIM_TXDQS8 */
- 0x00000000, /* EMC_DLI_TRIM_TXDQS9 */
- 0x00000000, /* EMC_DLI_TRIM_TXDQS10 */
- 0x00000000, /* EMC_DLI_TRIM_TXDQS11 */
- 0x00000000, /* EMC_DLI_TRIM_TXDQS12 */
- 0x00000000, /* EMC_DLI_TRIM_TXDQS13 */
- 0x00000000, /* EMC_DLI_TRIM_TXDQS14 */
- 0x00000000, /* EMC_DLI_TRIM_TXDQS15 */
- 0x0000000a, /* EMC_DLL_XFORM_DQ0 */
- 0x0000000a, /* EMC_DLL_XFORM_DQ1 */
- 0x0000000a, /* EMC_DLL_XFORM_DQ2 */
- 0x0000000a, /* EMC_DLL_XFORM_DQ3 */
- 0x0000000a, /* EMC_DLL_XFORM_DQ4 */
- 0x0000000a, /* EMC_DLL_XFORM_DQ5 */
- 0x0000000a, /* EMC_DLL_XFORM_DQ6 */
- 0x0000000a, /* EMC_DLL_XFORM_DQ7 */
- 0x100002a0, /* EMC_XM2CMDPADCTRL */
- 0x00000000, /* EMC_XM2CMDPADCTRL4 */
- 0x00111111, /* EMC_XM2CMDPADCTRL5 */
- 0x0120113d, /* EMC_XM2DQSPADCTRL2 */
- 0x00000000, /* EMC_XM2DQPADCTRL2 */
- 0x00000000, /* EMC_XM2DQPADCTRL3 */
- 0x77ffc085, /* EMC_XM2CLKPADCTRL */
- 0x00000505, /* EMC_XM2CLKPADCTRL2 */
- 0x81f1f108, /* EMC_XM2COMPPADCTRL */
- 0x07070004, /* EMC_XM2VTTGENPADCTRL */
- 0x00000000, /* EMC_XM2VTTGENPADCTRL2 */
- 0x016eeeee, /* EMC_XM2VTTGENPADCTRL3 */
- 0x5d75d720, /* EMC_XM2DQSPADCTRL3 */
- 0x00514514, /* EMC_XM2DQSPADCTRL4 */
- 0x00514514, /* EMC_XM2DQSPADCTRL5 */
- 0x5d75d700, /* EMC_XM2DQSPADCTRL6 */
- 0x0606003f, /* EMC_DSR_VTTGEN_DRV */
- 0x00000000, /* EMC_TXDSRVTTGEN */
- 0x00000000, /* EMC_FBIO_SPARE */
- 0x00020000, /* EMC_ZCAL_INTERVAL */
- 0x00000128, /* EMC_ZCAL_WAIT_CNT */
- 0x00cd000e, /* EMC_MRS_WAIT_CNT */
- 0x00cd000e, /* EMC_MRS_WAIT_CNT2 */
- 0x00000000, /* EMC_CTT */
- 0x00000004, /* EMC_CTT_DURATION */
- 0x00004080, /* EMC_CFG_PIPE */
- 0x800037ea, /* EMC_DYN_SELF_REF_CONTROL */
- 0x00000011, /* EMC_QPOP */
- 0x0e00000d, /* MC_EMEM_ARB_CFG */
- 0x80000040, /* MC_EMEM_ARB_OUTSTANDING_REQ */
- 0x00000005, /* MC_EMEM_ARB_TIMING_RCD */
- 0x00000006, /* MC_EMEM_ARB_TIMING_RP */
- 0x00000016, /* MC_EMEM_ARB_TIMING_RC */
- 0x0000000e, /* MC_EMEM_ARB_TIMING_RAS */
- 0x00000011, /* MC_EMEM_ARB_TIMING_FAW */
- 0x00000002, /* MC_EMEM_ARB_TIMING_RRD */
- 0x00000004, /* MC_EMEM_ARB_TIMING_RAP2PRE */
- 0x0000000e, /* MC_EMEM_ARB_TIMING_WAP2PRE */
- 0x00000002, /* MC_EMEM_ARB_TIMING_R2R */
- 0x00000002, /* MC_EMEM_ARB_TIMING_W2W */
- 0x00000007, /* MC_EMEM_ARB_TIMING_R2W */
- 0x00000009, /* MC_EMEM_ARB_TIMING_W2R */
- 0x09070202, /* MC_EMEM_ARB_DA_TURNS */
- 0x001a1016, /* MC_EMEM_ARB_DA_COVERS */
- 0x734e2a17, /* MC_EMEM_ARB_MISC0 */
- 0x001f0000, /* MC_EMEM_ARB_RING1_THROTTLE */
- },
- {
- 0x00000017, /* MC_MLL_MPCORER_PTSA_RATE */
- 0x000001bb, /* MC_PTSA_GRANT_DECREMENT */
- 0x006e0038, /* MC_LATENCY_ALLOWANCE_XUSB_0 */
- 0x006e0038, /* MC_LATENCY_ALLOWANCE_XUSB_1 */
- 0x006e003c, /* MC_LATENCY_ALLOWANCE_TSEC_0 */
- 0x006e0090, /* MC_LATENCY_ALLOWANCE_SDMMCA_0 */
- 0x006e0041, /* MC_LATENCY_ALLOWANCE_SDMMCAA_0 */
- 0x006e0090, /* MC_LATENCY_ALLOWANCE_SDMMC_0 */
- 0x006e0041, /* MC_LATENCY_ALLOWANCE_SDMMCAB_0 */
- 0x00270049, /* MC_LATENCY_ALLOWANCE_PPCS_0 */
- 0x006e0080, /* MC_LATENCY_ALLOWANCE_PPCS_1 */
- 0x006e0004, /* MC_LATENCY_ALLOWANCE_MPCORE_0 */
- 0x006e0004, /* MC_LATENCY_ALLOWANCE_MPCORELP_0 */
- 0x00080016, /* MC_LATENCY_ALLOWANCE_HC_0 */
- 0x0000006e, /* MC_LATENCY_ALLOWANCE_HC_1 */
- 0x006e0004, /* MC_LATENCY_ALLOWANCE_AVPC_0 */
- 0x006e0019, /* MC_LATENCY_ALLOWANCE_GPU_0 */
- 0x006e0018, /* MC_LATENCY_ALLOWANCE_MSENC_0 */
- 0x006e0024, /* MC_LATENCY_ALLOWANCE_HDA_0 */
- 0x006e001b, /* MC_LATENCY_ALLOWANCE_VIC_0 */
- 0x0000006e, /* MC_LATENCY_ALLOWANCE_VI2_0 */
- 0x00000036, /* MC_LATENCY_ALLOWANCE_ISP2_0 */
- 0x006e006e, /* MC_LATENCY_ALLOWANCE_ISP2_1 */
- 0x00000036, /* MC_LATENCY_ALLOWANCE_ISP2B_0 */
- 0x006e006e, /* MC_LATENCY_ALLOWANCE_ISP2B_1 */
- 0x00d400ff, /* MC_LATENCY_ALLOWANCE_VDE_0 */
- 0x00510029, /* MC_LATENCY_ALLOWANCE_VDE_1 */
- 0x006e006e, /* MC_LATENCY_ALLOWANCE_VDE_2 */
- 0x006e006e, /* MC_LATENCY_ALLOWANCE_VDE_3 */
- 0x006e0065, /* MC_LATENCY_ALLOWANCE_SATA_0 */
- 0x006e001c, /* MC_LATENCY_ALLOWANCE_AFI_0 */
- },
- 0x0000004c, /* EMC_ZCAL_WAIT_CNT after clock change */
- 0x001fffff, /* EMC_AUTO_CAL_INTERVAL */
- 0x00000802, /* EMC_CTT_TERM_CTRL */
- 0x73300000, /* EMC_CFG */
- 0x0000089d, /* EMC_CFG_2 */
- 0x00040000, /* EMC_SEL_DPD_CTRL */
- 0xe0040069, /* EMC_CFG_DIG_DLL */
- 0x00000000, /* EMC_BGBIAS_CTL0 */
- 0x00000000, /* EMC_AUTO_CAL_CONFIG2 */
- 0x00000000, /* EMC_AUTO_CAL_CONFIG3 */
- 0xa1430000, /* EMC_AUTO_CAL_CONFIG */
- 0x80000f15, /* Mode Register 0 */
- 0x80100002, /* Mode Register 1 */
- 0x80200020, /* Mode Register 2 */
+ 0x00000d71, /* Mode Register 0 */
+ 0x00100002, /* Mode Register 1 */
+ 0x00200018, /* Mode Register 2 */
0x00000000, /* Mode Register 4 */
},
};
generated by cgit v1.2.3 (git 2.0.4) at 2025-04-12 00:59:37 +0000