diff options
| author | Shreshtha Sahu <ssahu@nvidia.com> | 2014-05-21 12:09:50 +0530 |
|---|---|---|
| committer | Mandar Padmawar <mpadmawar@nvidia.com> | 2014-06-16 04:46:53 -0700 |
| commit | 8ec9033e13c639419d351ad9d1b6ac92f3da4cb6 (patch) | |
| tree | 90e96b0fbd739dc9d9c084e75ff43e3d326ed23b /arch/arm/mach-tegra/board-ardbeg-sdhci.c | |
| parent | 9fdbb99f956c39e40f28fadb3e89b7bd3eee7df9 (diff) | |
ARM: tegra: sdhci: set max clk to 200MHz for SDMMC3
This patch sets max clk limit to 200MHz for SDMMC3 for PM375.
Requesting 208MHz results in getting 204MHz from PLL_P and CRC
errors are seen.
Bug 1505798
Change-Id: I14825335fa5895ef2dde905f1e3cd568d2dafa62
Signed-off-by: Shreshtha Sahu <ssahu@nvidia.com>
Reviewed-on: http://git-master/r/412542
(cherry picked from commit fbcb0018d3622dedeb4c9413b9b774c4c9d49d36)
Signed-off-by: Shreshtha Sahu <ssahu@nvidia.com>
Reviewed-on: http://git-master/r/422034
Reviewed-by: Mandar Padmawar <mpadmawar@nvidia.com>
Tested-by: Mandar Padmawar <mpadmawar@nvidia.com>
Diffstat (limited to 'arch/arm/mach-tegra/board-ardbeg-sdhci.c')
| -rw-r--r-- | arch/arm/mach-tegra/board-ardbeg-sdhci.c | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/arch/arm/mach-tegra/board-ardbeg-sdhci.c b/arch/arm/mach-tegra/board-ardbeg-sdhci.c index 5bf0117454e0..e067812afd31 100644 --- a/arch/arm/mach-tegra/board-ardbeg-sdhci.c +++ b/arch/arm/mach-tegra/board-ardbeg-sdhci.c @@ -495,6 +495,14 @@ int __init ardbeg_sdhci_init(void) board_info.board_id == BOARD_PM359) tegra_sdhci_platform_data0.disable_clock_gate = 1; + /* + * FIXME: Set max clk limit to 200MHz for SDMMC3 for PM375. + * Requesting 208MHz results in getting 204MHz from PLL_P + * and CRC errors are seen with same. + */ + if (board_info.board_id == BOARD_PM375) + tegra_sdhci_platform_data2.max_clk_limit = 200000000; + speedo = tegra_fuse_readl(FUSE_SOC_SPEEDO_0); tegra_sdhci_platform_data0.cpu_speedo = speedo; tegra_sdhci_platform_data2.cpu_speedo = speedo; |