diff options
| author | Naveen Kumar Arepalli <naveenk@nvidia.com> | 2013-10-16 14:22:15 +0530 |
|---|---|---|
| committer | Naveen Kumar Arepalli <naveenk@nvidia.com> | 2013-10-16 23:24:36 -0700 |
| commit | f9061c3e5e12cbfe33d351e730c65956b0b625ab (patch) | |
| tree | 0d81a495fc045d85e6a6634777aa1764b002afc3 /arch/arm/mach-tegra/board-ardbeg-sdhci.c | |
| parent | ce6802b982e3fd2b8259eea361868156ed376b37 (diff) | |
ARM: tegra: t124: Set DDR mode's TRIM_VAL to 0
-For eMMC change DDR mode's TRIM_VAL from 4 to 0
as per char team data.
Bug 1333552
Change-Id: Ia5d877be07de80dcfe55ca8f78528e8a6a6fa12c
Signed-off-by: Naveen Kumar Arepalli <naveenk@nvidia.com>
Reviewed-on: http://git-master/r/299864
Reviewed-by: Venu Byravarasu <vbyravarasu@nvidia.com>
Diffstat (limited to 'arch/arm/mach-tegra/board-ardbeg-sdhci.c')
| -rw-r--r-- | arch/arm/mach-tegra/board-ardbeg-sdhci.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/arm/mach-tegra/board-ardbeg-sdhci.c b/arch/arm/mach-tegra/board-ardbeg-sdhci.c index c7c6314e4f31..f8299479f503 100644 --- a/arch/arm/mach-tegra/board-ardbeg-sdhci.c +++ b/arch/arm/mach-tegra/board-ardbeg-sdhci.c @@ -193,7 +193,7 @@ static struct tegra_sdhci_platform_data tegra_sdhci_platform_data3 = { .is_8bit = 1, .tap_delay = 0x4, .trim_delay = 0x4, - .ddr_trim_delay = 0x4, + .ddr_trim_delay = 0x0, .mmc_data = { .built_in = 1, .ocr_mask = MMC_OCR_1V8_MASK, |