arm: tegra: cardhu: Uart platform data for hsuart driver

Adding uart platform data for the hsuart driver. Passing the
clock information through the platform data.

bug 837140
bug 836059

Change-Id: I321cd904ea072b0bc931016d46a4fa8462c28c8d
Reviewed-on: http://git-master/r/37636
Reviewed-by: Niket Sirsi <nsirsi@nvidia.com>
Tested-by: Niket Sirsi <nsirsi@nvidia.com>

1 files changed, 36 insertions, 1 deletions

diff --git a/arch/arm/mach-tegra/board-cardhu.c b/arch/arm/mach-tegra/board-cardhu.c
index 3eb75f0d30ee..762fa264b416 100644
--- a/arch/arm/mach-tegra/board-cardhu.c
+++ b/arch/arm/mach-tegra/board-cardhu.c
@@ -35,6 +35,7 @@
 #include <linux/platform_data/tegra_usb.h>
 #include <linux/usb/android_composite.h>
 #include <linux/spi/spi.h>
+#include <linux/tegra_uart.h>
 #include <mach/clk.h>
 #include <mach/iomap.h>
 #include <mach/irqs.h>
@@ -430,11 +431,38 @@ static struct platform_device *cardhu_uart_devices[] __initdata = {
 	&tegra_uartd_device,
 	&tegra_uarte_device,
 };
+struct uart_clk_parent uart_parent_clk[] = {
+	[0] = {.name = "pll_p"},
+	[1] = {.name = "pll_m"},
+	[2] = {.name = "clk_m"},
+};
+
 static struct clk *debug_uart_clk;
+static struct tegra_uart_platform_data cardhu_uart_pdata;
 
 static void __init uart_debug_init(void)
 {
 	struct board_info board_info;
+	int i;
+	struct clk *c;
+
+	for (i = 0; i < ARRAY_SIZE(uart_parent_clk); ++i) {
+		c = tegra_get_clock_by_name(uart_parent_clk[i].name);
+		if (IS_ERR_OR_NULL(c)) {
+			pr_err("Not able to get the clock for %s\n",
+						uart_parent_clk[i].name);
+			continue;
+		}
+		uart_parent_clk[i].parent_clk = c;
+		uart_parent_clk[i].fixed_clk_rate = clk_get_rate(c);
+	}
+	cardhu_uart_pdata.parent_clk_list = uart_parent_clk;
+	cardhu_uart_pdata.parent_clk_count = ARRAY_SIZE(uart_parent_clk);
+	tegra_uarta_device.dev.platform_data = &cardhu_uart_pdata;
+	tegra_uartb_device.dev.platform_data = &cardhu_uart_pdata;
+	tegra_uartc_device.dev.platform_data = &cardhu_uart_pdata;
+	tegra_uartd_device.dev.platform_data = &cardhu_uart_pdata;
+	tegra_uarte_device.dev.platform_data = &cardhu_uart_pdata;
 
 	tegra_get_board_info(&board_info);
 	if (board_info.sku & SKU_SLT_ULPI_SUPPORT) {
@@ -459,6 +487,7 @@ static void __init uart_debug_init(void)
 
 static void __init cardhu_uart_init(void)
 {
+	struct clk *c;
 	/* Register low speed only if it is selected */
 	if (!is_tegra_debug_uartport_hs()) {
 		uart_debug_init();
@@ -466,8 +495,14 @@ static void __init cardhu_uart_init(void)
 		if (!IS_ERR_OR_NULL(debug_uart_clk)) {
 			pr_info("The debug console clock name is %s\n",
 						debug_uart_clk->name);
+			c = tegra_get_clock_by_name("pll_p");
+			if (IS_ERR_OR_NULL(c))
+				pr_err("Not getting the parent clock pll_p\n");
+			else
+				clk_set_parent(debug_uart_clk, c);
+
 			clk_enable(debug_uart_clk);
-			clk_set_rate(debug_uart_clk, 408000000);
+			clk_set_rate(debug_uart_clk, clk_get_rate(c));
 		} else {
 			pr_err("Not getting the clock %s for debug console\n",
 					debug_uart_clk->name);