diff options
| author | Tom Cherry <tcherry@nvidia.com> | 2011-11-22 11:19:12 -0800 |
|---|---|---|
| committer | Simone Willett <swillett@nvidia.com> | 2012-02-28 20:44:28 -0800 |
| commit | 1805544f13b3168194110c4c270b0d49442d862d (patch) | |
| tree | a20be2b2d427927129b6ebd92dfb143a3eea35d5 /arch/arm/mach-tegra/board-enterprise-memory.c | |
| parent | fed567e6f3f446c30d824dc7acfa4dde17e8ddc4 (diff) | |
ARM: tegra: enterprise: Updating EMC table
Bug 896654
Bug 905859
Reviewed-on: http://git-master/r/66191
(cherry picked from commit 196a42e94f1a8a33466a63f19f81d48aed442ac5)
Change-Id: Ic8417ee4370b827e69af23b407cd1bf88b836523
Signed-off-by: Tom Cherry <tcherry@nvidia.com>
Reviewed-on: http://git-master/r/86202
Reviewed-by: Mayuresh Kulkarni <mkulkarni@nvidia.com>
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
Tested-by: Bharat Nihalani <bnihalani@nvidia.com>
Diffstat (limited to 'arch/arm/mach-tegra/board-enterprise-memory.c')
| -rw-r--r-- | arch/arm/mach-tegra/board-enterprise-memory.c | 31 |
1 files changed, 18 insertions, 13 deletions
diff --git a/arch/arm/mach-tegra/board-enterprise-memory.c b/arch/arm/mach-tegra/board-enterprise-memory.c index 3212894cb049..1f09dfc4eec4 100644 --- a/arch/arm/mach-tegra/board-enterprise-memory.c +++ b/arch/arm/mach-tegra/board-enterprise-memory.c @@ -25,7 +25,7 @@ static const struct tegra_emc_table enterprise_emc_tables_h5tc2g[] = { { - 0x31, /* Rev 3.1 */ + 0x32, /* Rev 3.2 */ 25500, /* SDRAM frequency */ { 0x00000001, /* EMC_RC */ @@ -68,7 +68,7 @@ static const struct tegra_emc_table enterprise_emc_tables_h5tc2g[] = { 0x00000000, /* EMC_ODT_WRITE */ 0x00000000, /* EMC_ODT_READ */ 0x00004282, /* EMC_FBIO_CFG5 */ - 0x00780084, /* EMC_CFG_DIG_DLL */ + 0x007800a4, /* EMC_CFG_DIG_DLL */ 0x00008000, /* EMC_CFG_DIG_DLL_PERIOD */ 0x00090000, /* EMC_DLL_XFORM_DQS0 */ 0x00090000, /* EMC_DLL_XFORM_DQS1 */ @@ -116,7 +116,7 @@ static const struct tegra_emc_table enterprise_emc_tables_h5tc2g[] = { 0x00000000, /* EMC_CTT_DURATION */ 0x800001c2, /* EMC_DYN_SELF_REF_CONTROL */ 0x00020001, /* MC_EMEM_ARB_CFG */ - 0x80000008, /* MC_EMEM_ARB_OUTSTANDING_REQ */ + 0xc0000008, /* MC_EMEM_ARB_OUTSTANDING_REQ */ 0x00000001, /* MC_EMEM_ARB_TIMING_RCD */ 0x00000001, /* MC_EMEM_ARB_TIMING_RP */ 0x00000002, /* MC_EMEM_ARB_TIMING_RC */ @@ -142,9 +142,10 @@ static const struct tegra_emc_table enterprise_emc_tables_h5tc2g[] = { 0x00000000, /* Mode Register 0 */ 0x00010022, /* Mode Register 1 */ 0x00020001, /* Mode Register 2 */ + 0x00000001, /* EMC_CFG.DYN_SELF_REF */ }, { - 0x31, /* Rev 3.1 */ + 0x32, /* Rev 3.2 */ 51000, /* SDRAM frequency */ { 0x00000003, /* EMC_RC */ @@ -187,7 +188,7 @@ static const struct tegra_emc_table enterprise_emc_tables_h5tc2g[] = { 0x00000000, /* EMC_ODT_WRITE */ 0x00000000, /* EMC_ODT_READ */ 0x00004282, /* EMC_FBIO_CFG5 */ - 0x00780084, /* EMC_CFG_DIG_DLL */ + 0x007800a4, /* EMC_CFG_DIG_DLL */ 0x00008000, /* EMC_CFG_DIG_DLL_PERIOD */ 0x00090000, /* EMC_DLL_XFORM_DQS0 */ 0x00090000, /* EMC_DLL_XFORM_DQS1 */ @@ -235,7 +236,7 @@ static const struct tegra_emc_table enterprise_emc_tables_h5tc2g[] = { 0x00000000, /* EMC_CTT_DURATION */ 0x80000287, /* EMC_DYN_SELF_REF_CONTROL */ 0x00010001, /* MC_EMEM_ARB_CFG */ - 0x8000000a, /* MC_EMEM_ARB_OUTSTANDING_REQ */ + 0xc000000a, /* MC_EMEM_ARB_OUTSTANDING_REQ */ 0x00000001, /* MC_EMEM_ARB_TIMING_RCD */ 0x00000001, /* MC_EMEM_ARB_TIMING_RP */ 0x00000002, /* MC_EMEM_ARB_TIMING_RC */ @@ -261,9 +262,10 @@ static const struct tegra_emc_table enterprise_emc_tables_h5tc2g[] = { 0x00000000, /* Mode Register 0 */ 0x00010022, /* Mode Register 1 */ 0x00020001, /* Mode Register 2 */ + 0x00000001, /* EMC_CFG.DYN_SELF_REF */ }, { - 0x31, /* Rev 3.1 */ + 0x32, /* Rev 3.2 */ 102000, /* SDRAM frequency */ { 0x00000006, /* EMC_RC */ @@ -306,7 +308,7 @@ static const struct tegra_emc_table enterprise_emc_tables_h5tc2g[] = { 0x00000000, /* EMC_ODT_WRITE */ 0x00000000, /* EMC_ODT_READ */ 0x00004282, /* EMC_FBIO_CFG5 */ - 0x00780084, /* EMC_CFG_DIG_DLL */ + 0x007800a4, /* EMC_CFG_DIG_DLL */ 0x00008000, /* EMC_CFG_DIG_DLL_PERIOD */ 0x00090000, /* EMC_DLL_XFORM_DQS0 */ 0x00090000, /* EMC_DLL_XFORM_DQS1 */ @@ -354,7 +356,7 @@ static const struct tegra_emc_table enterprise_emc_tables_h5tc2g[] = { 0x00000000, /* EMC_CTT_DURATION */ 0x8000040b, /* EMC_DYN_SELF_REF_CONTROL */ 0x00000001, /* MC_EMEM_ARB_CFG */ - 0x80000013, /* MC_EMEM_ARB_OUTSTANDING_REQ */ + 0xc0000013, /* MC_EMEM_ARB_OUTSTANDING_REQ */ 0x00000001, /* MC_EMEM_ARB_TIMING_RCD */ 0x00000001, /* MC_EMEM_ARB_TIMING_RP */ 0x00000003, /* MC_EMEM_ARB_TIMING_RC */ @@ -380,9 +382,10 @@ static const struct tegra_emc_table enterprise_emc_tables_h5tc2g[] = { 0x00000000, /* Mode Register 0 */ 0x00010022, /* Mode Register 1 */ 0x00020001, /* Mode Register 2 */ + 0x00000001, /* EMC_CFG.DYN_SELF_REF */ }, { - 0x31, /* Rev 3.1 */ + 0x32, /* Rev 3.2 */ 204000, /* SDRAM frequency */ { 0x0000000c, /* EMC_RC */ @@ -425,7 +428,7 @@ static const struct tegra_emc_table enterprise_emc_tables_h5tc2g[] = { 0x00000000, /* EMC_ODT_WRITE */ 0x00000000, /* EMC_ODT_READ */ 0x00004282, /* EMC_FBIO_CFG5 */ - 0x00440084, /* EMC_CFG_DIG_DLL */ + 0x004400a4, /* EMC_CFG_DIG_DLL */ 0x00008000, /* EMC_CFG_DIG_DLL_PERIOD */ 0x0007c000, /* EMC_DLL_XFORM_DQS0 */ 0x0007c000, /* EMC_DLL_XFORM_DQS1 */ @@ -473,7 +476,7 @@ static const struct tegra_emc_table enterprise_emc_tables_h5tc2g[] = { 0x00000000, /* EMC_CTT_DURATION */ 0x80000713, /* EMC_DYN_SELF_REF_CONTROL */ 0x00000003, /* MC_EMEM_ARB_CFG */ - 0x80000025, /* MC_EMEM_ARB_OUTSTANDING_REQ */ + 0xc0000025, /* MC_EMEM_ARB_OUTSTANDING_REQ */ 0x00000001, /* MC_EMEM_ARB_TIMING_RCD */ 0x00000001, /* MC_EMEM_ARB_TIMING_RP */ 0x00000006, /* MC_EMEM_ARB_TIMING_RC */ @@ -499,9 +502,10 @@ static const struct tegra_emc_table enterprise_emc_tables_h5tc2g[] = { 0x00000000, /* Mode Register 0 */ 0x00010042, /* Mode Register 1 */ 0x00020001, /* Mode Register 2 */ + 0x00000001, /* EMC_CFG.DYN_SELF_REF */ }, { - 0x31, /* Rev 3.1 */ + 0x32, /* Rev 3.2 */ 400000, /* SDRAM frequency */ { 0x00000017, /* EMC_RC */ @@ -618,6 +622,7 @@ static const struct tegra_emc_table enterprise_emc_tables_h5tc2g[] = { 0x00000000, /* Mode Register 0 */ 0x00010082, /* Mode Register 1 */ 0x00020004, /* Mode Register 2 */ + 0x00000000, /* EMC_CFG.DYN_SELF_REF */ }, }; |