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authorAlex Frid <afrid@nvidia.com>2011-11-11 18:19:16 -0800
committerDan Willemsen <dwillemsen@nvidia.com>2011-11-30 21:50:19 -0800
commite6fa3337de9a8d0ee7236f424905d7ccdcc2401e (patch)
tree57f2818152896472b26a40dd636d05ceb1c4d711 /arch/arm/mach-tegra/board-enterprise.c
parent7f650285a37030a14bf9036a95a1d8d66e4cb666 (diff)
ARM: tegra: clock: Support restricted PLLM usage
Added configuration option TEGRA_PLLM_RESTRICTED - when enabled, PLLM - memory PLL - usage may be restricted to modules with dividers capable of dividing maximum PLLM frequency at minimum voltage. When disabled, PLLM is available as a clock source with no restrictions (current configuration), which may effectively increase lower limit for core voltage if high grade SDRAM is used. Implemented PLLM restrictions in Tegra3 clock framework and DVFS, but keep them disabled by default. Bug 884419 Signed-off-by: Alex Frid <afrid@nvidia.com> (cherry picked from commit 5313ebcae92839146870d5865bc0f4cd08b35c61) (cherry picked from commit 634647a9d2a8c1e03c8d98d0b2199950c947acc3) Change-Id: I012452d92830ad6b63ec407350568b8c316b3caa Reviewed-on: http://git-master/r/66512 Reviewed-by: Lokesh Pathak <lpathak@nvidia.com> Tested-by: Lokesh Pathak <lpathak@nvidia.com> Rebase-Id: R22de0f09e7af2640499ec8cd96e974328d78bace
Diffstat (limited to 'arch/arm/mach-tegra/board-enterprise.c')
-rw-r--r--arch/arm/mach-tegra/board-enterprise.c2
1 files changed, 2 insertions, 0 deletions
diff --git a/arch/arm/mach-tegra/board-enterprise.c b/arch/arm/mach-tegra/board-enterprise.c
index dafee77f9638..a5736c7d40de 100644
--- a/arch/arm/mach-tegra/board-enterprise.c
+++ b/arch/arm/mach-tegra/board-enterprise.c
@@ -385,7 +385,9 @@ static struct platform_device *enterprise_uart_devices[] __initdata = {
static struct uart_clk_parent uart_parent_clk[] = {
[0] = {.name = "clk_m"},
[1] = {.name = "pll_p"},
+#ifndef CONFIG_TEGRA_PLLM_RESTRICTED
[2] = {.name = "pll_m"},
+#endif
};
static struct tegra_uart_platform_data enterprise_uart_pdata;