diff options
| author | Matt Wagner <mwagner@nvidia.com> | 2013-03-18 19:06:19 -0700 |
|---|---|---|
| committer | Simone Willett <swillett@nvidia.com> | 2013-03-19 19:30:01 -0700 |
| commit | 9c3ccb8afc328cdf2729c0ae692488bdbba5b91e (patch) | |
| tree | 326bd543612920fa567fcc1eea46c521dde6fd17 /arch/arm/mach-tegra/board-roth-memory.c | |
| parent | 4a5b464edf8f835b92f2bc33f92083cd0cf0c2e3 (diff) | |
ARM: Tegra: Roth: Update DVFS for P2454 and P2560
Bug 1181038
Change-Id: I4923ca85e60220f920ee11d9c18a5538ca31a555
Signed-off-by: Matt Wagner <mwagner@nvidia.com>
Reviewed-on: http://git-master/r/210565
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Diffstat (limited to 'arch/arm/mach-tegra/board-roth-memory.c')
| -rw-r--r-- | arch/arm/mach-tegra/board-roth-memory.c | 3585 |
1 files changed, 3075 insertions, 510 deletions
diff --git a/arch/arm/mach-tegra/board-roth-memory.c b/arch/arm/mach-tegra/board-roth-memory.c index b8681028f0d3..fc7a4af067fc 100644 --- a/arch/arm/mach-tegra/board-roth-memory.c +++ b/arch/arm/mach-tegra/board-roth-memory.c @@ -54,12 +54,12 @@ static struct tegra11_emc_table p2454_h5tc4g63afr_pba_table[] = { 0x00000001, /* EMC_REXT */ 0x00000000, /* EMC_WEXT */ 0x00000005, /* EMC_WDV */ - 0x00000005, /* EMC_WDV_MASK */ + 0x0000000f, /* EMC_WDV_MASK */ 0x00000005, /* EMC_IBDLY */ - 0x00060004, /* EMC_PUTERM_EXTRA */ + 0x00010000, /* EMC_PUTERM_EXTRA */ 0x00000000, /* EMC_CDB_CNTL_2 */ 0x00000004, /* EMC_QRST */ - 0x0000000c, /* EMC_RDV_MASK */ + 0x0000000e, /* EMC_RDV_MASK */ 0x00000060, /* EMC_REFRESH */ 0x00000000, /* EMC_BURST_REFRESH_NUM */ 0x00000018, /* EMC_PRE_REFRESH_REQ_CNT */ @@ -74,7 +74,7 @@ static struct tegra11_emc_table p2454_h5tc4g63afr_pba_table[] = { 0x00000004, /* EMC_TCKE */ 0x00000004, /* EMC_TCKESR */ 0x00000004, /* EMC_TPD */ - 0x00000001, /* EMC_TFAW */ + 0x00000004, /* EMC_TFAW */ 0x00000000, /* EMC_TRPAB */ 0x00000004, /* EMC_TCLKSTABLE */ 0x00000005, /* EMC_TCLKSTOP */ @@ -82,13 +82,13 @@ static struct tegra11_emc_table p2454_h5tc4g63afr_pba_table[] = { 0x00000005, /* EMC_QUSE_EXTRA */ 0x00000020, /* EMC_ODT_WRITE */ 0x00000000, /* EMC_ODT_READ */ - 0x0000a888, /* EMC_FBIO_CFG5 */ + 0x0000aa88, /* EMC_FBIO_CFG5 */ 0x002c00a0, /* EMC_CFG_DIG_DLL */ 0x00008000, /* EMC_CFG_DIG_DLL_PERIOD */ - 0x00064000, /* EMC_DLL_XFORM_DQS4 */ - 0x00064000, /* EMC_DLL_XFORM_DQS5 */ - 0x00064000, /* EMC_DLL_XFORM_DQS6 */ - 0x00064000, /* EMC_DLL_XFORM_DQS7 */ + 0x00070000, /* EMC_DLL_XFORM_DQS4 */ + 0x00070000, /* EMC_DLL_XFORM_DQS5 */ + 0x00070000, /* EMC_DLL_XFORM_DQS6 */ + 0x00070000, /* EMC_DLL_XFORM_DQS7 */ 0x00000000, /* EMC_DLL_XFORM_QUSE4 */ 0x00000000, /* EMC_DLL_XFORM_QUSE5 */ 0x00000000, /* EMC_DLL_XFORM_QUSE6 */ @@ -99,9 +99,9 @@ static struct tegra11_emc_table p2454_h5tc4g63afr_pba_table[] = { 0x00000000, /* EMC_DLI_TRIM_TXDQS7 */ 0x001112a0, /* EMC_XM2CMDPADCTRL */ 0x00000000, /* EMC_XM2CMDPADCTRL4 */ - 0x0003033d, /* EMC_XM2DQSPADCTRL2 */ + 0x0000a11c, /* EMC_XM2DQSPADCTRL2 */ 0x00000000, /* EMC_XM2DQPADCTRL2 */ - 0x77ffc084, /* EMC_XM2CLKPADCTRL */ + 0x77ffc085, /* EMC_XM2CLKPADCTRL */ 0x81f1f108, /* EMC_XM2COMPPADCTRL */ 0x03035504, /* EMC_XM2VTTGENPADCTRL */ 0x0000003f, /* EMC_XM2VTTGENPADCTRL2 */ @@ -141,26 +141,26 @@ static struct tegra11_emc_table p2454_h5tc4g63afr_pba_table[] = { }, { 0x00000000, /* EMC_CDB_CNTL_1 */ - 0x00000006, /* EMC_FBIO_CFG6 */ + 0x00000004, /* EMC_FBIO_CFG6 */ 0x00000006, /* EMC_QUSE */ - 0x00000004, /* EMC_EINPUT */ + 0x00000003, /* EMC_EINPUT */ 0x00000004, /* EMC_EINPUT_DURATION */ - 0x00064000, /* EMC_DLL_XFORM_DQS0 */ + 0x00070000, /* EMC_DLL_XFORM_DQS0 */ 0x0000000a, /* EMC_QSAFE */ 0x00000000, /* EMC_DLL_XFORM_QUSE0 */ 0x0000000c, /* EMC_RDV */ - 0x0079e79e, /* EMC_XM2DQSPADCTRL4 */ - 0x10410400, /* EMC_XM2DQSPADCTRL3 */ + 0x00249249, /* EMC_XM2DQSPADCTRL4 */ + 0x20820800, /* EMC_XM2DQSPADCTRL3 */ 0x00070000, /* EMC_DLL_XFORM_DQ0 */ 0xa0f10000, /* EMC_AUTO_CAL_CONFIG */ 0x00000000, /* EMC_DLL_XFORM_ADDR0 */ - 0x00000909, /* EMC_XM2CLKPADCTRL2 */ + 0x00000a0a, /* EMC_XM2CLKPADCTRL2 */ 0x00000000, /* EMC_DLI_TRIM_TXDQS0 */ 0x00000000, /* EMC_DLL_XFORM_ADDR1 */ 0x00000000, /* EMC_DLL_XFORM_ADDR2 */ - 0x00064000, /* EMC_DLL_XFORM_DQS1 */ - 0x00064000, /* EMC_DLL_XFORM_DQS2 */ - 0x00064000, /* EMC_DLL_XFORM_DQS3 */ + 0x00070000, /* EMC_DLL_XFORM_DQS1 */ + 0x00070000, /* EMC_DLL_XFORM_DQS2 */ + 0x00070000, /* EMC_DLL_XFORM_DQS3 */ 0x00070000, /* EMC_DLL_XFORM_DQ1 */ 0x00070000, /* EMC_DLL_XFORM_DQ2 */ 0x00070000, /* EMC_DLL_XFORM_DQ3 */ @@ -173,26 +173,26 @@ static struct tegra11_emc_table p2454_h5tc4g63afr_pba_table[] = { }, { 0x00000000, /* EMC_CDB_CNTL_1 */ - 0x00000006, /* EMC_FBIO_CFG6 */ + 0x00000004, /* EMC_FBIO_CFG6 */ 0x00000006, /* EMC_QUSE */ - 0x00000004, /* EMC_EINPUT */ + 0x00000003, /* EMC_EINPUT */ 0x00000004, /* EMC_EINPUT_DURATION */ - 0x00064000, /* EMC_DLL_XFORM_DQS0 */ + 0x00070000, /* EMC_DLL_XFORM_DQS0 */ 0x0000000a, /* EMC_QSAFE */ 0x00000000, /* EMC_DLL_XFORM_QUSE0 */ 0x0000000c, /* EMC_RDV */ - 0x0079e79e, /* EMC_XM2DQSPADCTRL4 */ - 0x10410400, /* EMC_XM2DQSPADCTRL3 */ + 0x00249249, /* EMC_XM2DQSPADCTRL4 */ + 0x20820800, /* EMC_XM2DQSPADCTRL3 */ 0x00070000, /* EMC_DLL_XFORM_DQ0 */ 0xa8f10000, /* EMC_AUTO_CAL_CONFIG */ 0x00000000, /* EMC_DLL_XFORM_ADDR0 */ - 0x00000000, /* EMC_XM2CLKPADCTRL2 */ + 0x00000a0a, /* EMC_XM2CLKPADCTRL2 */ 0x00000000, /* EMC_DLI_TRIM_TXDQS0 */ 0x00000000, /* EMC_DLL_XFORM_ADDR1 */ 0x00000000, /* EMC_DLL_XFORM_ADDR2 */ - 0x00064000, /* EMC_DLL_XFORM_DQS1 */ - 0x00064000, /* EMC_DLL_XFORM_DQS2 */ - 0x00064000, /* EMC_DLL_XFORM_DQS3 */ + 0x00070000, /* EMC_DLL_XFORM_DQS1 */ + 0x00070000, /* EMC_DLL_XFORM_DQS2 */ + 0x00070000, /* EMC_DLL_XFORM_DQS3 */ 0x00070000, /* EMC_DLL_XFORM_DQ1 */ 0x00070000, /* EMC_DLL_XFORM_DQ2 */ 0x00070000, /* EMC_DLL_XFORM_DQ3 */ @@ -218,7 +218,7 @@ static struct tegra11_emc_table p2454_h5tc4g63afr_pba_table[] = { }, 0x00000042, /* EMC_ZCAL_WAIT_CNT after clock change */ 0x001fffff, /* EMC_AUTO_CAL_INTERVAL */ - 0x7310000e, /* EMC_CFG */ + 0x7320000e, /* EMC_CFG */ 0x80001221, /* Mode Register 0 */ 0x80100003, /* Mode Register 1 */ 0x80200008, /* Mode Register 2 */ @@ -236,7 +236,7 @@ static struct tegra11_emc_table p2454_h5tc4g63afr_pba_table[] = { 11, /* number of up_down_regs */ { 0x00000000, /* EMC_RC */ - 0x00000004, /* EMC_RFC */ + 0x00000005, /* EMC_RFC */ 0x00000000, /* EMC_RFC_SLR */ 0x00000000, /* EMC_RAS */ 0x00000000, /* EMC_RP */ @@ -250,12 +250,12 @@ static struct tegra11_emc_table p2454_h5tc4g63afr_pba_table[] = { 0x00000001, /* EMC_REXT */ 0x00000000, /* EMC_WEXT */ 0x00000005, /* EMC_WDV */ - 0x00000005, /* EMC_WDV_MASK */ + 0x0000000f, /* EMC_WDV_MASK */ 0x00000005, /* EMC_IBDLY */ - 0x00060004, /* EMC_PUTERM_EXTRA */ + 0x00010000, /* EMC_PUTERM_EXTRA */ 0x00000000, /* EMC_CDB_CNTL_2 */ 0x00000004, /* EMC_QRST */ - 0x0000000c, /* EMC_RDV_MASK */ + 0x0000000e, /* EMC_RDV_MASK */ 0x0000009a, /* EMC_REFRESH */ 0x00000000, /* EMC_BURST_REFRESH_NUM */ 0x00000026, /* EMC_PRE_REFRESH_REQ_CNT */ @@ -270,7 +270,7 @@ static struct tegra11_emc_table p2454_h5tc4g63afr_pba_table[] = { 0x00000004, /* EMC_TCKE */ 0x00000004, /* EMC_TCKESR */ 0x00000004, /* EMC_TPD */ - 0x00000001, /* EMC_TFAW */ + 0x00000004, /* EMC_TFAW */ 0x00000000, /* EMC_TRPAB */ 0x00000004, /* EMC_TCLKSTABLE */ 0x00000005, /* EMC_TCLKSTOP */ @@ -278,13 +278,13 @@ static struct tegra11_emc_table p2454_h5tc4g63afr_pba_table[] = { 0x00000005, /* EMC_QUSE_EXTRA */ 0x00000020, /* EMC_ODT_WRITE */ 0x00000000, /* EMC_ODT_READ */ - 0x0000a888, /* EMC_FBIO_CFG5 */ + 0x0000aa88, /* EMC_FBIO_CFG5 */ 0x002c00a0, /* EMC_CFG_DIG_DLL */ 0x00008000, /* EMC_CFG_DIG_DLL_PERIOD */ - 0x00064000, /* EMC_DLL_XFORM_DQS4 */ - 0x00064000, /* EMC_DLL_XFORM_DQS5 */ - 0x00064000, /* EMC_DLL_XFORM_DQS6 */ - 0x00064000, /* EMC_DLL_XFORM_DQS7 */ + 0x00070000, /* EMC_DLL_XFORM_DQS4 */ + 0x00070000, /* EMC_DLL_XFORM_DQS5 */ + 0x00070000, /* EMC_DLL_XFORM_DQS6 */ + 0x00070000, /* EMC_DLL_XFORM_DQS7 */ 0x00000000, /* EMC_DLL_XFORM_QUSE4 */ 0x00000000, /* EMC_DLL_XFORM_QUSE5 */ 0x00000000, /* EMC_DLL_XFORM_QUSE6 */ @@ -295,9 +295,9 @@ static struct tegra11_emc_table p2454_h5tc4g63afr_pba_table[] = { 0x00000000, /* EMC_DLI_TRIM_TXDQS7 */ 0x001112a0, /* EMC_XM2CMDPADCTRL */ 0x00000000, /* EMC_XM2CMDPADCTRL4 */ - 0x0003033d, /* EMC_XM2DQSPADCTRL2 */ + 0x0000a11c, /* EMC_XM2DQSPADCTRL2 */ 0x00000000, /* EMC_XM2DQPADCTRL2 */ - 0x77ffc084, /* EMC_XM2CLKPADCTRL */ + 0x77ffc085, /* EMC_XM2CLKPADCTRL */ 0x81f1f108, /* EMC_XM2COMPPADCTRL */ 0x03035504, /* EMC_XM2VTTGENPADCTRL */ 0x0000003f, /* EMC_XM2VTTGENPADCTRL2 */ @@ -332,31 +332,31 @@ static struct tegra11_emc_table p2454_h5tc4g63afr_pba_table[] = { 0x00000006, /* MC_EMEM_ARB_TIMING_W2R */ 0x06030102, /* MC_EMEM_ARB_DA_TURNS */ 0x000a0402, /* MC_EMEM_ARB_DA_COVERS */ - 0x75a30303, /* MC_EMEM_ARB_MISC0 */ + 0x76230303, /* MC_EMEM_ARB_MISC0 */ 0x001f0000, /* MC_EMEM_ARB_RING1_THROTTLE */ }, { 0x00000000, /* EMC_CDB_CNTL_1 */ - 0x00000006, /* EMC_FBIO_CFG6 */ + 0x00000004, /* EMC_FBIO_CFG6 */ 0x00000006, /* EMC_QUSE */ - 0x00000004, /* EMC_EINPUT */ + 0x00000003, /* EMC_EINPUT */ 0x00000004, /* EMC_EINPUT_DURATION */ - 0x00064000, /* EMC_DLL_XFORM_DQS0 */ + 0x00070000, /* EMC_DLL_XFORM_DQS0 */ 0x0000000a, /* EMC_QSAFE */ 0x00000000, /* EMC_DLL_XFORM_QUSE0 */ 0x0000000c, /* EMC_RDV */ - 0x0079e79e, /* EMC_XM2DQSPADCTRL4 */ - 0x10410400, /* EMC_XM2DQSPADCTRL3 */ + 0x00249249, /* EMC_XM2DQSPADCTRL4 */ + 0x20820800, /* EMC_XM2DQSPADCTRL3 */ 0x00070000, /* EMC_DLL_XFORM_DQ0 */ 0xa0f10000, /* EMC_AUTO_CAL_CONFIG */ 0x00000000, /* EMC_DLL_XFORM_ADDR0 */ - 0x00000909, /* EMC_XM2CLKPADCTRL2 */ + 0x00000a0a, /* EMC_XM2CLKPADCTRL2 */ 0x00000000, /* EMC_DLI_TRIM_TXDQS0 */ 0x00000000, /* EMC_DLL_XFORM_ADDR1 */ 0x00000000, /* EMC_DLL_XFORM_ADDR2 */ - 0x00064000, /* EMC_DLL_XFORM_DQS1 */ - 0x00064000, /* EMC_DLL_XFORM_DQS2 */ - 0x00064000, /* EMC_DLL_XFORM_DQS3 */ + 0x00070000, /* EMC_DLL_XFORM_DQS1 */ + 0x00070000, /* EMC_DLL_XFORM_DQS2 */ + 0x00070000, /* EMC_DLL_XFORM_DQS3 */ 0x00070000, /* EMC_DLL_XFORM_DQ1 */ 0x00070000, /* EMC_DLL_XFORM_DQ2 */ 0x00070000, /* EMC_DLL_XFORM_DQ3 */ @@ -369,26 +369,26 @@ static struct tegra11_emc_table p2454_h5tc4g63afr_pba_table[] = { }, { 0x00000000, /* EMC_CDB_CNTL_1 */ - 0x00000006, /* EMC_FBIO_CFG6 */ + 0x00000004, /* EMC_FBIO_CFG6 */ 0x00000006, /* EMC_QUSE */ - 0x00000004, /* EMC_EINPUT */ + 0x00000003, /* EMC_EINPUT */ 0x00000004, /* EMC_EINPUT_DURATION */ - 0x00064000, /* EMC_DLL_XFORM_DQS0 */ + 0x00070000, /* EMC_DLL_XFORM_DQS0 */ 0x0000000a, /* EMC_QSAFE */ 0x00000000, /* EMC_DLL_XFORM_QUSE0 */ 0x0000000c, /* EMC_RDV */ - 0x0079e79e, /* EMC_XM2DQSPADCTRL4 */ - 0x10410400, /* EMC_XM2DQSPADCTRL3 */ + 0x00249249, /* EMC_XM2DQSPADCTRL4 */ + 0x20820800, /* EMC_XM2DQSPADCTRL3 */ 0x00070000, /* EMC_DLL_XFORM_DQ0 */ 0xa8f10000, /* EMC_AUTO_CAL_CONFIG */ 0x00000000, /* EMC_DLL_XFORM_ADDR0 */ - 0x00000000, /* EMC_XM2CLKPADCTRL2 */ + 0x00000a0a, /* EMC_XM2CLKPADCTRL2 */ 0x00000000, /* EMC_DLI_TRIM_TXDQS0 */ 0x00000000, /* EMC_DLL_XFORM_ADDR1 */ 0x00000000, /* EMC_DLL_XFORM_ADDR2 */ - 0x00064000, /* EMC_DLL_XFORM_DQS1 */ - 0x00064000, /* EMC_DLL_XFORM_DQS2 */ - 0x00064000, /* EMC_DLL_XFORM_DQS3 */ + 0x00070000, /* EMC_DLL_XFORM_DQS1 */ + 0x00070000, /* EMC_DLL_XFORM_DQS2 */ + 0x00070000, /* EMC_DLL_XFORM_DQS3 */ 0x00070000, /* EMC_DLL_XFORM_DQ1 */ 0x00070000, /* EMC_DLL_XFORM_DQ2 */ 0x00070000, /* EMC_DLL_XFORM_DQ3 */ @@ -414,7 +414,7 @@ static struct tegra11_emc_table p2454_h5tc4g63afr_pba_table[] = { }, 0x00000042, /* EMC_ZCAL_WAIT_CNT after clock change */ 0x001fffff, /* EMC_AUTO_CAL_INTERVAL */ - 0x7310000e, /* EMC_CFG */ + 0x7320000e, /* EMC_CFG */ 0x80001221, /* Mode Register 0 */ 0x80100003, /* Mode Register 1 */ 0x80200008, /* Mode Register 2 */ @@ -432,7 +432,7 @@ static struct tegra11_emc_table p2454_h5tc4g63afr_pba_table[] = { 11, /* number of up_down_regs */ { 0x00000001, /* EMC_RC */ - 0x00000009, /* EMC_RFC */ + 0x0000000a, /* EMC_RFC */ 0x00000000, /* EMC_RFC_SLR */ 0x00000001, /* EMC_RAS */ 0x00000000, /* EMC_RP */ @@ -446,12 +446,12 @@ static struct tegra11_emc_table p2454_h5tc4g63afr_pba_table[] = { 0x00000001, /* EMC_REXT */ 0x00000000, /* EMC_WEXT */ 0x00000005, /* EMC_WDV */ - 0x00000005, /* EMC_WDV_MASK */ + 0x0000000f, /* EMC_WDV_MASK */ 0x00000005, /* EMC_IBDLY */ - 0x00060004, /* EMC_PUTERM_EXTRA */ + 0x00010000, /* EMC_PUTERM_EXTRA */ 0x00000000, /* EMC_CDB_CNTL_2 */ 0x00000004, /* EMC_QRST */ - 0x0000000c, /* EMC_RDV_MASK */ + 0x0000000e, /* EMC_RDV_MASK */ 0x00000134, /* EMC_REFRESH */ 0x00000000, /* EMC_BURST_REFRESH_NUM */ 0x0000004d, /* EMC_PRE_REFRESH_REQ_CNT */ @@ -459,14 +459,14 @@ static struct tegra11_emc_table p2454_h5tc4g63afr_pba_table[] = { 0x00000002, /* EMC_PDEX2RD */ 0x00000001, /* EMC_PCHG2PDEN */ 0x00000000, /* EMC_ACT2PDEN */ - 0x00000007, /* EMC_AR2PDEN */ + 0x00000008, /* EMC_AR2PDEN */ 0x0000000f, /* EMC_RW2PDEN */ - 0x0000000b, /* EMC_TXSR */ - 0x0000000b, /* EMC_TXSRDLL */ + 0x0000000c, /* EMC_TXSR */ + 0x0000000c, /* EMC_TXSRDLL */ 0x00000004, /* EMC_TCKE */ 0x00000004, /* EMC_TCKESR */ 0x00000004, /* EMC_TPD */ - 0x00000002, /* EMC_TFAW */ + 0x00000004, /* EMC_TFAW */ 0x00000000, /* EMC_TRPAB */ 0x00000004, /* EMC_TCLKSTABLE */ 0x00000005, /* EMC_TCLKSTOP */ @@ -474,13 +474,13 @@ static struct tegra11_emc_table p2454_h5tc4g63afr_pba_table[] = { 0x00000005, /* EMC_QUSE_EXTRA */ 0x00000020, /* EMC_ODT_WRITE */ 0x00000000, /* EMC_ODT_READ */ - 0x0000a888, /* EMC_FBIO_CFG5 */ + 0x0000aa88, /* EMC_FBIO_CFG5 */ 0x002c00a0, /* EMC_CFG_DIG_DLL */ 0x00008000, /* EMC_CFG_DIG_DLL_PERIOD */ - 0x00064000, /* EMC_DLL_XFORM_DQS4 */ - 0x00064000, /* EMC_DLL_XFORM_DQS5 */ - 0x00064000, /* EMC_DLL_XFORM_DQS6 */ - 0x00064000, /* EMC_DLL_XFORM_DQS7 */ + 0x00070000, /* EMC_DLL_XFORM_DQS4 */ + 0x00070000, /* EMC_DLL_XFORM_DQS5 */ + 0x00070000, /* EMC_DLL_XFORM_DQS6 */ + 0x00070000, /* EMC_DLL_XFORM_DQS7 */ 0x00000000, /* EMC_DLL_XFORM_QUSE4 */ 0x00000000, /* EMC_DLL_XFORM_QUSE5 */ 0x00000000, /* EMC_DLL_XFORM_QUSE6 */ @@ -491,9 +491,9 @@ static struct tegra11_emc_table p2454_h5tc4g63afr_pba_table[] = { 0x00000000, /* EMC_DLI_TRIM_TXDQS7 */ 0x001112a0, /* EMC_XM2CMDPADCTRL */ 0x00000000, /* EMC_XM2CMDPADCTRL4 */ - 0x0003033d, /* EMC_XM2DQSPADCTRL2 */ + 0x0000a11c, /* EMC_XM2DQSPADCTRL2 */ 0x00000000, /* EMC_XM2DQPADCTRL2 */ - 0x77ffc084, /* EMC_XM2CLKPADCTRL */ + 0x77ffc085, /* EMC_XM2CLKPADCTRL */ 0x81f1f108, /* EMC_XM2COMPPADCTRL */ 0x03035504, /* EMC_XM2VTTGENPADCTRL */ 0x0000003f, /* EMC_XM2VTTGENPADCTRL2 */ @@ -528,31 +528,31 @@ static struct tegra11_emc_table p2454_h5tc4g63afr_pba_table[] = { 0x00000006, /* MC_EMEM_ARB_TIMING_W2R */ 0x06030102, /* MC_EMEM_ARB_DA_TURNS */ 0x000a0402, /* MC_EMEM_ARB_DA_COVERS */ - 0x74630303, /* MC_EMEM_ARB_MISC0 */ + 0x74a30303, /* MC_EMEM_ARB_MISC0 */ 0x001f0000, /* MC_EMEM_ARB_RING1_THROTTLE */ }, { 0x00000000, /* EMC_CDB_CNTL_1 */ - 0x00000006, /* EMC_FBIO_CFG6 */ + 0x00000004, /* EMC_FBIO_CFG6 */ 0x00000006, /* EMC_QUSE */ - 0x00000004, /* EMC_EINPUT */ + 0x00000003, /* EMC_EINPUT */ 0x00000004, /* EMC_EINPUT_DURATION */ - 0x00064000, /* EMC_DLL_XFORM_DQS0 */ + 0x00070000, /* EMC_DLL_XFORM_DQS0 */ 0x0000000a, /* EMC_QSAFE */ 0x00000000, /* EMC_DLL_XFORM_QUSE0 */ 0x0000000c, /* EMC_RDV */ - 0x0079e79e, /* EMC_XM2DQSPADCTRL4 */ - 0x10410400, /* EMC_XM2DQSPADCTRL3 */ + 0x00249249, /* EMC_XM2DQSPADCTRL4 */ + 0x20820800, /* EMC_XM2DQSPADCTRL3 */ 0x00070000, /* EMC_DLL_XFORM_DQ0 */ 0xa0f10000, /* EMC_AUTO_CAL_CONFIG */ 0x00000000, /* EMC_DLL_XFORM_ADDR0 */ - 0x00000909, /* EMC_XM2CLKPADCTRL2 */ + 0x00000a0a, /* EMC_XM2CLKPADCTRL2 */ 0x00000000, /* EMC_DLI_TRIM_TXDQS0 */ 0x00000000, /* EMC_DLL_XFORM_ADDR1 */ 0x00000000, /* EMC_DLL_XFORM_ADDR2 */ - 0x00064000, /* EMC_DLL_XFORM_DQS1 */ - 0x00064000, /* EMC_DLL_XFORM_DQS2 */ - 0x00064000, /* EMC_DLL_XFORM_DQS3 */ + 0x00070000, /* EMC_DLL_XFORM_DQS1 */ + 0x00070000, /* EMC_DLL_XFORM_DQS2 */ + 0x00070000, /* EMC_DLL_XFORM_DQS3 */ 0x00070000, /* EMC_DLL_XFORM_DQ1 */ 0x00070000, /* EMC_DLL_XFORM_DQ2 */ 0x00070000, /* EMC_DLL_XFORM_DQ3 */ @@ -565,26 +565,26 @@ static struct tegra11_emc_table p2454_h5tc4g63afr_pba_table[] = { }, { 0x00000000, /* EMC_CDB_CNTL_1 */ - 0x00000006, /* EMC_FBIO_CFG6 */ + 0x00000004, /* EMC_FBIO_CFG6 */ 0x00000006, /* EMC_QUSE */ - 0x00000004, /* EMC_EINPUT */ + 0x00000003, /* EMC_EINPUT */ 0x00000004, /* EMC_EINPUT_DURATION */ - 0x00064000, /* EMC_DLL_XFORM_DQS0 */ + 0x00070000, /* EMC_DLL_XFORM_DQS0 */ 0x0000000a, /* EMC_QSAFE */ 0x00000000, /* EMC_DLL_XFORM_QUSE0 */ 0x0000000c, /* EMC_RDV */ - 0x0079e79e, /* EMC_XM2DQSPADCTRL4 */ - 0x10410400, /* EMC_XM2DQSPADCTRL3 */ + 0x00249249, /* EMC_XM2DQSPADCTRL4 */ + 0x20820800, /* EMC_XM2DQSPADCTRL3 */ 0x00070000, /* EMC_DLL_XFORM_DQ0 */ 0xa8f10000, /* EMC_AUTO_CAL_CONFIG */ 0x00000000, /* EMC_DLL_XFORM_ADDR0 */ - 0x00000000, /* EMC_XM2CLKPADCTRL2 */ + 0x00000a0a, /* EMC_XM2CLKPADCTRL2 */ 0x00000000, /* EMC_DLI_TRIM_TXDQS0 */ 0x00000000, /* EMC_DLL_XFORM_ADDR1 */ 0x00000000, /* EMC_DLL_XFORM_ADDR2 */ - 0x00064000, /* EMC_DLL_XFORM_DQS1 */ - 0x00064000, /* EMC_DLL_XFORM_DQS2 */ - 0x00064000, /* EMC_DLL_XFORM_DQS3 */ + 0x00070000, /* EMC_DLL_XFORM_DQS1 */ + 0x00070000, /* EMC_DLL_XFORM_DQS2 */ + 0x00070000, /* EMC_DLL_XFORM_DQS3 */ 0x00070000, /* EMC_DLL_XFORM_DQ1 */ 0x00070000, /* EMC_DLL_XFORM_DQ2 */ 0x00070000, /* EMC_DLL_XFORM_DQ3 */ @@ -610,7 +610,7 @@ static struct tegra11_emc_table p2454_h5tc4g63afr_pba_table[] = { }, 0x00000042, /* EMC_ZCAL_WAIT_CNT after clock change */ 0x001fffff, /* EMC_AUTO_CAL_INTERVAL */ - 0x7310000e, /* EMC_CFG */ + 0x7320000e, /* EMC_CFG */ 0x80001221, /* Mode Register 0 */ 0x80100003, /* Mode Register 1 */ 0x80200008, /* Mode Register 2 */ @@ -628,7 +628,7 @@ static struct tegra11_emc_table p2454_h5tc4g63afr_pba_table[] = { 11, /* number of up_down_regs */ { 0x00000003, /* EMC_RC */ - 0x00000010, /* EMC_RFC */ + 0x00000011, /* EMC_RFC */ 0x00000000, /* EMC_RFC_SLR */ 0x00000002, /* EMC_RAS */ 0x00000000, /* EMC_RP */ @@ -642,12 +642,12 @@ static struct tegra11_emc_table p2454_h5tc4g63afr_pba_table[] = { 0x00000001, /* EMC_REXT */ 0x00000000, /* EMC_WEXT */ 0x00000005, /* EMC_WDV */ - 0x00000005, /* EMC_WDV_MASK */ + 0x0000000f, /* EMC_WDV_MASK */ 0x00000005, /* EMC_IBDLY */ - 0x00060004, /* EMC_PUTERM_EXTRA */ + 0x00010000, /* EMC_PUTERM_EXTRA */ 0x00000000, /* EMC_CDB_CNTL_2 */ 0x00000004, /* EMC_QRST */ - 0x0000000c, /* EMC_RDV_MASK */ + 0x0000000e, /* EMC_RDV_MASK */ 0x00000202, /* EMC_REFRESH */ 0x00000000, /* EMC_BURST_REFRESH_NUM */ 0x00000080, /* EMC_PRE_REFRESH_REQ_CNT */ @@ -655,14 +655,14 @@ static struct tegra11_emc_table p2454_h5tc4g63afr_pba_table[] = { 0x00000002, /* EMC_PDEX2RD */ 0x00000001, /* EMC_PCHG2PDEN */ 0x00000000, /* EMC_ACT2PDEN */ - 0x0000000e, /* EMC_AR2PDEN */ + 0x0000000f, /* EMC_AR2PDEN */ 0x0000000f, /* EMC_RW2PDEN */ - 0x00000012, /* EMC_TXSR */ - 0x00000012, /* EMC_TXSRDLL */ + 0x00000013, /* EMC_TXSR */ + 0x00000013, /* EMC_TXSRDLL */ 0x00000004, /* EMC_TCKE */ 0x00000004, /* EMC_TCKESR */ 0x00000004, /* EMC_TPD */ - 0x00000003, /* EMC_TFAW */ + 0x00000004, /* EMC_TFAW */ 0x00000000, /* EMC_TRPAB */ 0x00000004, /* EMC_TCLKSTABLE */ 0x00000005, /* EMC_TCLKSTOP */ @@ -670,13 +670,13 @@ static struct tegra11_emc_table p2454_h5tc4g63afr_pba_table[] = { 0x00000005, /* EMC_QUSE_EXTRA */ 0x00000020, /* EMC_ODT_WRITE */ 0x00000000, /* EMC_ODT_READ */ - 0x0000a888, /* EMC_FBIO_CFG5 */ + 0x0000aa88, /* EMC_FBIO_CFG5 */ 0x002c00a0, /* EMC_CFG_DIG_DLL */ 0x00008000, /* EMC_CFG_DIG_DLL_PERIOD */ - 0x00064000, /* EMC_DLL_XFORM_DQS4 */ - 0x00064000, /* EMC_DLL_XFORM_DQS5 */ - 0x00064000, /* EMC_DLL_XFORM_DQS6 */ - 0x00064000, /* EMC_DLL_XFORM_DQS7 */ + 0x00070000, /* EMC_DLL_XFORM_DQS4 */ + 0x00070000, /* EMC_DLL_XFORM_DQS5 */ + 0x00070000, /* EMC_DLL_XFORM_DQS6 */ + 0x00070000, /* EMC_DLL_XFORM_DQS7 */ 0x00000000, /* EMC_DLL_XFORM_QUSE4 */ 0x00000000, /* EMC_DLL_XFORM_QUSE5 */ 0x00000000, /* EMC_DLL_XFORM_QUSE6 */ @@ -687,9 +687,9 @@ static struct tegra11_emc_table p2454_h5tc4g63afr_pba_table[] = { 0x00000000, /* EMC_DLI_TRIM_TXDQS7 */ 0x001112a0, /* EMC_XM2CMDPADCTRL */ 0x00000000, /* EMC_XM2CMDPADCTRL4 */ - 0x0003033d, /* EMC_XM2DQSPADCTRL2 */ + 0x0000a11c, /* EMC_XM2DQSPADCTRL2 */ 0x00000000, /* EMC_XM2DQPADCTRL2 */ - 0x77ffc084, /* EMC_XM2CLKPADCTRL */ + 0x77ffc085, /* EMC_XM2CLKPADCTRL */ 0x81f1f108, /* EMC_XM2COMPPADCTRL */ 0x03035504, /* EMC_XM2VTTGENPADCTRL */ 0x0000003f, /* EMC_XM2VTTGENPADCTRL2 */ @@ -705,7 +705,7 @@ static struct tegra11_emc_table p2454_h5tc4g63afr_pba_table[] = { 0x00000000, /* EMC_AUTO_CAL_CONFIG3 */ 0x00000000, /* EMC_CTT */ 0x00000000, /* EMC_CTT_DURATION */ - 0x8000050e, /* EMC_DYN_SELF_REF_CONTROL */ + 0x8000050d, /* EMC_DYN_SELF_REF_CONTROL */ 0x1f7df7df, /* EMC_CA_TRAINING_TIMING_CNTL1 */ 0x0000001f, /* EMC_CA_TRAINING_TIMING_CNTL2 */ 0x00000001, /* MC_EMEM_ARB_CFG */ @@ -724,31 +724,31 @@ static struct tegra11_emc_table p2454_h5tc4g63afr_pba_table[] = { 0x00000006, /* MC_EMEM_ARB_TIMING_W2R */ 0x06030102, /* MC_EMEM_ARB_DA_TURNS */ 0x000a0402, /* MC_EMEM_ARB_DA_COVERS */ - 0x73e30403, /* MC_EMEM_ARB_MISC0 */ + 0x74230403, /* MC_EMEM_ARB_MISC0 */ 0x001f0000, /* MC_EMEM_ARB_RING1_THROTTLE */ }, { 0x00000000, /* EMC_CDB_CNTL_1 */ - 0x00000006, /* EMC_FBIO_CFG6 */ + 0x00000004, /* EMC_FBIO_CFG6 */ 0x00000006, /* EMC_QUSE */ - 0x00000004, /* EMC_EINPUT */ + 0x00000003, /* EMC_EINPUT */ 0x00000004, /* EMC_EINPUT_DURATION */ - 0x00064000, /* EMC_DLL_XFORM_DQS0 */ + 0x00070000, /* EMC_DLL_XFORM_DQS0 */ 0x0000000a, /* EMC_QSAFE */ 0x00000000, /* EMC_DLL_XFORM_QUSE0 */ 0x0000000c, /* EMC_RDV */ - 0x0079e79e, /* EMC_XM2DQSPADCTRL4 */ - 0x10410400, /* EMC_XM2DQSPADCTRL3 */ + 0x00249249, /* EMC_XM2DQSPADCTRL4 */ + 0x20820800, /* EMC_XM2DQSPADCTRL3 */ 0x00070000, /* EMC_DLL_XFORM_DQ0 */ 0xa0f10000, /* EMC_AUTO_CAL_CONFIG */ - 0x000d8000, /* EMC_DLL_XFORM_ADDR0 */ - 0x00000000, /* EMC_XM2CLKPADCTRL2 */ + 0x00000000, /* EMC_DLL_XFORM_ADDR0 */ + 0x00001e1e, /* EMC_XM2CLKPADCTRL2 */ 0x00000000, /* EMC_DLI_TRIM_TXDQS0 */ 0x00000000, /* EMC_DLL_XFORM_ADDR1 */ - 0x000d8000, /* EMC_DLL_XFORM_ADDR2 */ - 0x00064000, /* EMC_DLL_XFORM_DQS1 */ - 0x00064000, /* EMC_DLL_XFORM_DQS2 */ - 0x00064000, /* EMC_DLL_XFORM_DQS3 */ + 0x00000000, /* EMC_DLL_XFORM_ADDR2 */ + 0x00070000, /* EMC_DLL_XFORM_DQS1 */ + 0x00070000, /* EMC_DLL_XFORM_DQS2 */ + 0x00070000, /* EMC_DLL_XFORM_DQS3 */ 0x00070000, /* EMC_DLL_XFORM_DQ1 */ 0x00070000, /* EMC_DLL_XFORM_DQ2 */ 0x00070000, /* EMC_DLL_XFORM_DQ3 */ @@ -761,26 +761,26 @@ static struct tegra11_emc_table p2454_h5tc4g63afr_pba_table[] = { }, { 0x00000000, /* EMC_CDB_CNTL_1 */ - 0x00000006, /* EMC_FBIO_CFG6 */ + 0x00000004, /* EMC_FBIO_CFG6 */ 0x00000006, /* EMC_QUSE */ - 0x00000004, /* EMC_EINPUT */ + 0x00000003, /* EMC_EINPUT */ 0x00000004, /* EMC_EINPUT_DURATION */ - 0x00064000, /* EMC_DLL_XFORM_DQS0 */ + 0x00070000, /* EMC_DLL_XFORM_DQS0 */ 0x0000000a, /* EMC_QSAFE */ 0x00000000, /* EMC_DLL_XFORM_QUSE0 */ 0x0000000c, /* EMC_RDV */ - 0x0079e79e, /* EMC_XM2DQSPADCTRL4 */ - 0x10410400, /* EMC_XM2DQSPADCTRL3 */ + 0x00249249, /* EMC_XM2DQSPADCTRL4 */ + 0x20820800, /* EMC_XM2DQSPADCTRL3 */ 0x00070000, /* EMC_DLL_XFORM_DQ0 */ 0xa8f10000, /* EMC_AUTO_CAL_CONFIG */ - 0x000d8000, /* EMC_DLL_XFORM_ADDR0 */ - 0x00000000, /* EMC_XM2CLKPADCTRL2 */ + 0x00000000, /* EMC_DLL_XFORM_ADDR0 */ + 0x00001e1e, /* EMC_XM2CLKPADCTRL2 */ 0x00000000, /* EMC_DLI_TRIM_TXDQS0 */ 0x00000000, /* EMC_DLL_XFORM_ADDR1 */ - 0x000d8000, /* EMC_DLL_XFORM_ADDR2 */ - 0x00064000, /* EMC_DLL_XFORM_DQS1 */ - 0x00064000, /* EMC_DLL_XFORM_DQS2 */ - 0x00064000, /* EMC_DLL_XFORM_DQS3 */ + 0x00000000, /* EMC_DLL_XFORM_ADDR2 */ + 0x00070000, /* EMC_DLL_XFORM_DQS1 */ + 0x00070000, /* EMC_DLL_XFORM_DQS2 */ + 0x00070000, /* EMC_DLL_XFORM_DQS3 */ 0x00070000, /* EMC_DLL_XFORM_DQ1 */ 0x00070000, /* EMC_DLL_XFORM_DQ2 */ 0x00070000, /* EMC_DLL_XFORM_DQ3 */ @@ -806,7 +806,7 @@ static struct tegra11_emc_table p2454_h5tc4g63afr_pba_table[] = { }, 0x00000042, /* EMC_ZCAL_WAIT_CNT after clock change */ 0x001fffff, /* EMC_AUTO_CAL_INTERVAL */ - 0x7310000e, /* EMC_CFG */ + 0x7320000e, /* EMC_CFG */ 0x80001221, /* Mode Register 0 */ 0x80100003, /* Mode Register 1 */ 0x80200008, /* Mode Register 2 */ @@ -824,7 +824,7 @@ static struct tegra11_emc_table p2454_h5tc4g63afr_pba_table[] = { 11, /* number of up_down_regs */ { 0x00000004, /* EMC_RC */ - 0x00000018, /* EMC_RFC */ + 0x0000001a, /* EMC_RFC */ 0x00000000, /* EMC_RFC_SLR */ 0x00000003, /* EMC_RAS */ 0x00000001, /* EMC_RP */ @@ -838,12 +838,12 @@ static struct tegra11_emc_table p2454_h5tc4g63afr_pba_table[] = { 0x00000001, /* EMC_REXT */ 0x00000000, /* EMC_WEXT */ 0x00000005, /* EMC_WDV */ - 0x00000005, /* EMC_WDV_MASK */ + 0x0000000f, /* EMC_WDV_MASK */ 0x00000005, /* EMC_IBDLY */ 0x00010000, /* EMC_PUTERM_EXTRA */ 0x00000000, /* EMC_CDB_CNTL_2 */ 0x00000004, /* EMC_QRST */ - 0x0000000c, /* EMC_RDV_MASK */ + 0x0000000e, /* EMC_RDV_MASK */ 0x00000303, /* EMC_REFRESH */ 0x00000000, /* EMC_BURST_REFRESH_NUM */ 0x000000c0, /* EMC_PRE_REFRESH_REQ_CNT */ @@ -851,10 +851,10 @@ static struct tegra11_emc_table p2454_h5tc4g63afr_pba_table[] = { 0x00000002, /* EMC_PDEX2RD */ 0x00000001, /* EMC_PCHG2PDEN */ 0x00000000, /* EMC_ACT2PDEN */ - 0x00000016, /* EMC_AR2PDEN */ + 0x00000018, /* EMC_AR2PDEN */ 0x0000000f, /* EMC_RW2PDEN */ - 0x0000001a, /* EMC_TXSR */ - 0x0000001a, /* EMC_TXSRDLL */ + 0x0000001c, /* EMC_TXSR */ + 0x0000001c, /* EMC_TXSRDLL */ 0x00000004, /* EMC_TCKE */ 0x00000004, /* EMC_TCKESR */ 0x00000004, /* EMC_TPD */ @@ -869,10 +869,10 @@ static struct tegra11_emc_table p2454_h5tc4g63afr_pba_table[] = { 0x0000aa88, /* EMC_FBIO_CFG5 */ 0x002c00a0, /* EMC_CFG_DIG_DLL */ 0x00008000, /* EMC_CFG_DIG_DLL_PERIOD */ - 0x00064000, /* EMC_DLL_XFORM_DQS4 */ - 0x00064000, /* EMC_DLL_XFORM_DQS5 */ - 0x00064000, /* EMC_DLL_XFORM_DQS6 */ - 0x00064000, /* EMC_DLL_XFORM_DQS7 */ + 0x00070000, /* EMC_DLL_XFORM_DQS4 */ + 0x00070000, /* EMC_DLL_XFORM_DQS5 */ + 0x00070000, /* EMC_DLL_XFORM_DQS6 */ + 0x00070000, /* EMC_DLL_XFORM_DQS7 */ 0x00000000, /* EMC_DLL_XFORM_QUSE4 */ 0x00000000, /* EMC_DLL_XFORM_QUSE5 */ 0x00000000, /* EMC_DLL_XFORM_QUSE6 */ @@ -885,7 +885,7 @@ static struct tegra11_emc_table p2454_h5tc4g63afr_pba_table[] = { 0x00000000, /* EMC_XM2CMDPADCTRL4 */ 0x0000a11c, /* EMC_XM2DQSPADCTRL2 */ 0x00000000, /* EMC_XM2DQPADCTRL2 */ - 0x77ffc084, /* EMC_XM2CLKPADCTRL */ + 0x77ffc085, /* EMC_XM2CLKPADCTRL */ 0x81f1f108, /* EMC_XM2COMPPADCTRL */ 0x03035504, /* EMC_XM2VTTGENPADCTRL */ 0x0000003f, /* EMC_XM2VTTGENPADCTRL2 */ @@ -920,31 +920,31 @@ static struct tegra11_emc_table p2454_h5tc4g63afr_pba_table[] = { 0x00000006, /* MC_EMEM_ARB_TIMING_W2R */ 0x06030102, /* MC_EMEM_ARB_DA_TURNS */ 0x000a0403, /* MC_EMEM_ARB_DA_COVERS */ - 0x73830504, /* MC_EMEM_ARB_MISC0 */ + 0x73c30504, /* MC_EMEM_ARB_MISC0 */ 0x001f0000, /* MC_EMEM_ARB_RING1_THROTTLE */ }, { 0x00000000, /* EMC_CDB_CNTL_1 */ 0x00000006, /* EMC_FBIO_CFG6 */ 0x00000006, /* EMC_QUSE */ - 0x00000004, /* EMC_EINPUT */ + 0x00000005, /* EMC_EINPUT */ 0x00000004, /* EMC_EINPUT_DURATION */ - 0x00064000, /* EMC_DLL_XFORM_DQS0 */ + 0x00070000, /* EMC_DLL_XFORM_DQS0 */ 0x0000000a, /* EMC_QSAFE */ 0x00000000, /* EMC_DLL_XFORM_QUSE0 */ 0x0000000c, /* EMC_RDV */ - 0x00208208, /* EMC_XM2DQSPADCTRL4 */ + 0x00249249, /* EMC_XM2DQSPADCTRL4 */ 0x20820800, /* EMC_XM2DQSPADCTRL3 */ 0x00070000, /* EMC_DLL_XFORM_DQ0 */ 0xa0f10000, /* EMC_AUTO_CAL_CONFIG */ 0x00000000, /* EMC_DLL_XFORM_ADDR0 */ - 0x00000909, /* EMC_XM2CLKPADCTRL2 */ + 0x00000a0a, /* EMC_XM2CLKPADCTRL2 */ 0x00000000, /* EMC_DLI_TRIM_TXDQS0 */ 0x00000000, /* EMC_DLL_XFORM_ADDR1 */ 0x00000000, /* EMC_DLL_XFORM_ADDR2 */ - 0x00064000, /* EMC_DLL_XFORM_DQS1 */ - 0x00064000, /* EMC_DLL_XFORM_DQS2 */ - 0x00064000, /* EMC_DLL_XFORM_DQS3 */ + 0x00070000, /* EMC_DLL_XFORM_DQS1 */ + 0x00070000, /* EMC_DLL_XFORM_DQS2 */ + 0x00070000, /* EMC_DLL_XFORM_DQS3 */ 0x00070000, /* EMC_DLL_XFORM_DQ1 */ 0x00070000, /* EMC_DLL_XFORM_DQ2 */ 0x00070000, /* EMC_DLL_XFORM_DQ3 */ @@ -959,24 +959,24 @@ static struct tegra11_emc_table p2454_h5tc4g63afr_pba_table[] = { 0x00000000, /* EMC_CDB_CNTL_1 */ 0x00000006, /* EMC_FBIO_CFG6 */ 0x00000006, /* EMC_QUSE */ - 0x00000004, /* EMC_EINPUT */ + 0x00000005, /* EMC_EINPUT */ 0x00000004, /* EMC_EINPUT_DURATION */ - 0x00064000, /* EMC_DLL_XFORM_DQS0 */ + 0x00070000, /* EMC_DLL_XFORM_DQS0 */ 0x0000000a, /* EMC_QSAFE */ 0x00000000, /* EMC_DLL_XFORM_QUSE0 */ 0x0000000c, /* EMC_RDV */ - 0x00208208, /* EMC_XM2DQSPADCTRL4 */ + 0x00249249, /* EMC_XM2DQSPADCTRL4 */ 0x20820800, /* EMC_XM2DQSPADCTRL3 */ 0x00070000, /* EMC_DLL_XFORM_DQ0 */ 0xa8f10000, /* EMC_AUTO_CAL_CONFIG */ 0x00000000, /* EMC_DLL_XFORM_ADDR0 */ - 0x00000000, /* EMC_XM2CLKPADCTRL2 */ + 0x00000a0a, /* EMC_XM2CLKPADCTRL2 */ 0x00000000, /* EMC_DLI_TRIM_TXDQS0 */ 0x00000000, /* EMC_DLL_XFORM_ADDR1 */ 0x00000000, /* EMC_DLL_XFORM_ADDR2 */ - 0x00064000, /* EMC_DLL_XFORM_DQS1 */ - 0x00064000, /* EMC_DLL_XFORM_DQS2 */ - 0x00064000, /* EMC_DLL_XFORM_DQS3 */ + 0x00070000, /* EMC_DLL_XFORM_DQS1 */ + 0x00070000, /* EMC_DLL_XFORM_DQS2 */ + 0x00070000, /* EMC_DLL_XFORM_DQS3 */ 0x00070000, /* EMC_DLL_XFORM_DQ1 */ 0x00070000, /* EMC_DLL_XFORM_DQ2 */ 0x00070000, /* EMC_DLL_XFORM_DQ3 */ @@ -1020,7 +1020,7 @@ static struct tegra11_emc_table p2454_h5tc4g63afr_pba_table[] = { 11, /* number of up_down_regs */ { 0x00000009, /* EMC_RC */ - 0x00000031, /* EMC_RFC */ + 0x00000035, /* EMC_RFC */ 0x00000000, /* EMC_RFC_SLR */ 0x00000006, /* EMC_RAS */ 0x00000002, /* EMC_RP */ @@ -1034,12 +1034,12 @@ static struct tegra11_emc_table p2454_h5tc4g63afr_pba_table[] = { 0x00000001, /* EMC_REXT */ 0x00000000, /* EMC_WEXT */ 0x00000005, /* EMC_WDV */ - 0x00000005, /* EMC_WDV_MASK */ + 0x0000000f, /* EMC_WDV_MASK */ 0x00000006, /* EMC_IBDLY */ 0x00010000, /* EMC_PUTERM_EXTRA */ 0x00000000, /* EMC_CDB_CNTL_2 */ 0x00000004, /* EMC_QRST */ - 0x0000000c, /* EMC_RDV_MASK */ + 0x0000000e, /* EMC_RDV_MASK */ 0x00000607, /* EMC_REFRESH */ 0x00000000, /* EMC_BURST_REFRESH_NUM */ 0x00000181, /* EMC_PRE_REFRESH_REQ_CNT */ @@ -1047,10 +1047,10 @@ static struct tegra11_emc_table p2454_h5tc4g63afr_pba_table[] = { 0x00000002, /* EMC_PDEX2RD */ 0x00000001, /* EMC_PCHG2PDEN */ 0x00000000, /* EMC_ACT2PDEN */ - 0x0000002e, /* EMC_AR2PDEN */ + 0x00000032, /* EMC_AR2PDEN */ 0x0000000f, /* EMC_RW2PDEN */ - 0x00000034, /* EMC_TXSR */ - 0x00000034, /* EMC_TXSRDLL */ + 0x00000038, /* EMC_TXSR */ + 0x00000038, /* EMC_TXSRDLL */ 0x00000004, /* EMC_TCKE */ 0x00000004, /* EMC_TCKESR */ 0x00000004, /* EMC_TPD */ @@ -1065,10 +1065,10 @@ static struct tegra11_emc_table p2454_h5tc4g63afr_pba_table[] = { 0x0000aa88, /* EMC_FBIO_CFG5 */ 0x002c00a0, /* EMC_CFG_DIG_DLL */ 0x00008000, /* EMC_CFG_DIG_DLL_PERIOD */ - 0x00070000, /* EMC_DLL_XFORM_DQS4 */ - 0x00070000, /* EMC_DLL_XFORM_DQS5 */ - 0x00070000, /* EMC_DLL_XFORM_DQS6 */ - 0x00070000, /* EMC_DLL_XFORM_DQS7 */ + 0x00064000, /* EMC_DLL_XFORM_DQS4 */ + 0x00064000, /* EMC_DLL_XFORM_DQS5 */ + 0x00064000, /* EMC_DLL_XFORM_DQS6 */ + 0x00064000, /* EMC_DLL_XFORM_DQS7 */ 0x00000000, /* EMC_DLL_XFORM_QUSE4 */ 0x00000000, /* EMC_DLL_XFORM_QUSE5 */ 0x00000000, /* EMC_DLL_XFORM_QUSE6 */ @@ -1081,9 +1081,9 @@ static struct tegra11_emc_table p2454_h5tc4g63afr_pba_table[] = { 0x00000000, /* EMC_XM2CMDPADCTRL4 */ 0x0000a11c, /* EMC_XM2DQSPADCTRL2 */ 0x00000000, /* EMC_XM2DQPADCTRL2 */ - 0x77ffc084, /* EMC_XM2CLKPADCTRL */ + 0x77ffc085, /* EMC_XM2CLKPADCTRL */ 0x81f1f108, /* EMC_XM2COMPPADCTRL */ - 0x03035504, /* EMC_XM2VTTGENPADCTRL */ + 0x05057404, /* EMC_XM2VTTGENPADCTRL */ 0x0000003f, /* EMC_XM2VTTGENPADCTRL2 */ 0x0000003f, /* EMC_DSR_VTTGEN_DRV */ 0x00000000, /* EMC_TXDSRVTTGEN */ @@ -1116,34 +1116,1606 @@ static struct tegra11_emc_table p2454_h5tc4g63afr_pba_table[] = { 0x00000006, /* MC_EMEM_ARB_TIMING_W2R */ 0x06030102, /* MC_EMEM_ARB_DA_TURNS */ 0x000a0404, /* MC_EMEM_ARB_DA_COVERS */ - 0x73440a05, /* MC_EMEM_ARB_MISC0 */ + 0x73840a05, /* MC_EMEM_ARB_MISC0 */ 0x001f0000, /* MC_EMEM_ARB_RING1_THROTTLE */ }, { 0x00000000, /* EMC_CDB_CNTL_1 */ 0x00000004, /* EMC_FBIO_CFG6 */ 0x00000007, /* EMC_QUSE */ - 0x00000004, /* EMC_EINPUT */ + 0x00000005, /* EMC_EINPUT */ + 0x00000005, /* EMC_EINPUT_DURATION */ + 0x00064000, /* EMC_DLL_XFORM_DQS0 */ + 0x0000000a, /* EMC_QSAFE */ + 0x00000000, /* EMC_DLL_XFORM_QUSE0 */ + 0x0000000d, /* EMC_RDV */ + 0x00249249, /* EMC_XM2DQSPADCTRL4 */ + 0x20820800, /* EMC_XM2DQSPADCTRL3 */ + 0x00070000, /* EMC_DLL_XFORM_DQ0 */ + 0xa0f10000, /* EMC_AUTO_CAL_CONFIG */ + 0x00000000, /* EMC_DLL_XFORM_ADDR0 */ + 0x00000a0a, /* EMC_XM2CLKPADCTRL2 */ + 0x00000000, /* EMC_DLI_TRIM_TXDQS0 */ + 0x00000000, /* EMC_DLL_XFORM_ADDR1 */ + 0x00000000, /* EMC_DLL_XFORM_ADDR2 */ + 0x00064000, /* EMC_DLL_XFORM_DQS1 */ + 0x00064000, /* EMC_DLL_XFORM_DQS2 */ + 0x00064000, /* EMC_DLL_XFORM_DQS3 */ + 0x00070000, /* EMC_DLL_XFORM_DQ1 */ + 0x00070000, /* EMC_DLL_XFORM_DQ2 */ + 0x00070000, /* EMC_DLL_XFORM_DQ3 */ + 0x00000000, /* EMC_DLI_TRIM_TXDQS1 */ + 0x00000000, /* EMC_DLI_TRIM_TXDQS2 */ + 0x00000000, /* EMC_DLI_TRIM_TXDQS3 */ + 0x00000000, /* EMC_DLL_XFORM_QUSE1 */ + 0x00000000, /* EMC_DLL_XFORM_QUSE2 */ + 0x00000000, /* EMC_DLL_XFORM_QUSE3 */ + }, + { + 0x00000000, /* EMC_CDB_CNTL_1 */ + 0x00000004, /* EMC_FBIO_CFG6 */ + 0x00000007, /* EMC_QUSE */ + 0x00000005, /* EMC_EINPUT */ + 0x00000005, /* EMC_EINPUT_DURATION */ + 0x00064000, /* EMC_DLL_XFORM_DQS0 */ + 0x0000000a, /* EMC_QSAFE */ + 0x00000000, /* EMC_DLL_XFORM_QUSE0 */ + 0x0000000d, /* EMC_RDV */ + 0x00249249, /* EMC_XM2DQSPADCTRL4 */ + 0x20820800, /* EMC_XM2DQSPADCTRL3 */ + 0x00070000, /* EMC_DLL_XFORM_DQ0 */ + 0xa8f10000, /* EMC_AUTO_CAL_CONFIG */ + 0x00000000, /* EMC_DLL_XFORM_ADDR0 */ + 0x00000a0a, /* EMC_XM2CLKPADCTRL2 */ + 0x00000000, /* EMC_DLI_TRIM_TXDQS0 */ + 0x00000000, /* EMC_DLL_XFORM_ADDR1 */ + 0x00000000, /* EMC_DLL_XFORM_ADDR2 */ + 0x00064000, /* EMC_DLL_XFORM_DQS1 */ + 0x00064000, /* EMC_DLL_XFORM_DQS2 */ + 0x00064000, /* EMC_DLL_XFORM_DQS3 */ + 0x00070000, /* EMC_DLL_XFORM_DQ1 */ + 0x00070000, /* EMC_DLL_XFORM_DQ2 */ + 0x00070000, /* EMC_DLL_XFORM_DQ3 */ + 0x00000000, /* EMC_DLI_TRIM_TXDQS1 */ + 0x00000000, /* EMC_DLI_TRIM_TXDQS2 */ + 0x00000000, /* EMC_DLI_TRIM_TXDQS3 */ + 0x00000000, /* EMC_DLL_XFORM_QUSE1 */ + 0x00000000, /* EMC_DLL_XFORM_QUSE2 */ + 0x00000000, /* EMC_DLL_XFORM_QUSE3 */ + }, + { + 0x000000d0, /* MC_PTSA_GRANT_DECREMENT */ + 0x00230023, /* MC_LATENCY_ALLOWANCE_G2_0 */ + 0x00230027, /* MC_LATENCY_ALLOWANCE_G2_1 */ + 0x002b002f, /* MC_LATENCY_ALLOWANCE_NV_0 */ + 0x0000002f, /* MC_LATENCY_ALLOWANCE_NV2_0 */ + 0x002f002f, /* MC_LATENCY_ALLOWANCE_NV_2 */ + 0x003e002f, /* MC_LATENCY_ALLOWANCE_NV_1 */ + 0x0000003e, /* MC_LATENCY_ALLOWANCE_NV2_1 */ + 0x003e003e, /* MC_LATENCY_ALLOWANCE_NV3 */ + 0x00ff00c8, /* MC_LATENCY_ALLOWANCE_EPP_0 */ + 0x00ff00ff, /* MC_LATENCY_ALLOWANCE_EPP_1 */ + }, + 0x00000042, /* EMC_ZCAL_WAIT_CNT after clock change */ + 0x001fffff, /* EMC_AUTO_CAL_INTERVAL */ + 0x7320000e, /* EMC_CFG */ + 0x80001221, /* Mode Register 0 */ + 0x80100003, /* Mode Register 1 */ + 0x80200008, /* Mode Register 2 */ + 0x00000000, /* Mode Register 4 */ + 3420, /* expected dvfs latency (ns) */ + }, + { + 0x41, /* Rev 4.0.3 */ + 312000, /* SDRAM frequency */ + 1000, /* min voltage */ + "pll_c", /* clock source id */ + 0x24000002, /* CLK_SOURCE_EMC */ + 99, /* number of burst_regs */ + 30, /* number of trim_regs (each channel) */ + 11, /* number of up_down_regs */ + { + 0x0000000d, /* EMC_RC */ + 0x00000050, /* EMC_RFC */ + 0x00000000, /* EMC_RFC_SLR */ + 0x00000009, /* EMC_RAS */ + 0x00000003, /* EMC_RP */ + 0x00000004, /* EMC_R2W */ + 0x00000008, /* EMC_W2R */ + 0x00000002, /* EMC_R2P */ + 0x00000009, /* EMC_W2P */ + 0x00000003, /* EMC_RD_RCD */ + 0x00000003, /* EMC_WR_RCD */ + 0x00000002, /* EMC_RRD */ + 0x00000001, /* EMC_REXT */ + 0x00000000, /* EMC_WEXT */ + 0x00000004, /* EMC_WDV */ + 0x0000000f, /* EMC_WDV_MASK */ + 0x00000007, /* EMC_IBDLY */ + 0x00010000, /* EMC_PUTERM_EXTRA */ + 0x00000000, /* EMC_CDB_CNTL_2 */ + 0x00000004, /* EMC_QRST */ + 0x0000000f, /* EMC_RDV_MASK */ + 0x00000945, /* EMC_REFRESH */ + 0x00000000, /* EMC_BURST_REFRESH_NUM */ + 0x00000251, /* EMC_PRE_REFRESH_REQ_CNT */ + 0x00000001, /* EMC_PDEX2WR */ + 0x00000008, /* EMC_PDEX2RD */ + 0x00000001, /* EMC_PCHG2PDEN */ + 0x00000000, /* EMC_ACT2PDEN */ + 0x0000004d, /* EMC_AR2PDEN */ + 0x0000000e, /* EMC_RW2PDEN */ + 0x00000055, /* EMC_TXSR */ + 0x00000200, /* EMC_TXSRDLL */ + 0x00000004, /* EMC_TCKE */ + 0x00000004, /* EMC_TCKESR */ + 0x00000004, /* EMC_TPD */ + 0x0000000d, /* EMC_TFAW */ + 0x00000000, /* EMC_TRPAB */ + 0x00000004, /* EMC_TCLKSTABLE */ + 0x00000005, /* EMC_TCLKSTOP */ + 0x00000986, /* EMC_TREFBW */ + 0x00000006, /* EMC_QUSE_EXTRA */ + 0x00000020, /* EMC_ODT_WRITE */ + 0x00000000, /* EMC_ODT_READ */ + 0x0000ba88, /* EMC_FBIO_CFG5 */ + 0x002c00a0, /* EMC_CFG_DIG_DLL */ + 0x00008000, /* EMC_CFG_DIG_DLL_PERIOD */ + 0x00038000, /* EMC_DLL_XFORM_DQS4 */ + 0x00038000, /* EMC_DLL_XFORM_DQS5 */ + 0x00038000, /* EMC_DLL_XFORM_DQS6 */ + 0x00038000, /* EMC_DLL_XFORM_DQS7 */ + 0x00000000, /* EMC_DLL_XFORM_QUSE4 */ + 0x00000000, /* EMC_DLL_XFORM_QUSE5 */ + 0x00000000, /* EMC_DLL_XFORM_QUSE6 */ + 0x00000000, /* EMC_DLL_XFORM_QUSE7 */ + 0x00000000, /* EMC_DLI_TRIM_TXDQS4 */ + 0x00000000, /* EMC_DLI_TRIM_TXDQS5 */ + 0x00000000, /* EMC_DLI_TRIM_TXDQS6 */ + 0x00000000, /* EMC_DLI_TRIM_TXDQS7 */ + 0x001112a0, /* EMC_XM2CMDPADCTRL */ + 0x00000000, /* EMC_XM2CMDPADCTRL4 */ + 0x0001013d, /* EMC_XM2DQSPADCTRL2 */ + 0x00000000, /* EMC_XM2DQPADCTRL2 */ + 0x77ffc085, /* EMC_XM2CLKPADCTRL */ + 0x81f1f108, /* EMC_XM2COMPPADCTRL */ + 0x03035504, /* EMC_XM2VTTGENPADCTRL */ + 0x00000000, /* EMC_XM2VTTGENPADCTRL2 */ + 0x0000003f, /* EMC_DSR_VTTGEN_DRV */ + 0x00000000, /* EMC_TXDSRVTTGEN */ + 0x02000000, /* EMC_FBIO_SPARE */ + 0x00000802, /* EMC_CTT_TERM_CTRL */ + 0x00020000, /* EMC_ZCAL_INTERVAL */ + 0x00000100, /* EMC_ZCAL_WAIT_CNT */ + 0x0171000f, /* EMC_MRS_WAIT_CNT */ + 0x0171000f, /* EMC_MRS_WAIT_CNT2 */ + 0x00000000, /* EMC_AUTO_CAL_CONFIG2 */ + 0x00000000, /* EMC_AUTO_CAL_CONFIG3 */ + 0x00000000, /* EMC_CTT */ + 0x00000000, /* EMC_CTT_DURATION */ + 0x80001395, /* EMC_DYN_SELF_REF_CONTROL */ + 0x1f7df7df, /* EMC_CA_TRAINING_TIMING_CNTL1 */ + 0x0000001f, /* EMC_CA_TRAINING_TIMING_CNTL2 */ + 0x0b000004, /* MC_EMEM_ARB_CFG */ + 0x8000016a, /* MC_EMEM_ARB_OUTSTANDING_REQ */ + 0x00000001, /* MC_EMEM_ARB_TIMING_RCD */ + 0x00000002, /* MC_EMEM_ARB_TIMING_RP */ + 0x00000007, /* MC_EMEM_ARB_TIMING_RC */ + 0x00000004, /* MC_EMEM_ARB_TIMING_RAS */ + 0x00000006, /* MC_EMEM_ARB_TIMING_FAW */ + 0x00000001, /* MC_EMEM_ARB_TIMING_RRD */ + 0x00000002, /* MC_EMEM_ARB_TIMING_RAP2PRE */ + 0x00000007, /* MC_EMEM_ARB_TIMING_WAP2PRE */ + 0x00000002, /* MC_EMEM_ARB_TIMING_R2R */ + 0x00000002, /* MC_EMEM_ARB_TIMING_W2W */ + 0x00000004, /* MC_EMEM_ARB_TIMING_R2W */ + 0x00000006, /* MC_EMEM_ARB_TIMING_W2R */ + 0x06040202, /* MC_EMEM_ARB_DA_TURNS */ + 0x000b0607, /* MC_EMEM_ARB_DA_COVERS */ + 0x76e50f08, /* MC_EMEM_ARB_MISC0 */ + 0x001f0000, /* MC_EMEM_ARB_RING1_THROTTLE */ + }, + { + 0x00000000, /* EMC_CDB_CNTL_1 */ + 0x00000006, /* EMC_FBIO_CFG6 */ + 0x00000007, /* EMC_QUSE */ + 0x00000005, /* EMC_EINPUT */ + 0x00000004, /* EMC_EINPUT_DURATION */ + 0x00038000, /* EMC_DLL_XFORM_DQS0 */ + 0x0000000b, /* EMC_QSAFE */ + 0x00000000, /* EMC_DLL_XFORM_QUSE0 */ + 0x0000000e, /* EMC_RDV */ + 0x00249249, /* EMC_XM2DQSPADCTRL4 */ + 0x20820800, /* EMC_XM2DQSPADCTRL3 */ + 0x00048000, /* EMC_DLL_XFORM_DQ0 */ + 0xa0f10000, /* EMC_AUTO_CAL_CONFIG */ + 0x00000000, /* EMC_DLL_XFORM_ADDR0 */ + 0x00000808, /* EMC_XM2CLKPADCTRL2 */ + 0x00000000, /* EMC_DLI_TRIM_TXDQS0 */ + 0x00000000, /* EMC_DLL_XFORM_ADDR1 */ + 0x00000000, /* EMC_DLL_XFORM_ADDR2 */ + 0x00038000, /* EMC_DLL_XFORM_DQS1 */ + 0x00038000, /* EMC_DLL_XFORM_DQS2 */ + 0x00038000, /* EMC_DLL_XFORM_DQS3 */ + 0x00048000, /* EMC_DLL_XFORM_DQ1 */ + 0x00048000, /* EMC_DLL_XFORM_DQ2 */ + 0x00048000, /* EMC_DLL_XFORM_DQ3 */ + 0x00000000, /* EMC_DLI_TRIM_TXDQS1 */ + 0x00000000, /* EMC_DLI_TRIM_TXDQS2 */ + 0x00000000, /* EMC_DLI_TRIM_TXDQS3 */ + 0x00000000, /* EMC_DLL_XFORM_QUSE1 */ + 0x00000000, /* EMC_DLL_XFORM_QUSE2 */ + 0x00000000, /* EMC_DLL_XFORM_QUSE3 */ + }, + { + 0x00000000, /* EMC_CDB_CNTL_1 */ + 0x00000006, /* EMC_FBIO_CFG6 */ + 0x00000007, /* EMC_QUSE */ + 0x00000005, /* EMC_EINPUT */ + 0x00000004, /* EMC_EINPUT_DURATION */ + 0x00038000, /* EMC_DLL_XFORM_DQS0 */ + 0x0000000b, /* EMC_QSAFE */ + 0x00000000, /* EMC_DLL_XFORM_QUSE0 */ + 0x0000000e, /* EMC_RDV */ + 0x00249249, /* EMC_XM2DQSPADCTRL4 */ + 0x20820800, /* EMC_XM2DQSPADCTRL3 */ + 0x00048000, /* EMC_DLL_XFORM_DQ0 */ + 0xa8f10000, /* EMC_AUTO_CAL_CONFIG */ + 0x00000000, /* EMC_DLL_XFORM_ADDR0 */ + 0x00000808, /* EMC_XM2CLKPADCTRL2 */ + 0x00000000, /* EMC_DLI_TRIM_TXDQS0 */ + 0x00000000, /* EMC_DLL_XFORM_ADDR1 */ + 0x00000000, /* EMC_DLL_XFORM_ADDR2 */ + 0x00038000, /* EMC_DLL_XFORM_DQS1 */ + 0x00038000, /* EMC_DLL_XFORM_DQS2 */ + 0x00038000, /* EMC_DLL_XFORM_DQS3 */ + 0x00048000, /* EMC_DLL_XFORM_DQ1 */ + 0x00048000, /* EMC_DLL_XFORM_DQ2 */ + 0x00048000, /* EMC_DLL_XFORM_DQ3 */ + 0x00000000, /* EMC_DLI_TRIM_TXDQS1 */ + 0x00000000, /* EMC_DLI_TRIM_TXDQS2 */ + 0x00000000, /* EMC_DLI_TRIM_TXDQS3 */ + 0x00000000, /* EMC_DLL_XFORM_QUSE1 */ + 0x00000000, /* EMC_DLL_XFORM_QUSE2 */ + 0x00000000, /* EMC_DLL_XFORM_QUSE3 */ + }, + { + 0x00000140, /* MC_PTSA_GRANT_DECREMENT */ + 0x00170017, /* MC_LATENCY_ALLOWANCE_G2_0 */ + 0x00170019, /* MC_LATENCY_ALLOWANCE_G2_1 */ + 0x001c001e, /* MC_LATENCY_ALLOWANCE_NV_0 */ + 0x0000001e, /* MC_LATENCY_ALLOWANCE_NV2_0 */ + 0x001e001e, /* MC_LATENCY_ALLOWANCE_NV_2 */ + 0x0029001e, /* MC_LATENCY_ALLOWANCE_NV_1 */ + 0x00000029, /* MC_LATENCY_ALLOWANCE_NV2_1 */ + 0x00290029, /* MC_LATENCY_ALLOWANCE_NV3 */ + 0x00ff0082, /* MC_LATENCY_ALLOWANCE_EPP_0 */ + 0x00ff00ff, /* MC_LATENCY_ALLOWANCE_EPP_1 */ + }, + 0x00000042, /* EMC_ZCAL_WAIT_CNT after clock change */ + 0x001fffff, /* EMC_AUTO_CAL_INTERVAL */ + 0x5320000e, /* EMC_CFG */ + 0x80000321, /* Mode Register 0 */ + 0x80100002, /* Mode Register 1 */ + 0x80200000, /* Mode Register 2 */ + 0x00000000, /* Mode Register 4 */ + 2680, /* expected dvfs latency (ns) */ + }, + { + 0x41, /* Rev 4.0.3 */ + 408000, /* SDRAM frequency */ + 1000, /* min voltage */ + "pll_p", /* clock source id */ + 0x40000000, /* CLK_SOURCE_EMC */ + 99, /* number of burst_regs */ + 30, /* number of trim_regs (each channel) */ + 11, /* number of up_down_regs */ + { + 0x00000012, /* EMC_RC */ + 0x00000069, /* EMC_RFC */ + 0x00000000, /* EMC_RFC_SLR */ + 0x0000000c, /* EMC_RAS */ + 0x00000004, /* EMC_RP */ + 0x00000005, /* EMC_R2W */ + 0x00000009, /* EMC_W2R */ + 0x00000002, /* EMC_R2P */ + 0x0000000c, /* EMC_W2P */ + 0x00000004, /* EMC_RD_RCD */ + 0x00000004, /* EMC_WR_RCD */ + 0x00000002, /* EMC_RRD */ + 0x00000001, /* EMC_REXT */ + 0x00000000, /* EMC_WEXT */ + 0x00000004, /* EMC_WDV */ + 0x0000000f, /* EMC_WDV_MASK */ + 0x00000007, /* EMC_IBDLY */ + 0x00010000, /* EMC_PUTERM_EXTRA */ + 0x00000000, /* EMC_CDB_CNTL_2 */ + 0x00000004, /* EMC_QRST */ + 0x00000010, /* EMC_RDV_MASK */ + 0x00000c2f, /* EMC_REFRESH */ + 0x00000000, /* EMC_BURST_REFRESH_NUM */ + 0x0000030b, /* EMC_PRE_REFRESH_REQ_CNT */ + 0x00000001, /* EMC_PDEX2WR */ + 0x00000008, /* EMC_PDEX2RD */ + 0x00000001, /* EMC_PCHG2PDEN */ + 0x00000000, /* EMC_ACT2PDEN */ + 0x00000066, /* EMC_AR2PDEN */ + 0x00000011, /* EMC_RW2PDEN */ + 0x0000006f, /* EMC_TXSR */ + 0x00000200, /* EMC_TXSRDLL */ + 0x00000004, /* EMC_TCKE */ + 0x00000004, /* EMC_TCKESR */ + 0x00000004, /* EMC_TPD */ + 0x00000011, /* EMC_TFAW */ + 0x00000000, /* EMC_TRPAB */ + 0x00000004, /* EMC_TCLKSTABLE */ + 0x00000005, /* EMC_TCLKSTOP */ + 0x00000c70, /* EMC_TREFBW */ + 0x00000006, /* EMC_QUSE_EXTRA */ + 0x00000020, /* EMC_ODT_WRITE */ + 0x00000000, /* EMC_ODT_READ */ + 0x0000ba88, /* EMC_FBIO_CFG5 */ + 0x002c0080, /* EMC_CFG_DIG_DLL */ + 0x00008000, /* EMC_CFG_DIG_DLL_PERIOD */ + 0x00028000, /* EMC_DLL_XFORM_DQS4 */ + 0x00028000, /* EMC_DLL_XFORM_DQS5 */ + 0x00028000, /* EMC_DLL_XFORM_DQS6 */ + 0x00028000, /* EMC_DLL_XFORM_DQS7 */ + 0x00000000, /* EMC_DLL_XFORM_QUSE4 */ + 0x00000000, /* EMC_DLL_XFORM_QUSE5 */ + 0x00000000, /* EMC_DLL_XFORM_QUSE6 */ + 0x00000000, /* EMC_DLL_XFORM_QUSE7 */ + 0x00000000, /* EMC_DLI_TRIM_TXDQS4 */ + 0x00000000, /* EMC_DLI_TRIM_TXDQS5 */ + 0x00000000, /* EMC_DLI_TRIM_TXDQS6 */ + 0x00000000, /* EMC_DLI_TRIM_TXDQS7 */ + 0x001112a0, /* EMC_XM2CMDPADCTRL */ + 0x00000000, /* EMC_XM2CMDPADCTRL4 */ + 0x0001013d, /* EMC_XM2DQSPADCTRL2 */ + 0x00000000, /* EMC_XM2DQPADCTRL2 */ + 0x77ffc085, /* EMC_XM2CLKPADCTRL */ + 0x81f1f108, /* EMC_XM2COMPPADCTRL */ + 0x03035504, /* EMC_XM2VTTGENPADCTRL */ + 0x00000000, /* EMC_XM2VTTGENPADCTRL2 */ + 0x0000003f, /* EMC_DSR_VTTGEN_DRV */ + 0x00000000, /* EMC_TXDSRVTTGEN */ + 0x02000000, /* EMC_FBIO_SPARE */ + 0x00000802, /* EMC_CTT_TERM_CTRL */ + 0x00020000, /* EMC_ZCAL_INTERVAL */ + 0x00000100, /* EMC_ZCAL_WAIT_CNT */ + 0x0158000f, /* EMC_MRS_WAIT_CNT */ + 0x0158000f, /* EMC_MRS_WAIT_CNT2 */ + 0x00000000, /* EMC_AUTO_CAL_CONFIG2 */ + 0x00000000, /* EMC_AUTO_CAL_CONFIG3 */ + 0x00000000, /* EMC_CTT */ + 0x00000000, /* EMC_CTT_DURATION */ + 0x80001944, /* EMC_DYN_SELF_REF_CONTROL */ + 0x1f7df7df, /* EMC_CA_TRAINING_TIMING_CNTL1 */ + 0x0000001f, /* EMC_CA_TRAINING_TIMING_CNTL2 */ + 0x02000006, /* MC_EMEM_ARB_CFG */ + 0x80000190, /* MC_EMEM_ARB_OUTSTANDING_REQ */ + 0x00000001, /* MC_EMEM_ARB_TIMING_RCD */ + 0x00000002, /* MC_EMEM_ARB_TIMING_RP */ + 0x00000009, /* MC_EMEM_ARB_TIMING_RC */ + 0x00000005, /* MC_EMEM_ARB_TIMING_RAS */ + 0x00000008, /* MC_EMEM_ARB_TIMING_FAW */ + 0x00000001, /* MC_EMEM_ARB_TIMING_RRD */ + 0x00000002, /* MC_EMEM_ARB_TIMING_RAP2PRE */ + 0x00000009, /* MC_EMEM_ARB_TIMING_WAP2PRE */ + 0x00000002, /* MC_EMEM_ARB_TIMING_R2R */ + 0x00000002, /* MC_EMEM_ARB_TIMING_W2W */ + 0x00000004, /* MC_EMEM_ARB_TIMING_R2W */ + 0x00000006, /* MC_EMEM_ARB_TIMING_W2R */ + 0x06040202, /* MC_EMEM_ARB_DA_TURNS */ + 0x000e0709, /* MC_EMEM_ARB_DA_COVERS */ + 0x7547130a, /* MC_EMEM_ARB_MISC0 */ + 0x001f0000, /* MC_EMEM_ARB_RING1_THROTTLE */ + }, + { + 0x00000000, /* EMC_CDB_CNTL_1 */ + 0x00000006, /* EMC_FBIO_CFG6 */ + 0x00000007, /* EMC_QUSE */ + 0x00000005, /* EMC_EINPUT */ + 0x00000004, /* EMC_EINPUT_DURATION */ + 0x00028000, /* EMC_DLL_XFORM_DQS0 */ + 0x0000000c, /* EMC_QSAFE */ + 0x00000000, /* EMC_DLL_XFORM_QUSE0 */ + 0x0000000e, /* EMC_RDV */ + 0x00249249, /* EMC_XM2DQSPADCTRL4 */ + 0x20820800, /* EMC_XM2DQSPADCTRL3 */ + 0x00038000, /* EMC_DLL_XFORM_DQ0 */ + 0xa0f10000, /* EMC_AUTO_CAL_CONFIG */ + 0x00000000, /* EMC_DLL_XFORM_ADDR0 */ + 0x00000808, /* EMC_XM2CLKPADCTRL2 */ + 0x00000000, /* EMC_DLI_TRIM_TXDQS0 */ + 0x00000000, /* EMC_DLL_XFORM_ADDR1 */ + 0x00000000, /* EMC_DLL_XFORM_ADDR2 */ + 0x00028000, /* EMC_DLL_XFORM_DQS1 */ + 0x00028000, /* EMC_DLL_XFORM_DQS2 */ + 0x00028000, /* EMC_DLL_XFORM_DQS3 */ + 0x00038000, /* EMC_DLL_XFORM_DQ1 */ + 0x00038000, /* EMC_DLL_XFORM_DQ2 */ + 0x00038000, /* EMC_DLL_XFORM_DQ3 */ + 0x00000000, /* EMC_DLI_TRIM_TXDQS1 */ + 0x00000000, /* EMC_DLI_TRIM_TXDQS2 */ + 0x00000000, /* EMC_DLI_TRIM_TXDQS3 */ + 0x00000000, /* EMC_DLL_XFORM_QUSE1 */ + 0x00000000, /* EMC_DLL_XFORM_QUSE2 */ + 0x00000000, /* EMC_DLL_XFORM_QUSE3 */ + }, + { + 0x00000000, /* EMC_CDB_CNTL_1 */ + 0x00000006, /* EMC_FBIO_CFG6 */ + 0x00000007, /* EMC_QUSE */ + 0x00000005, /* EMC_EINPUT */ + 0x00000004, /* EMC_EINPUT_DURATION */ + 0x00028000, /* EMC_DLL_XFORM_DQS0 */ + 0x0000000c, /* EMC_QSAFE */ + 0x00000000, /* EMC_DLL_XFORM_QUSE0 */ + 0x0000000e, /* EMC_RDV */ + 0x00249249, /* EMC_XM2DQSPADCTRL4 */ + 0x20820800, /* EMC_XM2DQSPADCTRL3 */ + 0x00038000, /* EMC_DLL_XFORM_DQ0 */ + 0xa8f10000, /* EMC_AUTO_CAL_CONFIG */ + 0x00000000, /* EMC_DLL_XFORM_ADDR0 */ + 0x00000808, /* EMC_XM2CLKPADCTRL2 */ + 0x00000000, /* EMC_DLI_TRIM_TXDQS0 */ + 0x00000000, /* EMC_DLL_XFORM_ADDR1 */ + 0x00000000, /* EMC_DLL_XFORM_ADDR2 */ + 0x00028000, /* EMC_DLL_XFORM_DQS1 */ + 0x00028000, /* EMC_DLL_XFORM_DQS2 */ + 0x00028000, /* EMC_DLL_XFORM_DQS3 */ + 0x00038000, /* EMC_DLL_XFORM_DQ1 */ + 0x00038000, /* EMC_DLL_XFORM_DQ2 */ + 0x00038000, /* EMC_DLL_XFORM_DQ3 */ + 0x00000000, /* EMC_DLI_TRIM_TXDQS1 */ + 0x00000000, /* EMC_DLI_TRIM_TXDQS2 */ + 0x00000000, /* EMC_DLI_TRIM_TXDQS3 */ + 0x00000000, /* EMC_DLL_XFORM_QUSE1 */ + 0x00000000, /* EMC_DLL_XFORM_QUSE2 */ + 0x00000000, /* EMC_DLL_XFORM_QUSE3 */ + }, + { + 0x000000d1, /* MC_PTSA_GRANT_DECREMENT */ + 0x00110011, /* MC_LATENCY_ALLOWANCE_G2_0 */ + 0x00110013, /* MC_LATENCY_ALLOWANCE_G2_1 */ + 0x00150017, /* MC_LATENCY_ALLOWANCE_NV_0 */ + 0x00000017, /* MC_LATENCY_ALLOWANCE_NV2_0 */ + 0x00170017, /* MC_LATENCY_ALLOWANCE_NV_2 */ + 0x001f0017, /* MC_LATENCY_ALLOWANCE_NV_1 */ + 0x0000001f, /* MC_LATENCY_ALLOWANCE_NV2_1 */ + 0x001f001f, /* MC_LATENCY_ALLOWANCE_NV3 */ + 0x00d30064, /* MC_LATENCY_ALLOWANCE_EPP_0 */ + 0x00d300d3, /* MC_LATENCY_ALLOWANCE_EPP_1 */ + }, + 0x00000042, /* EMC_ZCAL_WAIT_CNT after clock change */ + 0x001fffff, /* EMC_AUTO_CAL_INTERVAL */ + 0x53200006, /* EMC_CFG */ + 0x80000731, /* Mode Register 0 */ + 0x80100002, /* Mode Register 1 */ + 0x80200008, /* Mode Register 2 */ + 0x00000000, /* Mode Register 4 */ + 1750, /* expected dvfs latency (ns) */ + }, + { + 0x41, /* Rev 4.0.3 */ + 450000, /* SDRAM frequency */ + 1100, /* min voltage */ + "pll_m", /* clock source id */ + 0x00000002, /* CLK_SOURCE_EMC */ + 99, /* number of burst_regs */ + 30, /* number of trim_regs (each channel) */ + 11, /* number of up_down_regs */ + { + 0x00000014, /* EMC_RC */ + 0x00000074, /* EMC_RFC */ + 0x00000000, /* EMC_RFC_SLR */ + 0x0000000e, /* EMC_RAS */ + 0x00000005, /* EMC_RP */ + 0x00000005, /* EMC_R2W */ + 0x00000009, /* EMC_W2R */ + 0x00000002, /* EMC_R2P */ + 0x0000000c, /* EMC_W2P */ + 0x00000005, /* EMC_RD_RCD */ + 0x00000005, /* EMC_WR_RCD */ + 0x00000002, /* EMC_RRD */ + 0x00000001, /* EMC_REXT */ + 0x00000000, /* EMC_WEXT */ + 0x00000004, /* EMC_WDV */ + 0x0000000f, /* EMC_WDV_MASK */ + 0x00000007, /* EMC_IBDLY */ + 0x00010000, /* EMC_PUTERM_EXTRA */ + 0x00000000, /* EMC_CDB_CNTL_2 */ + 0x00000004, /* EMC_QRST */ + 0x00000010, /* EMC_RDV_MASK */ + 0x00000d79, /* EMC_REFRESH */ + 0x00000000, /* EMC_BURST_REFRESH_NUM */ + 0x0000035e, /* EMC_PRE_REFRESH_REQ_CNT */ + 0x00000001, /* EMC_PDEX2WR */ + 0x00000009, /* EMC_PDEX2RD */ + 0x00000001, /* EMC_PCHG2PDEN */ + 0x00000000, /* EMC_ACT2PDEN */ + 0x00000071, /* EMC_AR2PDEN */ + 0x00000011, /* EMC_RW2PDEN */ + 0x0000007a, /* EMC_TXSR */ + 0x00000200, /* EMC_TXSRDLL */ + 0x00000004, /* EMC_TCKE */ + 0x00000004, /* EMC_TCKESR */ + 0x00000004, /* EMC_TPD */ + 0x00000013, /* EMC_TFAW */ + 0x00000000, /* EMC_TRPAB */ + 0x00000004, /* EMC_TCLKSTABLE */ + 0x00000005, /* EMC_TCLKSTOP */ + 0x00000dba, /* EMC_TREFBW */ + 0x00000006, /* EMC_QUSE_EXTRA */ + 0x00000020, /* EMC_ODT_WRITE */ + 0x00000000, /* EMC_ODT_READ */ + 0x0000ba88, /* EMC_FBIO_CFG5 */ + 0x002c0080, /* EMC_CFG_DIG_DLL */ + 0x00008000, /* EMC_CFG_DIG_DLL_PERIOD */ + 0x00020000, /* EMC_DLL_XFORM_DQS4 */ + 0x00020000, /* EMC_DLL_XFORM_DQS5 */ + 0x00020000, /* EMC_DLL_XFORM_DQS6 */ + 0x00020000, /* EMC_DLL_XFORM_DQS7 */ + 0x00000000, /* EMC_DLL_XFORM_QUSE4 */ + 0x00000000, /* EMC_DLL_XFORM_QUSE5 */ + 0x00000000, /* EMC_DLL_XFORM_QUSE6 */ + 0x00000000, /* EMC_DLL_XFORM_QUSE7 */ + 0x00000000, /* EMC_DLI_TRIM_TXDQS4 */ + 0x00000000, /* EMC_DLI_TRIM_TXDQS5 */ + 0x00000000, /* EMC_DLI_TRIM_TXDQS6 */ + 0x00000000, /* EMC_DLI_TRIM_TXDQS7 */ + 0x001112a0, /* EMC_XM2CMDPADCTRL */ + 0x00000000, /* EMC_XM2CMDPADCTRL4 */ + 0x0000013d, /* EMC_XM2DQSPADCTRL2 */ + 0x00000000, /* EMC_XM2DQPADCTRL2 */ + 0x77ffc085, /* EMC_XM2CLKPADCTRL */ + 0x81f1f108, /* EMC_XM2COMPPADCTRL */ + 0x03035504, /* EMC_XM2VTTGENPADCTRL */ + 0x00000000, /* EMC_XM2VTTGENPADCTRL2 */ + 0x0000003f, /* EMC_DSR_VTTGEN_DRV */ + 0x00000000, /* EMC_TXDSRVTTGEN */ + 0x02000000, /* EMC_FBIO_SPARE */ + 0x00000802, /* EMC_CTT_TERM_CTRL */ + 0x00020000, /* EMC_ZCAL_INTERVAL */ + 0x00000100, /* EMC_ZCAL_WAIT_CNT */ + 0x014d000f, /* EMC_MRS_WAIT_CNT */ + 0x014d000f, /* EMC_MRS_WAIT_CNT2 */ + 0x00000000, /* EMC_AUTO_CAL_CONFIG2 */ + 0x00000000, /* EMC_AUTO_CAL_CONFIG3 */ + 0x00000000, /* EMC_CTT */ + 0x00000000, /* EMC_CTT_DURATION */ + 0x80001bc7, /* EMC_DYN_SELF_REF_CONTROL */ + 0x1f7df7df, /* EMC_CA_TRAINING_TIMING_CNTL1 */ + 0x0000001f, /* EMC_CA_TRAINING_TIMING_CNTL2 */ + 0x0c000006, /* MC_EMEM_ARB_CFG */ + 0x80000190, /* MC_EMEM_ARB_OUTSTANDING_REQ */ + 0x00000002, /* MC_EMEM_ARB_TIMING_RCD */ + 0x00000003, /* MC_EMEM_ARB_TIMING_RP */ + 0x0000000b, /* MC_EMEM_ARB_TIMING_RC */ + 0x00000006, /* MC_EMEM_ARB_TIMING_RAS */ + 0x00000009, /* MC_EMEM_ARB_TIMING_FAW */ + 0x00000001, /* MC_EMEM_ARB_TIMING_RRD */ + 0x00000002, /* MC_EMEM_ARB_TIMING_RAP2PRE */ + 0x00000009, /* MC_EMEM_ARB_TIMING_WAP2PRE */ + 0x00000002, /* MC_EMEM_ARB_TIMING_R2R */ + 0x00000002, /* MC_EMEM_ARB_TIMING_W2W */ + 0x00000004, /* MC_EMEM_ARB_TIMING_R2W */ + 0x00000006, /* MC_EMEM_ARB_TIMING_W2R */ + 0x06040202, /* MC_EMEM_ARB_DA_TURNS */ + 0x000f080b, /* MC_EMEM_ARB_DA_COVERS */ + 0x74c7150c, /* MC_EMEM_ARB_MISC0 */ + 0x001f0000, /* MC_EMEM_ARB_RING1_THROTTLE */ + }, + { + 0x00000000, /* EMC_CDB_CNTL_1 */ + 0x00000006, /* EMC_FBIO_CFG6 */ + 0x00000007, /* EMC_QUSE */ + 0x00000005, /* EMC_EINPUT */ + 0x00000004, /* EMC_EINPUT_DURATION */ + 0x00020000, /* EMC_DLL_XFORM_DQS0 */ + 0x0000000c, /* EMC_QSAFE */ + 0x00000000, /* EMC_DLL_XFORM_QUSE0 */ + 0x0000000e, /* EMC_RDV */ + 0x00249249, /* EMC_XM2DQSPADCTRL4 */ + 0x20820800, /* EMC_XM2DQSPADCTRL3 */ + 0x00028000, /* EMC_DLL_XFORM_DQ0 */ + 0xa0f10000, /* EMC_AUTO_CAL_CONFIG */ + 0x00000000, /* EMC_DLL_XFORM_ADDR0 */ + 0x00000808, /* EMC_XM2CLKPADCTRL2 */ + 0x00000000, /* EMC_DLI_TRIM_TXDQS0 */ + 0x00000000, /* EMC_DLL_XFORM_ADDR1 */ + 0x00000000, /* EMC_DLL_XFORM_ADDR2 */ + 0x00020000, /* EMC_DLL_XFORM_DQS1 */ + 0x00020000, /* EMC_DLL_XFORM_DQS2 */ + 0x00020000, /* EMC_DLL_XFORM_DQS3 */ + 0x00028000, /* EMC_DLL_XFORM_DQ1 */ + 0x00028000, /* EMC_DLL_XFORM_DQ2 */ + 0x00028000, /* EMC_DLL_XFORM_DQ3 */ + 0x00000000, /* EMC_DLI_TRIM_TXDQS1 */ + 0x00000000, /* EMC_DLI_TRIM_TXDQS2 */ + 0x00000000, /* EMC_DLI_TRIM_TXDQS3 */ + 0x00000000, /* EMC_DLL_XFORM_QUSE1 */ + 0x00000000, /* EMC_DLL_XFORM_QUSE2 */ + 0x00000000, /* EMC_DLL_XFORM_QUSE3 */ + }, + { + 0x00000000, /* EMC_CDB_CNTL_1 */ + 0x00000006, /* EMC_FBIO_CFG6 */ + 0x00000007, /* EMC_QUSE */ + 0x00000005, /* EMC_EINPUT */ + 0x00000004, /* EMC_EINPUT_DURATION */ + 0x00020000, /* EMC_DLL_XFORM_DQS0 */ + 0x0000000c, /* EMC_QSAFE */ + 0x00000000, /* EMC_DLL_XFORM_QUSE0 */ + 0x0000000e, /* EMC_RDV */ + 0x00249249, /* EMC_XM2DQSPADCTRL4 */ + 0x20820800, /* EMC_XM2DQSPADCTRL3 */ + 0x00028000, /* EMC_DLL_XFORM_DQ0 */ + 0xa8f10000, /* EMC_AUTO_CAL_CONFIG */ + 0x00000000, /* EMC_DLL_XFORM_ADDR0 */ + 0x00000808, /* EMC_XM2CLKPADCTRL2 */ + 0x00000000, /* EMC_DLI_TRIM_TXDQS0 */ + 0x00000000, /* EMC_DLL_XFORM_ADDR1 */ + 0x00000000, /* EMC_DLL_XFORM_ADDR2 */ + 0x00020000, /* EMC_DLL_XFORM_DQS1 */ + 0x00020000, /* EMC_DLL_XFORM_DQS2 */ + 0x00020000, /* EMC_DLL_XFORM_DQS3 */ + 0x00028000, /* EMC_DLL_XFORM_DQ1 */ + 0x00028000, /* EMC_DLL_XFORM_DQ2 */ + 0x00028000, /* EMC_DLL_XFORM_DQ3 */ + 0x00000000, /* EMC_DLI_TRIM_TXDQS1 */ + 0x00000000, /* EMC_DLI_TRIM_TXDQS2 */ + 0x00000000, /* EMC_DLI_TRIM_TXDQS3 */ + 0x00000000, /* EMC_DLL_XFORM_QUSE1 */ + 0x00000000, /* EMC_DLL_XFORM_QUSE2 */ + 0x00000000, /* EMC_DLL_XFORM_QUSE3 */ + }, + { + 0x000000e6, /* MC_PTSA_GRANT_DECREMENT */ + 0x00100010, /* MC_LATENCY_ALLOWANCE_G2_0 */ + 0x00100011, /* MC_LATENCY_ALLOWANCE_G2_1 */ + 0x00130015, /* MC_LATENCY_ALLOWANCE_NV_0 */ + 0x00000015, /* MC_LATENCY_ALLOWANCE_NV2_0 */ + 0x00150015, /* MC_LATENCY_ALLOWANCE_NV_2 */ + 0x001c0015, /* MC_LATENCY_ALLOWANCE_NV_1 */ + 0x0000001c, /* MC_LATENCY_ALLOWANCE_NV2_1 */ + 0x001c001c, /* MC_LATENCY_ALLOWANCE_NV3 */ + 0x00c0005a, /* MC_LATENCY_ALLOWANCE_EPP_0 */ + 0x00c000c0, /* MC_LATENCY_ALLOWANCE_EPP_1 */ + }, + 0x00000042, /* EMC_ZCAL_WAIT_CNT after clock change */ + 0x001fffff, /* EMC_AUTO_CAL_INTERVAL */ + 0x53200006, /* EMC_CFG */ + 0x80000731, /* Mode Register 0 */ + 0x80100002, /* Mode Register 1 */ + 0x80200008, /* Mode Register 2 */ + 0x00000000, /* Mode Register 4 */ + 1750, /* expected dvfs latency (ns) */ + }, + { + 0x41, /* Rev 4.0.3 */ + 528000, /* SDRAM frequency */ + 1100, /* min voltage */ + "pll_m", /* clock source id */ + 0x80000000, /* CLK_SOURCE_EMC */ + 99, /* number of burst_regs */ + 30, /* number of trim_regs (each channel) */ + 11, /* number of up_down_regs */ + { + 0x00000018, /* EMC_RC */ + 0x00000088, /* EMC_RFC */ + 0x00000000, /* EMC_RFC_SLR */ + 0x00000010, /* EMC_RAS */ + 0x00000006, /* EMC_RP */ + 0x00000006, /* EMC_R2W */ + 0x00000009, /* EMC_W2R */ + 0x00000002, /* EMC_R2P */ + 0x0000000d, /* EMC_W2P */ + 0x00000006, /* EMC_RD_RCD */ + 0x00000006, /* EMC_WR_RCD */ + 0x00000002, /* EMC_RRD */ + 0x00000001, /* EMC_REXT */ + 0x00000000, /* EMC_WEXT */ + 0x00000005, /* EMC_WDV */ + 0x0000000f, /* EMC_WDV_MASK */ + 0x00000009, /* EMC_IBDLY */ + 0x00010000, /* EMC_PUTERM_EXTRA */ + 0x00000000, /* EMC_CDB_CNTL_2 */ + 0x00000006, /* EMC_QRST */ + 0x00000012, /* EMC_RDV_MASK */ + 0x00000fde, /* EMC_REFRESH */ + 0x00000000, /* EMC_BURST_REFRESH_NUM */ + 0x000003f7, /* EMC_PRE_REFRESH_REQ_CNT */ + 0x00000002, /* EMC_PDEX2WR */ + 0x0000000b, /* EMC_PDEX2RD */ + 0x00000001, /* EMC_PCHG2PDEN */ + 0x00000000, /* EMC_ACT2PDEN */ + 0x00000085, /* EMC_AR2PDEN */ + 0x00000012, /* EMC_RW2PDEN */ + 0x0000008f, /* EMC_TXSR */ + 0x00000200, /* EMC_TXSRDLL */ + 0x00000004, /* EMC_TCKE */ + 0x00000004, /* EMC_TCKESR */ + 0x00000004, /* EMC_TPD */ + 0x00000016, /* EMC_TFAW */ + 0x00000000, /* EMC_TRPAB */ + 0x00000005, /* EMC_TCLKSTABLE */ + 0x00000006, /* EMC_TCLKSTOP */ + 0x0000101f, /* EMC_TREFBW */ + 0x00000008, /* EMC_QUSE_EXTRA */ + 0x00000020, /* EMC_ODT_WRITE */ + 0x00000000, /* EMC_ODT_READ */ + 0x0000ba88, /* EMC_FBIO_CFG5 */ + 0xf0120091, /* EMC_CFG_DIG_DLL */ + 0x00008000, /* EMC_CFG_DIG_DLL_PERIOD */ + 0x00000009, /* EMC_DLL_XFORM_DQS4 */ + 0x00000009, /* EMC_DLL_XFORM_DQS5 */ + 0x00000009, /* EMC_DLL_XFORM_DQS6 */ + 0x00000009, /* EMC_DLL_XFORM_DQS7 */ + 0x00000000, /* EMC_DLL_XFORM_QUSE4 */ + 0x00000000, /* EMC_DLL_XFORM_QUSE5 */ + 0x00000000, /* EMC_DLL_XFORM_QUSE6 */ + 0x00000000, /* EMC_DLL_XFORM_QUSE7 */ + 0x00000000, /* EMC_DLI_TRIM_TXDQS4 */ + 0x00000000, /* EMC_DLI_TRIM_TXDQS5 */ + 0x00000000, /* EMC_DLI_TRIM_TXDQS6 */ + 0x00000000, /* EMC_DLI_TRIM_TXDQS7 */ + 0x001112a0, /* EMC_XM2CMDPADCTRL */ + 0x00000000, /* EMC_XM2CMDPADCTRL4 */ + 0x0000013d, /* EMC_XM2DQSPADCTRL2 */ + 0x00000000, /* EMC_XM2DQPADCTRL2 */ + 0x77ffc085, /* EMC_XM2CLKPADCTRL */ + 0x81f1f108, /* EMC_XM2COMPPADCTRL */ + 0x03035504, /* EMC_XM2VTTGENPADCTRL */ + 0x00000000, /* EMC_XM2VTTGENPADCTRL2 */ + 0x0000003f, /* EMC_DSR_VTTGEN_DRV */ + 0x00000000, /* EMC_TXDSRVTTGEN */ + 0x02000000, /* EMC_FBIO_SPARE */ + 0x00000802, /* EMC_CTT_TERM_CTRL */ + 0x00020000, /* EMC_ZCAL_INTERVAL */ + 0x00000100, /* EMC_ZCAL_WAIT_CNT */ + 0x0139000f, /* EMC_MRS_WAIT_CNT */ + 0x0139000f, /* EMC_MRS_WAIT_CNT2 */ + 0x00000000, /* EMC_AUTO_CAL_CONFIG2 */ + 0x00000000, /* EMC_AUTO_CAL_CONFIG3 */ + 0x00000000, /* EMC_CTT */ + 0x00000000, /* EMC_CTT_DURATION */ + 0x80002073, /* EMC_DYN_SELF_REF_CONTROL */ + 0x1f7df7df, /* EMC_CA_TRAINING_TIMING_CNTL1 */ + 0x0000001f, /* EMC_CA_TRAINING_TIMING_CNTL2 */ + 0x0f000007, /* MC_EMEM_ARB_CFG */ + 0x80000190, /* MC_EMEM_ARB_OUTSTANDING_REQ */ + 0x00000002, /* MC_EMEM_ARB_TIMING_RCD */ + 0x00000003, /* MC_EMEM_ARB_TIMING_RP */ + 0x0000000c, /* MC_EMEM_ARB_TIMING_RC */ + 0x00000007, /* MC_EMEM_ARB_TIMING_RAS */ + 0x0000000a, /* MC_EMEM_ARB_TIMING_FAW */ + 0x00000001, /* MC_EMEM_ARB_TIMING_RRD */ + 0x00000002, /* MC_EMEM_ARB_TIMING_RAP2PRE */ + 0x00000009, /* MC_EMEM_ARB_TIMING_WAP2PRE */ + 0x00000002, /* MC_EMEM_ARB_TIMING_R2R */ + 0x00000002, /* MC_EMEM_ARB_TIMING_W2W */ + 0x00000005, /* MC_EMEM_ARB_TIMING_R2W */ + 0x00000006, /* MC_EMEM_ARB_TIMING_W2R */ + 0x06050202, /* MC_EMEM_ARB_DA_TURNS */ + 0x0010090c, /* MC_EMEM_ARB_DA_COVERS */ + 0x7428180d, /* MC_EMEM_ARB_MISC0 */ + 0x001f0000, /* MC_EMEM_ARB_RING1_THROTTLE */ + }, + { + 0x00000000, /* EMC_CDB_CNTL_1 */ + 0x00000006, /* EMC_FBIO_CFG6 */ + 0x00000009, /* EMC_QUSE */ + 0x00000007, /* EMC_EINPUT */ + 0x00000004, /* EMC_EINPUT_DURATION */ + 0x00000009, /* EMC_DLL_XFORM_DQS0 */ + 0x0000000c, /* EMC_QSAFE */ + 0x00000000, /* EMC_DLL_XFORM_QUSE0 */ + 0x00000010, /* EMC_RDV */ + 0x00249249, /* EMC_XM2DQSPADCTRL4 */ + 0x20820800, /* EMC_XM2DQSPADCTRL3 */ + 0x0000000b, /* EMC_DLL_XFORM_DQ0 */ + 0xa0f10000, /* EMC_AUTO_CAL_CONFIG */ + 0x00000000, /* EMC_DLL_XFORM_ADDR0 */ + 0x00000808, /* EMC_XM2CLKPADCTRL2 */ + 0x00000000, /* EMC_DLI_TRIM_TXDQS0 */ + 0x00000000, /* EMC_DLL_XFORM_ADDR1 */ + 0x00000000, /* EMC_DLL_XFORM_ADDR2 */ + 0x00000009, /* EMC_DLL_XFORM_DQS1 */ + 0x00000009, /* EMC_DLL_XFORM_DQS2 */ + 0x00000009, /* EMC_DLL_XFORM_DQS3 */ + 0x0000000b, /* EMC_DLL_XFORM_DQ1 */ + 0x0000000b, /* EMC_DLL_XFORM_DQ2 */ + 0x0000000b, /* EMC_DLL_XFORM_DQ3 */ + 0x00000000, /* EMC_DLI_TRIM_TXDQS1 */ + 0x00000000, /* EMC_DLI_TRIM_TXDQS2 */ + 0x00000000, /* EMC_DLI_TRIM_TXDQS3 */ + 0x00000000, /* EMC_DLL_XFORM_QUSE1 */ + 0x00000000, /* EMC_DLL_XFORM_QUSE2 */ + 0x00000000, /* EMC_DLL_XFORM_QUSE3 */ + }, + { + 0x00000000, /* EMC_CDB_CNTL_1 */ + 0x00000006, /* EMC_FBIO_CFG6 */ + 0x00000009, /* EMC_QUSE */ + 0x00000007, /* EMC_EINPUT */ + 0x00000004, /* EMC_EINPUT_DURATION */ + 0x00000009, /* EMC_DLL_XFORM_DQS0 */ + 0x0000000c, /* EMC_QSAFE */ + 0x00000000, /* EMC_DLL_XFORM_QUSE0 */ + 0x00000010, /* EMC_RDV */ + 0x00249249, /* EMC_XM2DQSPADCTRL4 */ + 0x20820800, /* EMC_XM2DQSPADCTRL3 */ + 0x0000000b, /* EMC_DLL_XFORM_DQ0 */ + 0xa8f10000, /* EMC_AUTO_CAL_CONFIG */ + 0x00000000, /* EMC_DLL_XFORM_ADDR0 */ + 0x00000808, /* EMC_XM2CLKPADCTRL2 */ + 0x00000000, /* EMC_DLI_TRIM_TXDQS0 */ + 0x00000000, /* EMC_DLL_XFORM_ADDR1 */ + 0x00000000, /* EMC_DLL_XFORM_ADDR2 */ + 0x00000009, /* EMC_DLL_XFORM_DQS1 */ + 0x00000009, /* EMC_DLL_XFORM_DQS2 */ + 0x00000009, /* EMC_DLL_XFORM_DQS3 */ + 0x0000000b, /* EMC_DLL_XFORM_DQ1 */ + 0x0000000b, /* EMC_DLL_XFORM_DQ2 */ + 0x0000000b, /* EMC_DLL_XFORM_DQ3 */ + 0x00000000, /* EMC_DLI_TRIM_TXDQS1 */ + 0x00000000, /* EMC_DLI_TRIM_TXDQS2 */ + 0x00000000, /* EMC_DLI_TRIM_TXDQS3 */ + 0x00000000, /* EMC_DLL_XFORM_QUSE1 */ + 0x00000000, /* EMC_DLL_XFORM_QUSE2 */ + 0x00000000, /* EMC_DLL_XFORM_QUSE3 */ + }, + { + 0x0000010e, /* MC_PTSA_GRANT_DECREMENT */ + 0x000d000d, /* MC_LATENCY_ALLOWANCE_G2_0 */ + 0x000d000f, /* MC_LATENCY_ALLOWANCE_G2_1 */ + 0x00100012, /* MC_LATENCY_ALLOWANCE_NV_0 */ + 0x00000012, /* MC_LATENCY_ALLOWANCE_NV2_0 */ + 0x00120012, /* MC_LATENCY_ALLOWANCE_NV_2 */ + 0x00180012, /* MC_LATENCY_ALLOWANCE_NV_1 */ + 0x00000018, /* MC_LATENCY_ALLOWANCE_NV2_1 */ + 0x00180018, /* MC_LATENCY_ALLOWANCE_NV3 */ + 0x00a3004d, /* MC_LATENCY_ALLOWANCE_EPP_0 */ + 0x00a300a3, /* MC_LATENCY_ALLOWANCE_EPP_1 */ + }, + 0x00000042, /* EMC_ZCAL_WAIT_CNT after clock change */ + 0x001fffff, /* EMC_AUTO_CAL_INTERVAL */ + 0x53200004, /* EMC_CFG */ + 0x80000941, /* Mode Register 0 */ + 0x80100002, /* Mode Register 1 */ + 0x80200008, /* Mode Register 2 */ + 0x00000000, /* Mode Register 4 */ + 1440, /* expected dvfs latency (ns) */ + }, + { + 0x41, /* Rev 4.0.3 */ + 624000, /* SDRAM frequency */ + 1100, /* min voltage */ + "pll_c", /* clock source id */ + 0x24000000, /* CLK_SOURCE_EMC */ + 99, /* number of burst_regs */ + 30, /* number of trim_regs (each channel) */ + 11, /* number of up_down_regs */ + { + 0x0000001c, /* EMC_RC */ + 0x000000a1, /* EMC_RFC */ + 0x00000000, /* EMC_RFC_SLR */ + 0x00000014, /* EMC_RAS */ + 0x00000007, /* EMC_RP */ + 0x00000007, /* EMC_R2W */ + 0x0000000b, /* EMC_W2R */ + 0x00000003, /* EMC_R2P */ + 0x00000010, /* EMC_W2P */ + 0x00000007, /* EMC_RD_RCD */ + 0x00000007, /* EMC_WR_RCD */ + 0x00000002, /* EMC_RRD */ + 0x00000001, /* EMC_REXT */ + 0x00000000, /* EMC_WEXT */ + 0x00000005, /* EMC_WDV */ + 0x0000000f, /* EMC_WDV_MASK */ + 0x0000000b, /* EMC_IBDLY */ + 0x00010000, /* EMC_PUTERM_EXTRA */ + 0x00000000, /* EMC_CDB_CNTL_2 */ + 0x00000007, /* EMC_QRST */ + 0x00000013, /* EMC_RDV_MASK */ + 0x000012cb, /* EMC_REFRESH */ + 0x00000000, /* EMC_BURST_REFRESH_NUM */ + 0x000004b2, /* EMC_PRE_REFRESH_REQ_CNT */ + 0x00000002, /* EMC_PDEX2WR */ + 0x0000000d, /* EMC_PDEX2RD */ + 0x00000001, /* EMC_PCHG2PDEN */ + 0x00000000, /* EMC_ACT2PDEN */ + 0x000000a5, /* EMC_AR2PDEN */ + 0x00000015, /* EMC_RW2PDEN */ + 0x000000a9, /* EMC_TXSR */ + 0x00000200, /* EMC_TXSRDLL */ + 0x00000005, /* EMC_TCKE */ + 0x00000005, /* EMC_TCKESR */ + 0x00000005, /* EMC_TPD */ + 0x00000019, /* EMC_TFAW */ + 0x00000000, /* EMC_TRPAB */ + 0x00000006, /* EMC_TCLKSTABLE */ + 0x00000007, /* EMC_TCLKSTOP */ + 0x0000130b, /* EMC_TREFBW */ + 0x00000009, /* EMC_QUSE_EXTRA */ + 0x00000020, /* EMC_ODT_WRITE */ + 0x00000000, /* EMC_ODT_READ */ + 0x0000ba88, /* EMC_FBIO_CFG5 */ + 0xf00d0191, /* EMC_CFG_DIG_DLL */ + 0x00008000, /* EMC_CFG_DIG_DLL_PERIOD */ + 0x0000000a, /* EMC_DLL_XFORM_DQS4 */ + 0x0000000a, /* EMC_DLL_XFORM_DQS5 */ + 0x0000000a, /* EMC_DLL_XFORM_DQS6 */ + 0x0000000a, /* EMC_DLL_XFORM_DQS7 */ + 0x00000000, /* EMC_DLL_XFORM_QUSE4 */ + 0x00000000, /* EMC_DLL_XFORM_QUSE5 */ + 0x00000000, /* EMC_DLL_XFORM_QUSE6 */ + 0x00000000, /* EMC_DLL_XFORM_QUSE7 */ + 0x00000000, /* EMC_DLI_TRIM_TXDQS4 */ + 0x00000000, /* EMC_DLI_TRIM_TXDQS5 */ + 0x00000000, /* EMC_DLI_TRIM_TXDQS6 */ + 0x00000000, /* EMC_DLI_TRIM_TXDQS7 */ + 0x001112a0, /* EMC_XM2CMDPADCTRL */ + 0x00000000, /* EMC_XM2CMDPADCTRL4 */ + 0x0000013d, /* EMC_XM2DQSPADCTRL2 */ + 0x00000000, /* EMC_XM2DQPADCTRL2 */ + 0x77ffc085, /* EMC_XM2CLKPADCTRL */ + 0x81f1f108, /* EMC_XM2COMPPADCTRL */ + 0x07077504, /* EMC_XM2VTTGENPADCTRL */ + 0x00000000, /* EMC_XM2VTTGENPADCTRL2 */ + 0x0000003f, /* EMC_DSR_VTTGEN_DRV */ + 0x00000000, /* EMC_TXDSRVTTGEN */ + 0x02000000, /* EMC_FBIO_SPARE */ + 0x00000802, /* EMC_CTT_TERM_CTRL */ + 0x00020000, /* EMC_ZCAL_INTERVAL */ + 0x00000100, /* EMC_ZCAL_WAIT_CNT */ + 0x0122000f, /* EMC_MRS_WAIT_CNT */ + 0x0122000f, /* EMC_MRS_WAIT_CNT2 */ + 0x00000000, /* EMC_AUTO_CAL_CONFIG2 */ + 0x00000000, /* EMC_AUTO_CAL_CONFIG3 */ + 0x00000000, /* EMC_CTT */ + 0x00000000, /* EMC_CTT_DURATION */ + 0x80002626, /* EMC_DYN_SELF_REF_CONTROL */ + 0x1f7df7df, /* EMC_CA_TRAINING_TIMING_CNTL1 */ + 0x0000001f, /* EMC_CA_TRAINING_TIMING_CNTL2 */ + 0x06000009, /* MC_EMEM_ARB_CFG */ + 0x80000190, /* MC_EMEM_ARB_OUTSTANDING_REQ */ + 0x00000003, /* MC_EMEM_ARB_TIMING_RCD */ + 0x00000004, /* MC_EMEM_ARB_TIMING_RP */ + 0x0000000f, /* MC_EMEM_ARB_TIMING_RC */ + 0x00000009, /* MC_EMEM_ARB_TIMING_RAS */ + 0x0000000c, /* MC_EMEM_ARB_TIMING_FAW */ + 0x00000001, /* MC_EMEM_ARB_TIMING_RRD */ + 0x00000003, /* MC_EMEM_ARB_TIMING_RAP2PRE */ + 0x0000000b, /* MC_EMEM_ARB_TIMING_WAP2PRE */ + 0x00000002, /* MC_EMEM_ARB_TIMING_R2R */ + 0x00000002, /* MC_EMEM_ARB_TIMING_W2W */ + 0x00000005, /* MC_EMEM_ARB_TIMING_R2W */ + 0x00000007, /* MC_EMEM_ARB_TIMING_W2R */ + 0x07050202, /* MC_EMEM_ARB_DA_TURNS */ + 0x00130b0f, /* MC_EMEM_ARB_DA_COVERS */ + 0x736a1d10, /* MC_EMEM_ARB_MISC0 */ + 0x001f0000, /* MC_EMEM_ARB_RING1_THROTTLE */ + }, + { + 0x00000000, /* EMC_CDB_CNTL_1 */ + 0x00000006, /* EMC_FBIO_CFG6 */ + 0x0000000a, /* EMC_QUSE */ + 0x00000007, /* EMC_EINPUT */ + 0x00000005, /* EMC_EINPUT_DURATION */ + 0x0000000a, /* EMC_DLL_XFORM_DQS0 */ + 0x0000000c, /* EMC_QSAFE */ + 0x00000000, /* EMC_DLL_XFORM_QUSE0 */ + 0x00000011, /* EMC_RDV */ + 0x00249249, /* EMC_XM2DQSPADCTRL4 */ + 0x20820800, /* EMC_XM2DQSPADCTRL3 */ + 0x0000000b, /* EMC_DLL_XFORM_DQ0 */ + 0xa0f10000, /* EMC_AUTO_CAL_CONFIG */ + 0x00000000, /* EMC_DLL_XFORM_ADDR0 */ + 0x00000808, /* EMC_XM2CLKPADCTRL2 */ + 0x00000000, /* EMC_DLI_TRIM_TXDQS0 */ + 0x00000000, /* EMC_DLL_XFORM_ADDR1 */ + 0x00000000, /* EMC_DLL_XFORM_ADDR2 */ + 0x0000000a, /* EMC_DLL_XFORM_DQS1 */ + 0x0000000a, /* EMC_DLL_XFORM_DQS2 */ + 0x0000000a, /* EMC_DLL_XFORM_DQS3 */ + 0x0000000a, /* EMC_DLL_XFORM_DQ1 */ + 0x0000000b, /* EMC_DLL_XFORM_DQ2 */ + 0x0000000b, /* EMC_DLL_XFORM_DQ3 */ + 0x00000000, /* EMC_DLI_TRIM_TXDQS1 */ + 0x00000000, /* EMC_DLI_TRIM_TXDQS2 */ + 0x00000000, /* EMC_DLI_TRIM_TXDQS3 */ + 0x00000000, /* EMC_DLL_XFORM_QUSE1 */ + 0x00000000, /* EMC_DLL_XFORM_QUSE2 */ + 0x00000000, /* EMC_DLL_XFORM_QUSE3 */ + }, + { + 0x00000000, /* EMC_CDB_CNTL_1 */ + 0x00000006, /* EMC_FBIO_CFG6 */ + 0x0000000a, /* EMC_QUSE */ + 0x00000007, /* EMC_EINPUT */ + 0x00000005, /* EMC_EINPUT_DURATION */ + 0x0000000a, /* EMC_DLL_XFORM_DQS0 */ + 0x0000000c, /* EMC_QSAFE */ + 0x00000000, /* EMC_DLL_XFORM_QUSE0 */ + 0x00000011, /* EMC_RDV */ + 0x00249249, /* EMC_XM2DQSPADCTRL4 */ + 0x20820800, /* EMC_XM2DQSPADCTRL3 */ + 0x0000000a, /* EMC_DLL_XFORM_DQ0 */ + 0xa8f10000, /* EMC_AUTO_CAL_CONFIG */ + 0x00000000, /* EMC_DLL_XFORM_ADDR0 */ + 0x00000808, /* EMC_XM2CLKPADCTRL2 */ + 0x00000000, /* EMC_DLI_TRIM_TXDQS0 */ + 0x00000000, /* EMC_DLL_XFORM_ADDR1 */ + 0x00000000, /* EMC_DLL_XFORM_ADDR2 */ + 0x0000000a, /* EMC_DLL_XFORM_DQS1 */ + 0x0000000a, /* EMC_DLL_XFORM_DQS2 */ + 0x0000000a, /* EMC_DLL_XFORM_DQS3 */ + 0x0000000a, /* EMC_DLL_XFORM_DQ1 */ + 0x0000000a, /* EMC_DLL_XFORM_DQ2 */ + 0x0000000a, /* EMC_DLL_XFORM_DQ3 */ + 0x00000000, /* EMC_DLI_TRIM_TXDQS1 */ + 0x00000000, /* EMC_DLI_TRIM_TXDQS2 */ + 0x00000000, /* EMC_DLI_TRIM_TXDQS3 */ + 0x00000000, /* EMC_DLL_XFORM_QUSE1 */ + 0x00000000, /* EMC_DLL_XFORM_QUSE2 */ + 0x00000000, /* EMC_DLL_XFORM_QUSE3 */ + }, + { + 0x0000013f, /* MC_PTSA_GRANT_DECREMENT */ + 0x000b000b, /* MC_LATENCY_ALLOWANCE_G2_0 */ + 0x000b000c, /* MC_LATENCY_ALLOWANCE_G2_1 */ + 0x000e000f, /* MC_LATENCY_ALLOWANCE_NV_0 */ + 0x0000000f, /* MC_LATENCY_ALLOWANCE_NV2_0 */ + 0x000f000f, /* MC_LATENCY_ALLOWANCE_NV_2 */ + 0x0014000f, /* MC_LATENCY_ALLOWANCE_NV_1 */ + 0x00000014, /* MC_LATENCY_ALLOWANCE_NV2_1 */ + 0x00140014, /* MC_LATENCY_ALLOWANCE_NV3 */ + 0x008a0041, /* MC_LATENCY_ALLOWANCE_EPP_0 */ + 0x008a008a, /* MC_LATENCY_ALLOWANCE_EPP_1 */ + }, + 0x00000042, /* EMC_ZCAL_WAIT_CNT after clock change */ + 0x001fffff, /* EMC_AUTO_CAL_INTERVAL */ + 0x53200000, /* EMC_CFG */ + 0x80000b61, /* Mode Register 0 */ + 0x80100002, /* Mode Register 1 */ + 0x80200010, /* Mode Register 2 */ + 0x00000000, /* Mode Register 4 */ + 1440, /* expected dvfs latency (ns) */ + }, + { + 0x41, /* Rev 4.0.3 */ + 792000, /* SDRAM frequency */ + 1100, /* min voltage */ + "pll_m", /* clock source id */ + 0x80000000, /* CLK_SOURCE_EMC */ + 99, /* number of burst_regs */ + 30, /* number of trim_regs (each channel) */ + 11, /* number of up_down_regs */ + { + 0x00000025, /* EMC_RC */ + 0x000000cd, /* EMC_RFC */ + 0x00000000, /* EMC_RFC_SLR */ + 0x00000019, /* EMC_RAS */ + 0x0000000a, /* EMC_RP */ + 0x00000009, /* EMC_R2W */ + 0x0000000d, /* EMC_W2R */ + 0x00000004, /* EMC_R2P */ + 0x00000013, /* EMC_W2P */ + 0x0000000a, /* EMC_RD_RCD */ + 0x0000000a, /* EMC_WR_RCD */ + 0x00000003, /* EMC_RRD */ + 0x00000001, /* EMC_REXT */ + 0x00000000, /* EMC_WEXT */ + 0x00000006, /* EMC_WDV */ + 0x0000000f, /* EMC_WDV_MASK */ + 0x0000000c, /* EMC_IBDLY */ + 0x000d000a, /* EMC_PUTERM_EXTRA */ + 0x00000000, /* EMC_CDB_CNTL_2 */ + 0x00000009, /* EMC_QRST */ + 0x00000016, /* EMC_RDV_MASK */ + 0x000017ee, /* EMC_REFRESH */ + 0x00000000, /* EMC_BURST_REFRESH_NUM */ + 0x000005fb, /* EMC_PRE_REFRESH_REQ_CNT */ + 0x00000003, /* EMC_PDEX2WR */ + 0x00000012, /* EMC_PDEX2RD */ + 0x00000001, /* EMC_PCHG2PDEN */ + 0x00000000, /* EMC_ACT2PDEN */ + 0x000000c6, /* EMC_AR2PDEN */ + 0x00000018, /* EMC_RW2PDEN */ + 0x000000d7, /* EMC_TXSR */ + 0x00000200, /* EMC_TXSRDLL */ + 0x00000005, /* EMC_TCKE */ + 0x00000005, /* EMC_TCKESR */ + 0x00000005, /* EMC_TPD */ + 0x00000020, /* EMC_TFAW */ + 0x00000000, /* EMC_TRPAB */ + 0x00000007, /* EMC_TCLKSTABLE */ + 0x00000008, /* EMC_TCLKSTOP */ + 0x0000182f, /* EMC_TREFBW */ + 0x0000000b, /* EMC_QUSE_EXTRA */ + 0x80000000, /* EMC_ODT_WRITE */ + 0x00000000, /* EMC_ODT_READ */ + 0x0000ba88, /* EMC_FBIO_CFG5 */ + 0xf0070191, /* EMC_CFG_DIG_DLL */ + 0x00008000, /* EMC_CFG_DIG_DLL_PERIOD */ + 0x00000008, /* EMC_DLL_XFORM_DQS4 */ + 0x00000008, /* EMC_DLL_XFORM_DQS5 */ + 0x00000008, /* EMC_DLL_XFORM_DQS6 */ + 0x00000008, /* EMC_DLL_XFORM_DQS7 */ + 0x00000000, /* EMC_DLL_XFORM_QUSE4 */ + 0x00000000, /* EMC_DLL_XFORM_QUSE5 */ + 0x00000000, /* EMC_DLL_XFORM_QUSE6 */ + 0x00000000, /* EMC_DLL_XFORM_QUSE7 */ + 0x00000000, /* EMC_DLI_TRIM_TXDQS4 */ + 0x00000000, /* EMC_DLI_TRIM_TXDQS5 */ + 0x00000000, /* EMC_DLI_TRIM_TXDQS6 */ + 0x00000000, /* EMC_DLI_TRIM_TXDQS7 */ + 0x001112a0, /* EMC_XM2CMDPADCTRL */ + 0x00000000, /* EMC_XM2CMDPADCTRL4 */ + 0x0000013d, /* EMC_XM2DQSPADCTRL2 */ + 0x00000000, /* EMC_XM2DQPADCTRL2 */ + 0x77ffc085, /* EMC_XM2CLKPADCTRL */ + 0x81f1f508, /* EMC_XM2COMPPADCTRL */ + 0x07076604, /* EMC_XM2VTTGENPADCTRL */ + 0x00000000, /* EMC_XM2VTTGENPADCTRL2 */ + 0x0000003f, /* EMC_DSR_VTTGEN_DRV */ + 0x00000000, /* EMC_TXDSRVTTGEN */ + 0x02000000, /* EMC_FBIO_SPARE */ + 0x00000802, /* EMC_CTT_TERM_CTRL */ + 0x00020000, /* EMC_ZCAL_INTERVAL */ + 0x00000100, /* EMC_ZCAL_WAIT_CNT */ + 0x00f8000f, /* EMC_MRS_WAIT_CNT */ + 0x00f8000f, /* EMC_MRS_WAIT_CNT2 */ + 0x00000000, /* EMC_AUTO_CAL_CONFIG2 */ + 0x00000000, /* EMC_AUTO_CAL_CONFIG3 */ + 0x00000000, /* EMC_CTT */ + 0x00000000, /* EMC_CTT_DURATION */ + 0x8000302b, /* EMC_DYN_SELF_REF_CONTROL */ + 0x1f7df7df, /* EMC_CA_TRAINING_TIMING_CNTL1 */ + 0x0000001f, /* EMC_CA_TRAINING_TIMING_CNTL2 */ + 0x0e00000b, /* MC_EMEM_ARB_CFG */ + 0x80000190, /* MC_EMEM_ARB_OUTSTANDING_REQ */ + 0x00000004, /* MC_EMEM_ARB_TIMING_RCD */ + 0x00000005, /* MC_EMEM_ARB_TIMING_RP */ + 0x00000013, /* MC_EMEM_ARB_TIMING_RC */ + 0x0000000c, /* MC_EMEM_ARB_TIMING_RAS */ + 0x0000000f, /* MC_EMEM_ARB_TIMING_FAW */ + 0x00000002, /* MC_EMEM_ARB_TIMING_RRD */ + 0x00000003, /* MC_EMEM_ARB_TIMING_RAP2PRE */ + 0x0000000c, /* MC_EMEM_ARB_TIMING_WAP2PRE */ + 0x00000002, /* MC_EMEM_ARB_TIMING_R2R */ + 0x00000002, /* MC_EMEM_ARB_TIMING_W2W */ + 0x00000006, /* MC_EMEM_ARB_TIMING_R2W */ + 0x00000008, /* MC_EMEM_ARB_TIMING_W2R */ + 0x08060202, /* MC_EMEM_ARB_DA_TURNS */ + 0x00170e13, /* MC_EMEM_ARB_DA_COVERS */ + 0x734c2414, /* MC_EMEM_ARB_MISC0 */ + 0x001f0000, /* MC_EMEM_ARB_RING1_THROTTLE */ + }, + { + 0x00000000, /* EMC_CDB_CNTL_1 */ + 0x00000006, /* EMC_FBIO_CFG6 */ + 0x0000000d, /* EMC_QUSE */ + 0x0000000a, /* EMC_EINPUT */ + 0x00000005, /* EMC_EINPUT_DURATION */ + 0x00000008, /* EMC_DLL_XFORM_DQS0 */ + 0x0000000d, /* EMC_QSAFE */ + 0x00000000, /* EMC_DLL_XFORM_QUSE0 */ + 0x00000015, /* EMC_RDV */ + 0x00249249, /* EMC_XM2DQSPADCTRL4 */ + 0x20820800, /* EMC_XM2DQSPADCTRL3 */ + 0x0000000a, /* EMC_DLL_XFORM_DQ0 */ + 0xa0f10f0f, /* EMC_AUTO_CAL_CONFIG */ + 0x00004000, /* EMC_DLL_XFORM_ADDR0 */ + 0x00000a0a, /* EMC_XM2CLKPADCTRL2 */ + 0x00000000, /* EMC_DLI_TRIM_TXDQS0 */ + 0x00000000, /* EMC_DLL_XFORM_ADDR1 */ + 0x00004000, /* EMC_DLL_XFORM_ADDR2 */ + 0x00000008, /* EMC_DLL_XFORM_DQS1 */ + 0x00000008, /* EMC_DLL_XFORM_DQS2 */ + 0x00000008, /* EMC_DLL_XFORM_DQS3 */ + 0x0000000a, /* EMC_DLL_XFORM_DQ1 */ + 0x0000000c, /* EMC_DLL_XFORM_DQ2 */ + 0x0000000a, /* EMC_DLL_XFORM_DQ3 */ + 0x00000000, /* EMC_DLI_TRIM_TXDQS1 */ + 0x00000000, /* EMC_DLI_TRIM_TXDQS2 */ + 0x00000000, /* EMC_DLI_TRIM_TXDQS3 */ + 0x00000000, /* EMC_DLL_XFORM_QUSE1 */ + 0x00000000, /* EMC_DLL_XFORM_QUSE2 */ + 0x00000000, /* EMC_DLL_XFORM_QUSE3 */ + }, + { + 0x00000000, /* EMC_CDB_CNTL_1 */ + 0x00000006, /* EMC_FBIO_CFG6 */ + 0x0000000d, /* EMC_QUSE */ + 0x0000000a, /* EMC_EINPUT */ + 0x00000005, /* EMC_EINPUT_DURATION */ + 0x00000008, /* EMC_DLL_XFORM_DQS0 */ + 0x0000000d, /* EMC_QSAFE */ + 0x00000000, /* EMC_DLL_XFORM_QUSE0 */ + 0x00000015, /* EMC_RDV */ + 0x00249249, /* EMC_XM2DQSPADCTRL4 */ + 0x20820800, /* EMC_XM2DQSPADCTRL3 */ + 0x0000000a, /* EMC_DLL_XFORM_DQ0 */ + 0xa8f10f0f, /* EMC_AUTO_CAL_CONFIG */ + 0x00004000, /* EMC_DLL_XFORM_ADDR0 */ + 0x00000a0a, /* EMC_XM2CLKPADCTRL2 */ + 0x00000000, /* EMC_DLI_TRIM_TXDQS0 */ + 0x00000000, /* EMC_DLL_XFORM_ADDR1 */ + 0x00004000, /* EMC_DLL_XFORM_ADDR2 */ + 0x00000008, /* EMC_DLL_XFORM_DQS1 */ + 0x00000008, /* EMC_DLL_XFORM_DQS2 */ + 0x00000008, /* EMC_DLL_XFORM_DQS3 */ + 0x0000000a, /* EMC_DLL_XFORM_DQ1 */ + 0x0000000c, /* EMC_DLL_XFORM_DQ2 */ + 0x0000000a, /* EMC_DLL_XFORM_DQ3 */ + 0x00000000, /* EMC_DLI_TRIM_TXDQS1 */ + 0x00000000, /* EMC_DLI_TRIM_TXDQS2 */ + 0x00000000, /* EMC_DLI_TRIM_TXDQS3 */ + 0x00000000, /* EMC_DLL_XFORM_QUSE1 */ + 0x00000000, /* EMC_DLL_XFORM_QUSE2 */ + 0x00000000, /* EMC_DLL_XFORM_QUSE3 */ + }, + { + 0x00000196, /* MC_PTSA_GRANT_DECREMENT */ + 0x00090009, /* MC_LATENCY_ALLOWANCE_G2_0 */ + 0x0009000a, /* MC_LATENCY_ALLOWANCE_G2_1 */ + 0x000b000c, /* MC_LATENCY_ALLOWANCE_NV_0 */ + 0x0000000c, /* MC_LATENCY_ALLOWANCE_NV2_0 */ + 0x000c000c, /* MC_LATENCY_ALLOWANCE_NV_2 */ + 0x0010000c, /* MC_LATENCY_ALLOWANCE_NV_1 */ + 0x00000010, /* MC_LATENCY_ALLOWANCE_NV2_1 */ + 0x00100010, /* MC_LATENCY_ALLOWANCE_NV3 */ + 0x006d0033, /* MC_LATENCY_ALLOWANCE_EPP_0 */ + 0x006d006d, /* MC_LATENCY_ALLOWANCE_EPP_1 */ + }, + 0x00000042, /* EMC_ZCAL_WAIT_CNT after clock change */ + 0x001fffff, /* EMC_AUTO_CAL_INTERVAL */ + 0x53300000, /* EMC_CFG */ + 0x80000d05, /* Mode Register 0 */ + 0x80100002, /* Mode Register 1 */ + 0x80200418, /* Mode Register 2 */ + 0x00000000, /* Mode Register 4 */ + 1200, /* expected dvfs latency (ns) */ + }, + { + 0x41, /* Rev 4.0.3 */ + 900000, /* SDRAM frequency */ + 1200, /* min voltage */ + "pll_m", /* clock source id */ + 0x80000000, /* CLK_SOURCE_EMC */ + 99, /* number of burst_regs */ + 30, /* number of trim_regs (each channel) */ + 11, /* number of up_down_regs */ + { + 0x0000002a, /* EMC_RC */ + 0x000000e9, /* EMC_RFC */ + 0x00000000, /* EMC_RFC_SLR */ + 0x0000001d, /* EMC_RAS */ + 0x0000000b, /* EMC_RP */ + 0x00000008, /* EMC_R2W */ + 0x0000000f, /* EMC_W2R */ + 0x00000005, /* EMC_R2P */ + 0x00000016, /* EMC_W2P */ + 0x0000000b, /* EMC_RD_RCD */ + 0x0000000b, /* EMC_WR_RCD */ + 0x00000004, /* EMC_RRD */ + 0x00000001, /* EMC_REXT */ + 0x00000000, /* EMC_WEXT */ + 0x00000007, /* EMC_WDV */ + 0x0000000f, /* EMC_WDV_MASK */ + 0x0000000d, /* EMC_IBDLY */ + 0x00010000, /* EMC_PUTERM_EXTRA */ + 0x00000000, /* EMC_CDB_CNTL_2 */ + 0x0000000a, /* EMC_QRST */ + 0x00000017, /* EMC_RDV_MASK */ + 0x00001b33, /* EMC_REFRESH */ + 0x00000000, /* EMC_BURST_REFRESH_NUM */ + 0x000006cc, /* EMC_PRE_REFRESH_REQ_CNT */ + 0x00000004, /* EMC_PDEX2WR */ + 0x00000014, /* EMC_PDEX2RD */ + 0x00000001, /* EMC_PCHG2PDEN */ + 0x00000000, /* EMC_ACT2PDEN */ + 0x000000e0, /* EMC_AR2PDEN */ + 0x0000001b, /* EMC_RW2PDEN */ + 0x000000f4, /* EMC_TXSR */ + 0x00000200, /* EMC_TXSRDLL */ + 0x00000006, /* EMC_TCKE */ + 0x00000006, /* EMC_TCKESR */ + 0x00000006, /* EMC_TPD */ + 0x00000025, /* EMC_TFAW */ + 0x00000000, /* EMC_TRPAB */ + 0x00000008, /* EMC_TCLKSTABLE */ + 0x00000009, /* EMC_TCLKSTOP */ + 0x00001b74, /* EMC_TREFBW */ + 0x00000000, /* EMC_QUSE_EXTRA */ + 0x80000000, /* EMC_ODT_WRITE */ + 0x00000000, /* EMC_ODT_READ */ + 0x00005088, /* EMC_FBIO_CFG5 */ + 0xf0040191, /* EMC_CFG_DIG_DLL */ + 0x00008000, /* EMC_CFG_DIG_DLL_PERIOD */ + 0x00000008, /* EMC_DLL_XFORM_DQS4 */ + 0x00000008, /* EMC_DLL_XFORM_DQS5 */ + 0x00000008, /* EMC_DLL_XFORM_DQS6 */ + 0x00000008, /* EMC_DLL_XFORM_DQS7 */ + 0x00018007, /* EMC_DLL_XFORM_QUSE4 */ + 0x00018007, /* EMC_DLL_XFORM_QUSE5 */ + 0x00018007, /* EMC_DLL_XFORM_QUSE6 */ + 0x00018007, /* EMC_DLL_XFORM_QUSE7 */ + 0x00000000, /* EMC_DLI_TRIM_TXDQS4 */ + 0x00000000, /* EMC_DLI_TRIM_TXDQS5 */ + 0x00000000, /* EMC_DLI_TRIM_TXDQS6 */ + 0x00000000, /* EMC_DLI_TRIM_TXDQS7 */ + 0x001112a0, /* EMC_XM2CMDPADCTRL */ + 0x00000000, /* EMC_XM2CMDPADCTRL4 */ + 0x0000013d, /* EMC_XM2DQSPADCTRL2 */ + 0x00000000, /* EMC_XM2DQPADCTRL2 */ + 0x77ffc085, /* EMC_XM2CLKPADCTRL */ + 0x81f1f508, /* EMC_XM2COMPPADCTRL */ + 0x07077504, /* EMC_XM2VTTGENPADCTRL */ + 0x00000000, /* EMC_XM2VTTGENPADCTRL2 */ + 0x0000003f, /* EMC_DSR_VTTGEN_DRV */ + 0x00000000, /* EMC_TXDSRVTTGEN */ + 0x02000000, /* EMC_FBIO_SPARE */ + 0x00000802, /* EMC_CTT_TERM_CTRL */ + 0x00020000, /* EMC_ZCAL_INTERVAL */ + 0x00000120, /* EMC_ZCAL_WAIT_CNT */ + 0x00d5000f, /* EMC_MRS_WAIT_CNT */ + 0x00d5000f, /* EMC_MRS_WAIT_CNT2 */ + 0x00000000, /* EMC_AUTO_CAL_CONFIG2 */ + 0x00000000, /* EMC_AUTO_CAL_CONFIG3 */ + 0x00000000, /* EMC_CTT */ + 0x00000000, /* EMC_CTT_DURATION */ + 0x8000368a, /* EMC_DYN_SELF_REF_CONTROL */ + 0x1f7df7df, /* EMC_CA_TRAINING_TIMING_CNTL1 */ + 0x0000001f, /* EMC_CA_TRAINING_TIMING_CNTL2 */ + 0x0800000d, /* MC_EMEM_ARB_CFG */ + 0x80000190, /* MC_EMEM_ARB_OUTSTANDING_REQ */ + 0x00000005, /* MC_EMEM_ARB_TIMING_RCD */ + 0x00000006, /* MC_EMEM_ARB_TIMING_RP */ + 0x00000015, /* MC_EMEM_ARB_TIMING_RC */ + 0x0000000e, /* MC_EMEM_ARB_TIMING_RAS */ + 0x00000012, /* MC_EMEM_ARB_TIMING_FAW */ + 0x00000002, /* MC_EMEM_ARB_TIMING_RRD */ + 0x00000004, /* MC_EMEM_ARB_TIMING_RAP2PRE */ + 0x0000000e, /* MC_EMEM_ARB_TIMING_WAP2PRE */ + 0x00000002, /* MC_EMEM_ARB_TIMING_R2R */ + 0x00000002, /* MC_EMEM_ARB_TIMING_W2W */ + 0x00000006, /* MC_EMEM_ARB_TIMING_R2W */ + 0x00000009, /* MC_EMEM_ARB_TIMING_W2R */ + 0x09060202, /* MC_EMEM_ARB_DA_TURNS */ + 0x001a1015, /* MC_EMEM_ARB_DA_COVERS */ + 0x734e2916, /* MC_EMEM_ARB_MISC0 */ + 0x001f0000, /* MC_EMEM_ARB_RING1_THROTTLE */ + }, + { + 0x00000000, /* EMC_CDB_CNTL_1 */ + 0x00000006, /* EMC_FBIO_CFG6 */ + 0x0000000c, /* EMC_QUSE */ + 0x0000000a, /* EMC_EINPUT */ + 0x00000006, /* EMC_EINPUT_DURATION */ + 0x00000008, /* EMC_DLL_XFORM_DQS0 */ + 0x0000000d, /* EMC_QSAFE */ + 0x00018007, /* EMC_DLL_XFORM_QUSE0 */ + 0x00000015, /* EMC_RDV */ + 0x00249249, /* EMC_XM2DQSPADCTRL4 */ + 0x20820800, /* EMC_XM2DQSPADCTRL3 */ + 0x00008008, /* EMC_DLL_XFORM_DQ0 */ + 0xa0f10202, /* EMC_AUTO_CAL_CONFIG */ + 0x00000000, /* EMC_DLL_XFORM_ADDR0 */ + 0x00000a0a, /* EMC_XM2CLKPADCTRL2 */ + 0x00000000, /* EMC_DLI_TRIM_TXDQS0 */ + 0x00000000, /* EMC_DLL_XFORM_ADDR1 */ + 0x00000000, /* EMC_DLL_XFORM_ADDR2 */ + 0x00000008, /* EMC_DLL_XFORM_DQS1 */ + 0x00000008, /* EMC_DLL_XFORM_DQS2 */ + 0x00000008, /* EMC_DLL_XFORM_DQS3 */ + 0x00000008, /* EMC_DLL_XFORM_DQ1 */ + 0x00008008, /* EMC_DLL_XFORM_DQ2 */ + 0x00008008, /* EMC_DLL_XFORM_DQ3 */ + 0x00000000, /* EMC_DLI_TRIM_TXDQS1 */ + 0x00000000, /* EMC_DLI_TRIM_TXDQS2 */ + 0x00000000, /* EMC_DLI_TRIM_TXDQS3 */ + 0x00018007, /* EMC_DLL_XFORM_QUSE1 */ + 0x00018007, /* EMC_DLL_XFORM_QUSE2 */ + 0x00018007, /* EMC_DLL_XFORM_QUSE3 */ + }, + { + 0x00000000, /* EMC_CDB_CNTL_1 */ + 0x00000006, /* EMC_FBIO_CFG6 */ + 0x0000000c, /* EMC_QUSE */ + 0x0000000a, /* EMC_EINPUT */ + 0x00000006, /* EMC_EINPUT_DURATION */ + 0x00000008, /* EMC_DLL_XFORM_DQS0 */ + 0x0000000d, /* EMC_QSAFE */ + 0x00018007, /* EMC_DLL_XFORM_QUSE0 */ + 0x00000015, /* EMC_RDV */ + 0x00249249, /* EMC_XM2DQSPADCTRL4 */ + 0x20820800, /* EMC_XM2DQSPADCTRL3 */ + 0x00008008, /* EMC_DLL_XFORM_DQ0 */ + 0xa8f10f0f, /* EMC_AUTO_CAL_CONFIG */ + 0x00000000, /* EMC_DLL_XFORM_ADDR0 */ + 0x00000a0a, /* EMC_XM2CLKPADCTRL2 */ + 0x00000000, /* EMC_DLI_TRIM_TXDQS0 */ + 0x00000000, /* EMC_DLL_XFORM_ADDR1 */ + 0x00000000, /* EMC_DLL_XFORM_ADDR2 */ + 0x00000008, /* EMC_DLL_XFORM_DQS1 */ + 0x00000008, /* EMC_DLL_XFORM_DQS2 */ + 0x00000008, /* EMC_DLL_XFORM_DQS3 */ + 0x00000008, /* EMC_DLL_XFORM_DQ1 */ + 0x00008008, /* EMC_DLL_XFORM_DQ2 */ + 0x00008008, /* EMC_DLL_XFORM_DQ3 */ + 0x00000000, /* EMC_DLI_TRIM_TXDQS1 */ + 0x00000000, /* EMC_DLI_TRIM_TXDQS2 */ + 0x00000000, /* EMC_DLI_TRIM_TXDQS3 */ + 0x00018007, /* EMC_DLL_XFORM_QUSE1 */ + 0x00018007, /* EMC_DLL_XFORM_QUSE2 */ + 0x00018007, /* EMC_DLL_XFORM_QUSE3 */ + }, + { + 0x000001cd, /* MC_PTSA_GRANT_DECREMENT */ + 0x00080008, /* MC_LATENCY_ALLOWANCE_G2_0 */ + 0x00080008, /* MC_LATENCY_ALLOWANCE_G2_1 */ + 0x0009000a, /* MC_LATENCY_ALLOWANCE_NV_0 */ + 0x0000000a, /* MC_LATENCY_ALLOWANCE_NV2_0 */ + 0x000a000a, /* MC_LATENCY_ALLOWANCE_NV_2 */ + 0x000e000a, /* MC_LATENCY_ALLOWANCE_NV_1 */ + 0x0000000e, /* MC_LATENCY_ALLOWANCE_NV2_1 */ + 0x000e000e, /* MC_LATENCY_ALLOWANCE_NV3 */ + 0x0060002d, /* MC_LATENCY_ALLOWANCE_EPP_0 */ + 0x00600060, /* MC_LATENCY_ALLOWANCE_EPP_1 */ + }, + 0x0000004b, /* EMC_ZCAL_WAIT_CNT after clock change */ + 0x001fffff, /* EMC_AUTO_CAL_INTERVAL */ + 0x53000000, /* EMC_CFG */ + 0x80000f15, /* Mode Register 0 */ + 0x80100002, /* Mode Register 1 */ + 0x80200420, /* Mode Register 2 */ + 0x00000000, /* Mode Register 4 */ + 1200, /* expected dvfs latency (ns) */ + }, +}; + + +static struct tegra11_emc_table p2560_h5tc4g63afr_pba_table[] = { + { + 0x41, /* Rev 4.0.3 */ + 12750, /* SDRAM frequency */ + 900, /* min voltage */ + "pll_p", /* clock source id */ + 0x4000003e, /* CLK_SOURCE_EMC */ + 99, /* number of burst_regs */ + 30, /* number of trim_regs (each channel) */ + 11, /* number of up_down_regs */ + { + 0x00000000, /* EMC_RC */ + 0x00000003, /* EMC_RFC */ + 0x00000000, /* EMC_RFC_SLR */ + 0x00000000, /* EMC_RAS */ + 0x00000000, /* EMC_RP */ + 0x00000004, /* EMC_R2W */ + 0x0000000a, /* EMC_W2R */ + 0x00000003, /* EMC_R2P */ + 0x0000000b, /* EMC_W2P */ + 0x00000000, /* EMC_RD_RCD */ + 0x00000000, /* EMC_WR_RCD */ + 0x00000003, /* EMC_RRD */ + 0x00000001, /* EMC_REXT */ + 0x00000000, /* EMC_WEXT */ + 0x00000005, /* EMC_WDV */ + 0x0000000f, /* EMC_WDV_MASK */ + 0x00000005, /* EMC_IBDLY */ + 0x00010000, /* EMC_PUTERM_EXTRA */ + 0x00000000, /* EMC_CDB_CNTL_2 */ + 0x00000004, /* EMC_QRST */ + 0x0000000e, /* EMC_RDV_MASK */ + 0x00000060, /* EMC_REFRESH */ + 0x00000000, /* EMC_BURST_REFRESH_NUM */ + 0x00000018, /* EMC_PRE_REFRESH_REQ_CNT */ + 0x00000002, /* EMC_PDEX2WR */ + 0x00000002, /* EMC_PDEX2RD */ + 0x00000001, /* EMC_PCHG2PDEN */ + 0x00000000, /* EMC_ACT2PDEN */ + 0x00000007, /* EMC_AR2PDEN */ + 0x0000000f, /* EMC_RW2PDEN */ + 0x00000005, /* EMC_TXSR */ + 0x00000005, /* EMC_TXSRDLL */ + 0x00000004, /* EMC_TCKE */ + 0x00000004, /* EMC_TCKESR */ + 0x00000004, /* EMC_TPD */ + 0x00000004, /* EMC_TFAW */ + 0x00000000, /* EMC_TRPAB */ + 0x00000004, /* EMC_TCLKSTABLE */ + 0x00000005, /* EMC_TCLKSTOP */ + 0x00000064, /* EMC_TREFBW */ + 0x00000005, /* EMC_QUSE_EXTRA */ + 0x00000020, /* EMC_ODT_WRITE */ + 0x00000000, /* EMC_ODT_READ */ + 0x0000aa88, /* EMC_FBIO_CFG5 */ + 0x002c00a0, /* EMC_CFG_DIG_DLL */ + 0x00008000, /* EMC_CFG_DIG_DLL_PERIOD */ + 0x00070000, /* EMC_DLL_XFORM_DQS4 */ + 0x00070000, /* EMC_DLL_XFORM_DQS5 */ + 0x00070000, /* EMC_DLL_XFORM_DQS6 */ + 0x00070000, /* EMC_DLL_XFORM_DQS7 */ + 0x00000000, /* EMC_DLL_XFORM_QUSE4 */ + 0x00000000, /* EMC_DLL_XFORM_QUSE5 */ + 0x00000000, /* EMC_DLL_XFORM_QUSE6 */ + 0x00000000, /* EMC_DLL_XFORM_QUSE7 */ + 0x00000000, /* EMC_DLI_TRIM_TXDQS4 */ + 0x00000000, /* EMC_DLI_TRIM_TXDQS5 */ + 0x00000000, /* EMC_DLI_TRIM_TXDQS6 */ + 0x00000000, /* EMC_DLI_TRIM_TXDQS7 */ + 0x001112a0, /* EMC_XM2CMDPADCTRL */ + 0x00000000, /* EMC_XM2CMDPADCTRL4 */ + 0x0000a11c, /* EMC_XM2DQSPADCTRL2 */ + 0x00000000, /* EMC_XM2DQPADCTRL2 */ + 0x77ffc085, /* EMC_XM2CLKPADCTRL */ + 0x81f1f108, /* EMC_XM2COMPPADCTRL */ + 0x03035504, /* EMC_XM2VTTGENPADCTRL */ + 0x0000003f, /* EMC_XM2VTTGENPADCTRL2 */ + 0x0000003f, /* EMC_DSR_VTTGEN_DRV */ + 0x00000000, /* EMC_TXDSRVTTGEN */ + 0x02000000, /* EMC_FBIO_SPARE */ + 0x00000802, /* EMC_CTT_TERM_CTRL */ + 0x00000000, /* EMC_ZCAL_INTERVAL */ + 0x00000042, /* EMC_ZCAL_WAIT_CNT */ + 0x000f000f, /* EMC_MRS_WAIT_CNT */ + 0x000f000f, /* EMC_MRS_WAIT_CNT2 */ + 0x00000000, /* EMC_AUTO_CAL_CONFIG2 */ + 0x00000000, /* EMC_AUTO_CAL_CONFIG3 */ + 0x00000000, /* EMC_CTT */ + 0x00000000, /* EMC_CTT_DURATION */ + 0x800001c5, /* EMC_DYN_SELF_REF_CONTROL */ + 0x1f7df7df, /* EMC_CA_TRAINING_TIMING_CNTL1 */ + 0x0000001f, /* EMC_CA_TRAINING_TIMING_CNTL2 */ + 0x40040001, /* MC_EMEM_ARB_CFG */ + 0x8000003f, /* MC_EMEM_ARB_OUTSTANDING_REQ */ + 0x00000001, /* MC_EMEM_ARB_TIMING_RCD */ + 0x00000001, /* MC_EMEM_ARB_TIMING_RP */ + 0x00000002, /* MC_EMEM_ARB_TIMING_RC */ + 0x00000000, /* MC_EMEM_ARB_TIMING_RAS */ + 0x00000001, /* MC_EMEM_ARB_TIMING_FAW */ + 0x00000001, /* MC_EMEM_ARB_TIMING_RRD */ + 0x00000002, /* MC_EMEM_ARB_TIMING_RAP2PRE */ + 0x00000008, /* MC_EMEM_ARB_TIMING_WAP2PRE */ + 0x00000002, /* MC_EMEM_ARB_TIMING_R2R */ + 0x00000001, /* MC_EMEM_ARB_TIMING_W2W */ + 0x00000003, /* MC_EMEM_ARB_TIMING_R2W */ + 0x00000006, /* MC_EMEM_ARB_TIMING_W2R */ + 0x06030102, /* MC_EMEM_ARB_DA_TURNS */ + 0x000a0402, /* MC_EMEM_ARB_DA_COVERS */ + 0x77e30303, /* MC_EMEM_ARB_MISC0 */ + 0x001f0000, /* MC_EMEM_ARB_RING1_THROTTLE */ + }, + { + 0x00000000, /* EMC_CDB_CNTL_1 */ + 0x00000004, /* EMC_FBIO_CFG6 */ + 0x00000006, /* EMC_QUSE */ + 0x00000003, /* EMC_EINPUT */ 0x00000004, /* EMC_EINPUT_DURATION */ 0x00070000, /* EMC_DLL_XFORM_DQS0 */ 0x0000000a, /* EMC_QSAFE */ 0x00000000, /* EMC_DLL_XFORM_QUSE0 */ 0x0000000c, /* EMC_RDV */ - 0x0079e79e, /* EMC_XM2DQSPADCTRL4 */ + 0x00249249, /* EMC_XM2DQSPADCTRL4 */ 0x20820800, /* EMC_XM2DQSPADCTRL3 */ - 0x00078000, /* EMC_DLL_XFORM_DQ0 */ + 0x00070000, /* EMC_DLL_XFORM_DQ0 */ 0xa0f10000, /* EMC_AUTO_CAL_CONFIG */ 0x00000000, /* EMC_DLL_XFORM_ADDR0 */ - 0x00000909, /* EMC_XM2CLKPADCTRL2 */ + 0x00000a0a, /* EMC_XM2CLKPADCTRL2 */ 0x00000000, /* EMC_DLI_TRIM_TXDQS0 */ 0x00000000, /* EMC_DLL_XFORM_ADDR1 */ 0x00000000, /* EMC_DLL_XFORM_ADDR2 */ 0x00070000, /* EMC_DLL_XFORM_DQS1 */ 0x00070000, /* EMC_DLL_XFORM_DQS2 */ 0x00070000, /* EMC_DLL_XFORM_DQS3 */ - 0x00078000, /* EMC_DLL_XFORM_DQ1 */ - 0x00078000, /* EMC_DLL_XFORM_DQ2 */ - 0x00078000, /* EMC_DLL_XFORM_DQ3 */ + 0x00070000, /* EMC_DLL_XFORM_DQ1 */ + 0x00070000, /* EMC_DLL_XFORM_DQ2 */ + 0x00070000, /* EMC_DLL_XFORM_DQ3 */ 0x00000000, /* EMC_DLI_TRIM_TXDQS1 */ 0x00000000, /* EMC_DLI_TRIM_TXDQS2 */ 0x00000000, /* EMC_DLI_TRIM_TXDQS3 */ @@ -1154,28 +2726,1008 @@ static struct tegra11_emc_table p2454_h5tc4g63afr_pba_table[] = { { 0x00000000, /* EMC_CDB_CNTL_1 */ 0x00000004, /* EMC_FBIO_CFG6 */ - 0x00000007, /* EMC_QUSE */ - 0x00000004, /* EMC_EINPUT */ + 0x00000006, /* EMC_QUSE */ + 0x00000003, /* EMC_EINPUT */ + 0x00000004, /* EMC_EINPUT_DURATION */ + 0x00070000, /* EMC_DLL_XFORM_DQS0 */ + 0x0000000a, /* EMC_QSAFE */ + 0x00000000, /* EMC_DLL_XFORM_QUSE0 */ + 0x0000000c, /* EMC_RDV */ + 0x00249249, /* EMC_XM2DQSPADCTRL4 */ + 0x20820800, /* EMC_XM2DQSPADCTRL3 */ + 0x00070000, /* EMC_DLL_XFORM_DQ0 */ + 0xa8f10000, /* EMC_AUTO_CAL_CONFIG */ + 0x00000000, /* EMC_DLL_XFORM_ADDR0 */ + 0x00000a0a, /* EMC_XM2CLKPADCTRL2 */ + 0x00000000, /* EMC_DLI_TRIM_TXDQS0 */ + 0x00000000, /* EMC_DLL_XFORM_ADDR1 */ + 0x00000000, /* EMC_DLL_XFORM_ADDR2 */ + 0x00070000, /* EMC_DLL_XFORM_DQS1 */ + 0x00070000, /* EMC_DLL_XFORM_DQS2 */ + 0x00070000, /* EMC_DLL_XFORM_DQS3 */ + 0x00070000, /* EMC_DLL_XFORM_DQ1 */ + 0x00070000, /* EMC_DLL_XFORM_DQ2 */ + 0x00070000, /* EMC_DLL_XFORM_DQ3 */ + 0x00000000, /* EMC_DLI_TRIM_TXDQS1 */ + 0x00000000, /* EMC_DLI_TRIM_TXDQS2 */ + 0x00000000, /* EMC_DLI_TRIM_TXDQS3 */ + 0x00000000, /* EMC_DLL_XFORM_QUSE1 */ + 0x00000000, /* EMC_DLL_XFORM_QUSE2 */ + 0x00000000, /* EMC_DLL_XFORM_QUSE3 */ + }, + { + 0x0000000e, /* MC_PTSA_GRANT_DECREMENT */ + 0x00ff00ff, /* MC_LATENCY_ALLOWANCE_G2_0 */ + 0x00ff00ff, /* MC_LATENCY_ALLOWANCE_G2_1 */ + 0x00ff00ff, /* MC_LATENCY_ALLOWANCE_NV_0 */ + 0x000000ff, /* MC_LATENCY_ALLOWANCE_NV2_0 */ + 0x00ff00ff, /* MC_LATENCY_ALLOWANCE_NV_2 */ + 0x00ff00ff, /* MC_LATENCY_ALLOWANCE_NV_1 */ + 0x000000ff, /* MC_LATENCY_ALLOWANCE_NV2_1 */ + 0x00ff00ff, /* MC_LATENCY_ALLOWANCE_NV3 */ + 0x00ff00ff, /* MC_LATENCY_ALLOWANCE_EPP_0 */ + 0x00ff00ff, /* MC_LATENCY_ALLOWANCE_EPP_1 */ + }, + 0x00000042, /* EMC_ZCAL_WAIT_CNT after clock change */ + 0x001fffff, /* EMC_AUTO_CAL_INTERVAL */ + 0x7320000e, /* EMC_CFG */ + 0x80001221, /* Mode Register 0 */ + 0x80100003, /* Mode Register 1 */ + 0x80200008, /* Mode Register 2 */ + 0x00000000, /* Mode Register 4 */ + 57820, /* expected dvfs latency (ns) */ + }, + { + 0x41, /* Rev 4.0.3 */ + 20400, /* SDRAM frequency */ + 900, /* min voltage */ + "pll_p", /* clock source id */ + 0x40000026, /* CLK_SOURCE_EMC */ + 99, /* number of burst_regs */ + 30, /* number of trim_regs (each channel) */ + 11, /* number of up_down_regs */ + { + 0x00000000, /* EMC_RC */ + 0x00000005, /* EMC_RFC */ + 0x00000000, /* EMC_RFC_SLR */ + 0x00000000, /* EMC_RAS */ + 0x00000000, /* EMC_RP */ + 0x00000004, /* EMC_R2W */ + 0x0000000a, /* EMC_W2R */ + 0x00000003, /* EMC_R2P */ + 0x0000000b, /* EMC_W2P */ + 0x00000000, /* EMC_RD_RCD */ + 0x00000000, /* EMC_WR_RCD */ + 0x00000003, /* EMC_RRD */ + 0x00000001, /* EMC_REXT */ + 0x00000000, /* EMC_WEXT */ + 0x00000005, /* EMC_WDV */ + 0x0000000f, /* EMC_WDV_MASK */ + 0x00000005, /* EMC_IBDLY */ + 0x00010000, /* EMC_PUTERM_EXTRA */ + 0x00000000, /* EMC_CDB_CNTL_2 */ + 0x00000004, /* EMC_QRST */ + 0x0000000e, /* EMC_RDV_MASK */ + 0x0000009a, /* EMC_REFRESH */ + 0x00000000, /* EMC_BURST_REFRESH_NUM */ + 0x00000026, /* EMC_PRE_REFRESH_REQ_CNT */ + 0x00000002, /* EMC_PDEX2WR */ + 0x00000002, /* EMC_PDEX2RD */ + 0x00000001, /* EMC_PCHG2PDEN */ + 0x00000000, /* EMC_ACT2PDEN */ + 0x00000007, /* EMC_AR2PDEN */ + 0x0000000f, /* EMC_RW2PDEN */ + 0x00000006, /* EMC_TXSR */ + 0x00000006, /* EMC_TXSRDLL */ + 0x00000004, /* EMC_TCKE */ + 0x00000004, /* EMC_TCKESR */ + 0x00000004, /* EMC_TPD */ + 0x00000004, /* EMC_TFAW */ + 0x00000000, /* EMC_TRPAB */ + 0x00000004, /* EMC_TCLKSTABLE */ + 0x00000005, /* EMC_TCLKSTOP */ + 0x000000a0, /* EMC_TREFBW */ + 0x00000005, /* EMC_QUSE_EXTRA */ + 0x00000020, /* EMC_ODT_WRITE */ + 0x00000000, /* EMC_ODT_READ */ + 0x0000aa88, /* EMC_FBIO_CFG5 */ + 0x002c00a0, /* EMC_CFG_DIG_DLL */ + 0x00008000, /* EMC_CFG_DIG_DLL_PERIOD */ + 0x00070000, /* EMC_DLL_XFORM_DQS4 */ + 0x00070000, /* EMC_DLL_XFORM_DQS5 */ + 0x00070000, /* EMC_DLL_XFORM_DQS6 */ + 0x00070000, /* EMC_DLL_XFORM_DQS7 */ + 0x00000000, /* EMC_DLL_XFORM_QUSE4 */ + 0x00000000, /* EMC_DLL_XFORM_QUSE5 */ + 0x00000000, /* EMC_DLL_XFORM_QUSE6 */ + 0x00000000, /* EMC_DLL_XFORM_QUSE7 */ + 0x00000000, /* EMC_DLI_TRIM_TXDQS4 */ + 0x00000000, /* EMC_DLI_TRIM_TXDQS5 */ + 0x00000000, /* EMC_DLI_TRIM_TXDQS6 */ + 0x00000000, /* EMC_DLI_TRIM_TXDQS7 */ + 0x001112a0, /* EMC_XM2CMDPADCTRL */ + 0x00000000, /* EMC_XM2CMDPADCTRL4 */ + 0x0000a11c, /* EMC_XM2DQSPADCTRL2 */ + 0x00000000, /* EMC_XM2DQPADCTRL2 */ + 0x77ffc085, /* EMC_XM2CLKPADCTRL */ + 0x81f1f108, /* EMC_XM2COMPPADCTRL */ + 0x03035504, /* EMC_XM2VTTGENPADCTRL */ + 0x0000003f, /* EMC_XM2VTTGENPADCTRL2 */ + 0x0000003f, /* EMC_DSR_VTTGEN_DRV */ + 0x00000000, /* EMC_TXDSRVTTGEN */ + 0x02000000, /* EMC_FBIO_SPARE */ + 0x00000802, /* EMC_CTT_TERM_CTRL */ + 0x00000000, /* EMC_ZCAL_INTERVAL */ + 0x00000042, /* EMC_ZCAL_WAIT_CNT */ + 0x000f000f, /* EMC_MRS_WAIT_CNT */ + 0x000f000f, /* EMC_MRS_WAIT_CNT2 */ + 0x00000000, /* EMC_AUTO_CAL_CONFIG2 */ + 0x00000000, /* EMC_AUTO_CAL_CONFIG3 */ + 0x00000000, /* EMC_CTT */ + 0x00000000, /* EMC_CTT_DURATION */ + 0x8000023a, /* EMC_DYN_SELF_REF_CONTROL */ + 0x1f7df7df, /* EMC_CA_TRAINING_TIMING_CNTL1 */ + 0x0000001f, /* EMC_CA_TRAINING_TIMING_CNTL2 */ + 0x40020001, /* MC_EMEM_ARB_CFG */ + 0x80000046, /* MC_EMEM_ARB_OUTSTANDING_REQ */ + 0x00000001, /* MC_EMEM_ARB_TIMING_RCD */ + 0x00000001, /* MC_EMEM_ARB_TIMING_RP */ + 0x00000002, /* MC_EMEM_ARB_TIMING_RC */ + 0x00000000, /* MC_EMEM_ARB_TIMING_RAS */ + 0x00000001, /* MC_EMEM_ARB_TIMING_FAW */ + 0x00000001, /* MC_EMEM_ARB_TIMING_RRD */ + 0x00000002, /* MC_EMEM_ARB_TIMING_RAP2PRE */ + 0x00000008, /* MC_EMEM_ARB_TIMING_WAP2PRE */ + 0x00000002, /* MC_EMEM_ARB_TIMING_R2R */ + 0x00000001, /* MC_EMEM_ARB_TIMING_W2W */ + 0x00000003, /* MC_EMEM_ARB_TIMING_R2W */ + 0x00000006, /* MC_EMEM_ARB_TIMING_W2R */ + 0x06030102, /* MC_EMEM_ARB_DA_TURNS */ + 0x000a0402, /* MC_EMEM_ARB_DA_COVERS */ + 0x76230303, /* MC_EMEM_ARB_MISC0 */ + 0x001f0000, /* MC_EMEM_ARB_RING1_THROTTLE */ + }, + { + 0x00000000, /* EMC_CDB_CNTL_1 */ + 0x00000004, /* EMC_FBIO_CFG6 */ + 0x00000006, /* EMC_QUSE */ + 0x00000003, /* EMC_EINPUT */ + 0x00000004, /* EMC_EINPUT_DURATION */ + 0x00070000, /* EMC_DLL_XFORM_DQS0 */ + 0x0000000a, /* EMC_QSAFE */ + 0x00000000, /* EMC_DLL_XFORM_QUSE0 */ + 0x0000000c, /* EMC_RDV */ + 0x00249249, /* EMC_XM2DQSPADCTRL4 */ + 0x20820800, /* EMC_XM2DQSPADCTRL3 */ + 0x00070000, /* EMC_DLL_XFORM_DQ0 */ + 0xa0f10000, /* EMC_AUTO_CAL_CONFIG */ + 0x00000000, /* EMC_DLL_XFORM_ADDR0 */ + 0x00000a0a, /* EMC_XM2CLKPADCTRL2 */ + 0x00000000, /* EMC_DLI_TRIM_TXDQS0 */ + 0x00000000, /* EMC_DLL_XFORM_ADDR1 */ + 0x00000000, /* EMC_DLL_XFORM_ADDR2 */ + 0x00070000, /* EMC_DLL_XFORM_DQS1 */ + 0x00070000, /* EMC_DLL_XFORM_DQS2 */ + 0x00070000, /* EMC_DLL_XFORM_DQS3 */ + 0x00070000, /* EMC_DLL_XFORM_DQ1 */ + 0x00070000, /* EMC_DLL_XFORM_DQ2 */ + 0x00070000, /* EMC_DLL_XFORM_DQ3 */ + 0x00000000, /* EMC_DLI_TRIM_TXDQS1 */ + 0x00000000, /* EMC_DLI_TRIM_TXDQS2 */ + 0x00000000, /* EMC_DLI_TRIM_TXDQS3 */ + 0x00000000, /* EMC_DLL_XFORM_QUSE1 */ + 0x00000000, /* EMC_DLL_XFORM_QUSE2 */ + 0x00000000, /* EMC_DLL_XFORM_QUSE3 */ + }, + { + 0x00000000, /* EMC_CDB_CNTL_1 */ + 0x00000004, /* EMC_FBIO_CFG6 */ + 0x00000006, /* EMC_QUSE */ + 0x00000003, /* EMC_EINPUT */ + 0x00000004, /* EMC_EINPUT_DURATION */ + 0x00070000, /* EMC_DLL_XFORM_DQS0 */ + 0x0000000a, /* EMC_QSAFE */ + 0x00000000, /* EMC_DLL_XFORM_QUSE0 */ + 0x0000000c, /* EMC_RDV */ + 0x00249249, /* EMC_XM2DQSPADCTRL4 */ + 0x20820800, /* EMC_XM2DQSPADCTRL3 */ + 0x00070000, /* EMC_DLL_XFORM_DQ0 */ + 0xa8f10000, /* EMC_AUTO_CAL_CONFIG */ + 0x00000000, /* EMC_DLL_XFORM_ADDR0 */ + 0x00000a0a, /* EMC_XM2CLKPADCTRL2 */ + 0x00000000, /* EMC_DLI_TRIM_TXDQS0 */ + 0x00000000, /* EMC_DLL_XFORM_ADDR1 */ + 0x00000000, /* EMC_DLL_XFORM_ADDR2 */ + 0x00070000, /* EMC_DLL_XFORM_DQS1 */ + 0x00070000, /* EMC_DLL_XFORM_DQS2 */ + 0x00070000, /* EMC_DLL_XFORM_DQS3 */ + 0x00070000, /* EMC_DLL_XFORM_DQ1 */ + 0x00070000, /* EMC_DLL_XFORM_DQ2 */ + 0x00070000, /* EMC_DLL_XFORM_DQ3 */ + 0x00000000, /* EMC_DLI_TRIM_TXDQS1 */ + 0x00000000, /* EMC_DLI_TRIM_TXDQS2 */ + 0x00000000, /* EMC_DLI_TRIM_TXDQS3 */ + 0x00000000, /* EMC_DLL_XFORM_QUSE1 */ + 0x00000000, /* EMC_DLL_XFORM_QUSE2 */ + 0x00000000, /* EMC_DLL_XFORM_QUSE3 */ + }, + { + 0x00000014, /* MC_PTSA_GRANT_DECREMENT */ + 0x00ff00ff, /* MC_LATENCY_ALLOWANCE_G2_0 */ + 0x00ff00ff, /* MC_LATENCY_ALLOWANCE_G2_1 */ + 0x00ff00ff, /* MC_LATENCY_ALLOWANCE_NV_0 */ + 0x000000ff, /* MC_LATENCY_ALLOWANCE_NV2_0 */ + 0x00ff00ff, /* MC_LATENCY_ALLOWANCE_NV_2 */ + 0x00ff00ff, /* MC_LATENCY_ALLOWANCE_NV_1 */ + 0x000000ff, /* MC_LATENCY_ALLOWANCE_NV2_1 */ + 0x00ff00ff, /* MC_LATENCY_ALLOWANCE_NV3 */ + 0x00ff00ff, /* MC_LATENCY_ALLOWANCE_EPP_0 */ + 0x00ff00ff, /* MC_LATENCY_ALLOWANCE_EPP_1 */ + }, + 0x00000042, /* EMC_ZCAL_WAIT_CNT after clock change */ + 0x001fffff, /* EMC_AUTO_CAL_INTERVAL */ + 0x7320000e, /* EMC_CFG */ + 0x80001221, /* Mode Register 0 */ + 0x80100003, /* Mode Register 1 */ + 0x80200008, /* Mode Register 2 */ + 0x00000000, /* Mode Register 4 */ + 35610, /* expected dvfs latency (ns) */ + }, + { + 0x41, /* Rev 4.0.3 */ + 40800, /* SDRAM frequency */ + 900, /* min voltage */ + "pll_p", /* clock source id */ + 0x40000012, /* CLK_SOURCE_EMC */ + 99, /* number of burst_regs */ + 30, /* number of trim_regs (each channel) */ + 11, /* number of up_down_regs */ + { + 0x00000001, /* EMC_RC */ + 0x0000000a, /* EMC_RFC */ + 0x00000000, /* EMC_RFC_SLR */ + 0x00000001, /* EMC_RAS */ + 0x00000000, /* EMC_RP */ + 0x00000004, /* EMC_R2W */ + 0x0000000a, /* EMC_W2R */ + 0x00000003, /* EMC_R2P */ + 0x0000000b, /* EMC_W2P */ + 0x00000000, /* EMC_RD_RCD */ + 0x00000000, /* EMC_WR_RCD */ + 0x00000003, /* EMC_RRD */ + 0x00000001, /* EMC_REXT */ + 0x00000000, /* EMC_WEXT */ + 0x00000005, /* EMC_WDV */ + 0x0000000f, /* EMC_WDV_MASK */ + 0x00000005, /* EMC_IBDLY */ + 0x00010000, /* EMC_PUTERM_EXTRA */ + 0x00000000, /* EMC_CDB_CNTL_2 */ + 0x00000004, /* EMC_QRST */ + 0x0000000e, /* EMC_RDV_MASK */ + 0x00000134, /* EMC_REFRESH */ + 0x00000000, /* EMC_BURST_REFRESH_NUM */ + 0x0000004d, /* EMC_PRE_REFRESH_REQ_CNT */ + 0x00000002, /* EMC_PDEX2WR */ + 0x00000002, /* EMC_PDEX2RD */ + 0x00000001, /* EMC_PCHG2PDEN */ + 0x00000000, /* EMC_ACT2PDEN */ + 0x00000008, /* EMC_AR2PDEN */ + 0x0000000f, /* EMC_RW2PDEN */ + 0x0000000c, /* EMC_TXSR */ + 0x0000000c, /* EMC_TXSRDLL */ + 0x00000004, /* EMC_TCKE */ + 0x00000004, /* EMC_TCKESR */ + 0x00000004, /* EMC_TPD */ + 0x00000004, /* EMC_TFAW */ + 0x00000000, /* EMC_TRPAB */ + 0x00000004, /* EMC_TCLKSTABLE */ + 0x00000005, /* EMC_TCLKSTOP */ + 0x0000013f, /* EMC_TREFBW */ + 0x00000005, /* EMC_QUSE_EXTRA */ + 0x00000020, /* EMC_ODT_WRITE */ + 0x00000000, /* EMC_ODT_READ */ + 0x0000aa88, /* EMC_FBIO_CFG5 */ + 0x002c00a0, /* EMC_CFG_DIG_DLL */ + 0x00008000, /* EMC_CFG_DIG_DLL_PERIOD */ + 0x00070000, /* EMC_DLL_XFORM_DQS4 */ + 0x00070000, /* EMC_DLL_XFORM_DQS5 */ + 0x00070000, /* EMC_DLL_XFORM_DQS6 */ + 0x00070000, /* EMC_DLL_XFORM_DQS7 */ + 0x00000000, /* EMC_DLL_XFORM_QUSE4 */ + 0x00000000, /* EMC_DLL_XFORM_QUSE5 */ + 0x00000000, /* EMC_DLL_XFORM_QUSE6 */ + 0x00000000, /* EMC_DLL_XFORM_QUSE7 */ + 0x00000000, /* EMC_DLI_TRIM_TXDQS4 */ + 0x00000000, /* EMC_DLI_TRIM_TXDQS5 */ + 0x00000000, /* EMC_DLI_TRIM_TXDQS6 */ + 0x00000000, /* EMC_DLI_TRIM_TXDQS7 */ + 0x001112a0, /* EMC_XM2CMDPADCTRL */ + 0x00000000, /* EMC_XM2CMDPADCTRL4 */ + 0x0000a11c, /* EMC_XM2DQSPADCTRL2 */ + 0x00000000, /* EMC_XM2DQPADCTRL2 */ + 0x77ffc085, /* EMC_XM2CLKPADCTRL */ + 0x81f1f108, /* EMC_XM2COMPPADCTRL */ + 0x03035504, /* EMC_XM2VTTGENPADCTRL */ + 0x0000003f, /* EMC_XM2VTTGENPADCTRL2 */ + 0x0000003f, /* EMC_DSR_VTTGEN_DRV */ + 0x00000000, /* EMC_TXDSRVTTGEN */ + 0x02000000, /* EMC_FBIO_SPARE */ + 0x00000802, /* EMC_CTT_TERM_CTRL */ + 0x00000000, /* EMC_ZCAL_INTERVAL */ + 0x00000042, /* EMC_ZCAL_WAIT_CNT */ + 0x000f000f, /* EMC_MRS_WAIT_CNT */ + 0x000f000f, /* EMC_MRS_WAIT_CNT2 */ + 0x00000000, /* EMC_AUTO_CAL_CONFIG2 */ + 0x00000000, /* EMC_AUTO_CAL_CONFIG3 */ + 0x00000000, /* EMC_CTT */ + 0x00000000, /* EMC_CTT_DURATION */ + 0x80000370, /* EMC_DYN_SELF_REF_CONTROL */ + 0x1f7df7df, /* EMC_CA_TRAINING_TIMING_CNTL1 */ + 0x0000001f, /* EMC_CA_TRAINING_TIMING_CNTL2 */ + 0xa0000001, /* MC_EMEM_ARB_CFG */ + 0x8000005b, /* MC_EMEM_ARB_OUTSTANDING_REQ */ + 0x00000001, /* MC_EMEM_ARB_TIMING_RCD */ + 0x00000001, /* MC_EMEM_ARB_TIMING_RP */ + 0x00000002, /* MC_EMEM_ARB_TIMING_RC */ + 0x00000000, /* MC_EMEM_ARB_TIMING_RAS */ + 0x00000001, /* MC_EMEM_ARB_TIMING_FAW */ + 0x00000001, /* MC_EMEM_ARB_TIMING_RRD */ + 0x00000002, /* MC_EMEM_ARB_TIMING_RAP2PRE */ + 0x00000008, /* MC_EMEM_ARB_TIMING_WAP2PRE */ + 0x00000002, /* MC_EMEM_ARB_TIMING_R2R */ + 0x00000001, /* MC_EMEM_ARB_TIMING_W2W */ + 0x00000003, /* MC_EMEM_ARB_TIMING_R2W */ + 0x00000006, /* MC_EMEM_ARB_TIMING_W2R */ + 0x06030102, /* MC_EMEM_ARB_DA_TURNS */ + 0x000a0402, /* MC_EMEM_ARB_DA_COVERS */ + 0x74a30303, /* MC_EMEM_ARB_MISC0 */ + 0x001f0000, /* MC_EMEM_ARB_RING1_THROTTLE */ + }, + { + 0x00000000, /* EMC_CDB_CNTL_1 */ + 0x00000004, /* EMC_FBIO_CFG6 */ + 0x00000006, /* EMC_QUSE */ + 0x00000003, /* EMC_EINPUT */ + 0x00000004, /* EMC_EINPUT_DURATION */ + 0x00070000, /* EMC_DLL_XFORM_DQS0 */ + 0x0000000a, /* EMC_QSAFE */ + 0x00000000, /* EMC_DLL_XFORM_QUSE0 */ + 0x0000000c, /* EMC_RDV */ + 0x00249249, /* EMC_XM2DQSPADCTRL4 */ + 0x20820800, /* EMC_XM2DQSPADCTRL3 */ + 0x00070000, /* EMC_DLL_XFORM_DQ0 */ + 0xa0f10000, /* EMC_AUTO_CAL_CONFIG */ + 0x00000000, /* EMC_DLL_XFORM_ADDR0 */ + 0x00000a0a, /* EMC_XM2CLKPADCTRL2 */ + 0x00000000, /* EMC_DLI_TRIM_TXDQS0 */ + 0x00000000, /* EMC_DLL_XFORM_ADDR1 */ + 0x00000000, /* EMC_DLL_XFORM_ADDR2 */ + 0x00070000, /* EMC_DLL_XFORM_DQS1 */ + 0x00070000, /* EMC_DLL_XFORM_DQS2 */ + 0x00070000, /* EMC_DLL_XFORM_DQS3 */ + 0x00070000, /* EMC_DLL_XFORM_DQ1 */ + 0x00070000, /* EMC_DLL_XFORM_DQ2 */ + 0x00070000, /* EMC_DLL_XFORM_DQ3 */ + 0x00000000, /* EMC_DLI_TRIM_TXDQS1 */ + 0x00000000, /* EMC_DLI_TRIM_TXDQS2 */ + 0x00000000, /* EMC_DLI_TRIM_TXDQS3 */ + 0x00000000, /* EMC_DLL_XFORM_QUSE1 */ + 0x00000000, /* EMC_DLL_XFORM_QUSE2 */ + 0x00000000, /* EMC_DLL_XFORM_QUSE3 */ + }, + { + 0x00000000, /* EMC_CDB_CNTL_1 */ + 0x00000004, /* EMC_FBIO_CFG6 */ + 0x00000006, /* EMC_QUSE */ + 0x00000003, /* EMC_EINPUT */ + 0x00000004, /* EMC_EINPUT_DURATION */ + 0x00070000, /* EMC_DLL_XFORM_DQS0 */ + 0x0000000a, /* EMC_QSAFE */ + 0x00000000, /* EMC_DLL_XFORM_QUSE0 */ + 0x0000000c, /* EMC_RDV */ + 0x00249249, /* EMC_XM2DQSPADCTRL4 */ + 0x20820800, /* EMC_XM2DQSPADCTRL3 */ + 0x00070000, /* EMC_DLL_XFORM_DQ0 */ + 0xa8f10000, /* EMC_AUTO_CAL_CONFIG */ + 0x00000000, /* EMC_DLL_XFORM_ADDR0 */ + 0x00000a0a, /* EMC_XM2CLKPADCTRL2 */ + 0x00000000, /* EMC_DLI_TRIM_TXDQS0 */ + 0x00000000, /* EMC_DLL_XFORM_ADDR1 */ + 0x00000000, /* EMC_DLL_XFORM_ADDR2 */ + 0x00070000, /* EMC_DLL_XFORM_DQS1 */ + 0x00070000, /* EMC_DLL_XFORM_DQS2 */ + 0x00070000, /* EMC_DLL_XFORM_DQS3 */ + 0x00070000, /* EMC_DLL_XFORM_DQ1 */ + 0x00070000, /* EMC_DLL_XFORM_DQ2 */ + 0x00070000, /* EMC_DLL_XFORM_DQ3 */ + 0x00000000, /* EMC_DLI_TRIM_TXDQS1 */ + 0x00000000, /* EMC_DLI_TRIM_TXDQS2 */ + 0x00000000, /* EMC_DLI_TRIM_TXDQS3 */ + 0x00000000, /* EMC_DLL_XFORM_QUSE1 */ + 0x00000000, /* EMC_DLL_XFORM_QUSE2 */ + 0x00000000, /* EMC_DLL_XFORM_QUSE3 */ + }, + { + 0x0000002a, /* MC_PTSA_GRANT_DECREMENT */ + 0x00b000b0, /* MC_LATENCY_ALLOWANCE_G2_0 */ + 0x00b000c4, /* MC_LATENCY_ALLOWANCE_G2_1 */ + 0x00d700eb, /* MC_LATENCY_ALLOWANCE_NV_0 */ + 0x000000eb, /* MC_LATENCY_ALLOWANCE_NV2_0 */ + 0x00eb00eb, /* MC_LATENCY_ALLOWANCE_NV_2 */ + 0x00ff00eb, /* MC_LATENCY_ALLOWANCE_NV_1 */ + 0x000000ff, /* MC_LATENCY_ALLOWANCE_NV2_1 */ + 0x00ff00ff, /* MC_LATENCY_ALLOWANCE_NV3 */ + 0x00ff00ff, /* MC_LATENCY_ALLOWANCE_EPP_0 */ + 0x00ff00ff, /* MC_LATENCY_ALLOWANCE_EPP_1 */ + }, + 0x00000042, /* EMC_ZCAL_WAIT_CNT after clock change */ + 0x001fffff, /* EMC_AUTO_CAL_INTERVAL */ + 0x7320000e, /* EMC_CFG */ + 0x80001221, /* Mode Register 0 */ + 0x80100003, /* Mode Register 1 */ + 0x80200008, /* Mode Register 2 */ + 0x00000000, /* Mode Register 4 */ + 20850, /* expected dvfs latency (ns) */ + }, + { + 0x41, /* Rev 4.0.3 */ + 68000, /* SDRAM frequency */ + 900, /* min voltage */ + "pll_p", /* clock source id */ + 0x4000000a, /* CLK_SOURCE_EMC */ + 99, /* number of burst_regs */ + 30, /* number of trim_regs (each channel) */ + 11, /* number of up_down_regs */ + { + 0x00000003, /* EMC_RC */ + 0x00000011, /* EMC_RFC */ + 0x00000000, /* EMC_RFC_SLR */ + 0x00000002, /* EMC_RAS */ + 0x00000000, /* EMC_RP */ + 0x00000004, /* EMC_R2W */ + 0x0000000a, /* EMC_W2R */ + 0x00000003, /* EMC_R2P */ + 0x0000000b, /* EMC_W2P */ + 0x00000000, /* EMC_RD_RCD */ + 0x00000000, /* EMC_WR_RCD */ + 0x00000003, /* EMC_RRD */ + 0x00000001, /* EMC_REXT */ + 0x00000000, /* EMC_WEXT */ + 0x00000005, /* EMC_WDV */ + 0x0000000f, /* EMC_WDV_MASK */ + 0x00000005, /* EMC_IBDLY */ + 0x00010000, /* EMC_PUTERM_EXTRA */ + 0x00000000, /* EMC_CDB_CNTL_2 */ + 0x00000004, /* EMC_QRST */ + 0x0000000e, /* EMC_RDV_MASK */ + 0x00000202, /* EMC_REFRESH */ + 0x00000000, /* EMC_BURST_REFRESH_NUM */ + 0x00000080, /* EMC_PRE_REFRESH_REQ_CNT */ + 0x00000002, /* EMC_PDEX2WR */ + 0x00000002, /* EMC_PDEX2RD */ + 0x00000001, /* EMC_PCHG2PDEN */ + 0x00000000, /* EMC_ACT2PDEN */ + 0x0000000f, /* EMC_AR2PDEN */ + 0x0000000f, /* EMC_RW2PDEN */ + 0x00000013, /* EMC_TXSR */ + 0x00000013, /* EMC_TXSRDLL */ + 0x00000004, /* EMC_TCKE */ + 0x00000004, /* EMC_TCKESR */ + 0x00000004, /* EMC_TPD */ + 0x00000004, /* EMC_TFAW */ + 0x00000000, /* EMC_TRPAB */ + 0x00000004, /* EMC_TCLKSTABLE */ + 0x00000005, /* EMC_TCLKSTOP */ + 0x00000213, /* EMC_TREFBW */ + 0x00000005, /* EMC_QUSE_EXTRA */ + 0x00000020, /* EMC_ODT_WRITE */ + 0x00000000, /* EMC_ODT_READ */ + 0x0000aa88, /* EMC_FBIO_CFG5 */ + 0x002c00a0, /* EMC_CFG_DIG_DLL */ + 0x00008000, /* EMC_CFG_DIG_DLL_PERIOD */ + 0x00070000, /* EMC_DLL_XFORM_DQS4 */ + 0x00070000, /* EMC_DLL_XFORM_DQS5 */ + 0x00070000, /* EMC_DLL_XFORM_DQS6 */ + 0x00070000, /* EMC_DLL_XFORM_DQS7 */ + 0x00000000, /* EMC_DLL_XFORM_QUSE4 */ + 0x00000000, /* EMC_DLL_XFORM_QUSE5 */ + 0x00000000, /* EMC_DLL_XFORM_QUSE6 */ + 0x00000000, /* EMC_DLL_XFORM_QUSE7 */ + 0x00000000, /* EMC_DLI_TRIM_TXDQS4 */ + 0x00000000, /* EMC_DLI_TRIM_TXDQS5 */ + 0x00000000, /* EMC_DLI_TRIM_TXDQS6 */ + 0x00000000, /* EMC_DLI_TRIM_TXDQS7 */ + 0x001112a0, /* EMC_XM2CMDPADCTRL */ + 0x00000000, /* EMC_XM2CMDPADCTRL4 */ + 0x0000a11c, /* EMC_XM2DQSPADCTRL2 */ + 0x00000000, /* EMC_XM2DQPADCTRL2 */ + 0x77ffc085, /* EMC_XM2CLKPADCTRL */ + 0x81f1f108, /* EMC_XM2COMPPADCTRL */ + 0x03035504, /* EMC_XM2VTTGENPADCTRL */ + 0x0000003f, /* EMC_XM2VTTGENPADCTRL2 */ + 0x0000003f, /* EMC_DSR_VTTGEN_DRV */ + 0x00000000, /* EMC_TXDSRVTTGEN */ + 0x02000000, /* EMC_FBIO_SPARE */ + 0x00000802, /* EMC_CTT_TERM_CTRL */ + 0x00000000, /* EMC_ZCAL_INTERVAL */ + 0x00000042, /* EMC_ZCAL_WAIT_CNT */ + 0x000f000f, /* EMC_MRS_WAIT_CNT */ + 0x000f000f, /* EMC_MRS_WAIT_CNT2 */ + 0x00000000, /* EMC_AUTO_CAL_CONFIG2 */ + 0x00000000, /* EMC_AUTO_CAL_CONFIG3 */ + 0x00000000, /* EMC_CTT */ + 0x00000000, /* EMC_CTT_DURATION */ + 0x8000050d, /* EMC_DYN_SELF_REF_CONTROL */ + 0x1f7df7df, /* EMC_CA_TRAINING_TIMING_CNTL1 */ + 0x0000001f, /* EMC_CA_TRAINING_TIMING_CNTL2 */ + 0x00000001, /* MC_EMEM_ARB_CFG */ + 0x80000076, /* MC_EMEM_ARB_OUTSTANDING_REQ */ + 0x00000001, /* MC_EMEM_ARB_TIMING_RCD */ + 0x00000001, /* MC_EMEM_ARB_TIMING_RP */ + 0x00000002, /* MC_EMEM_ARB_TIMING_RC */ + 0x00000000, /* MC_EMEM_ARB_TIMING_RAS */ + 0x00000001, /* MC_EMEM_ARB_TIMING_FAW */ + 0x00000001, /* MC_EMEM_ARB_TIMING_RRD */ + 0x00000002, /* MC_EMEM_ARB_TIMING_RAP2PRE */ + 0x00000008, /* MC_EMEM_ARB_TIMING_WAP2PRE */ + 0x00000002, /* MC_EMEM_ARB_TIMING_R2R */ + 0x00000001, /* MC_EMEM_ARB_TIMING_W2W */ + 0x00000003, /* MC_EMEM_ARB_TIMING_R2W */ + 0x00000006, /* MC_EMEM_ARB_TIMING_W2R */ + 0x06030102, /* MC_EMEM_ARB_DA_TURNS */ + 0x000a0402, /* MC_EMEM_ARB_DA_COVERS */ + 0x74230403, /* MC_EMEM_ARB_MISC0 */ + 0x001f0000, /* MC_EMEM_ARB_RING1_THROTTLE */ + }, + { + 0x00000000, /* EMC_CDB_CNTL_1 */ + 0x00000004, /* EMC_FBIO_CFG6 */ + 0x00000006, /* EMC_QUSE */ + 0x00000003, /* EMC_EINPUT */ + 0x00000004, /* EMC_EINPUT_DURATION */ + 0x00070000, /* EMC_DLL_XFORM_DQS0 */ + 0x0000000a, /* EMC_QSAFE */ + 0x00000000, /* EMC_DLL_XFORM_QUSE0 */ + 0x0000000c, /* EMC_RDV */ + 0x00249249, /* EMC_XM2DQSPADCTRL4 */ + 0x20820800, /* EMC_XM2DQSPADCTRL3 */ + 0x00070000, /* EMC_DLL_XFORM_DQ0 */ + 0xa0f10000, /* EMC_AUTO_CAL_CONFIG */ + 0x00000000, /* EMC_DLL_XFORM_ADDR0 */ + 0x00001e1e, /* EMC_XM2CLKPADCTRL2 */ + 0x00000000, /* EMC_DLI_TRIM_TXDQS0 */ + 0x00000000, /* EMC_DLL_XFORM_ADDR1 */ + 0x00000000, /* EMC_DLL_XFORM_ADDR2 */ + 0x00070000, /* EMC_DLL_XFORM_DQS1 */ + 0x00070000, /* EMC_DLL_XFORM_DQS2 */ + 0x00070000, /* EMC_DLL_XFORM_DQS3 */ + 0x00070000, /* EMC_DLL_XFORM_DQ1 */ + 0x00070000, /* EMC_DLL_XFORM_DQ2 */ + 0x00070000, /* EMC_DLL_XFORM_DQ3 */ + 0x00000000, /* EMC_DLI_TRIM_TXDQS1 */ + 0x00000000, /* EMC_DLI_TRIM_TXDQS2 */ + 0x00000000, /* EMC_DLI_TRIM_TXDQS3 */ + 0x00000000, /* EMC_DLL_XFORM_QUSE1 */ + 0x00000000, /* EMC_DLL_XFORM_QUSE2 */ + 0x00000000, /* EMC_DLL_XFORM_QUSE3 */ + }, + { + 0x00000000, /* EMC_CDB_CNTL_1 */ + 0x00000004, /* EMC_FBIO_CFG6 */ + 0x00000006, /* EMC_QUSE */ + 0x00000003, /* EMC_EINPUT */ 0x00000004, /* EMC_EINPUT_DURATION */ 0x00070000, /* EMC_DLL_XFORM_DQS0 */ 0x0000000a, /* EMC_QSAFE */ 0x00000000, /* EMC_DLL_XFORM_QUSE0 */ 0x0000000c, /* EMC_RDV */ - 0x0079e79e, /* EMC_XM2DQSPADCTRL4 */ + 0x00249249, /* EMC_XM2DQSPADCTRL4 */ 0x20820800, /* EMC_XM2DQSPADCTRL3 */ - 0x00078000, /* EMC_DLL_XFORM_DQ0 */ + 0x00070000, /* EMC_DLL_XFORM_DQ0 */ 0xa8f10000, /* EMC_AUTO_CAL_CONFIG */ 0x00000000, /* EMC_DLL_XFORM_ADDR0 */ - 0x00000909, /* EMC_XM2CLKPADCTRL2 */ + 0x00001e1e, /* EMC_XM2CLKPADCTRL2 */ 0x00000000, /* EMC_DLI_TRIM_TXDQS0 */ 0x00000000, /* EMC_DLL_XFORM_ADDR1 */ 0x00000000, /* EMC_DLL_XFORM_ADDR2 */ 0x00070000, /* EMC_DLL_XFORM_DQS1 */ 0x00070000, /* EMC_DLL_XFORM_DQS2 */ 0x00070000, /* EMC_DLL_XFORM_DQS3 */ - 0x00078000, /* EMC_DLL_XFORM_DQ1 */ - 0x00078000, /* EMC_DLL_XFORM_DQ2 */ - 0x00078000, /* EMC_DLL_XFORM_DQ3 */ + 0x00070000, /* EMC_DLL_XFORM_DQ1 */ + 0x00070000, /* EMC_DLL_XFORM_DQ2 */ + 0x00070000, /* EMC_DLL_XFORM_DQ3 */ + 0x00000000, /* EMC_DLI_TRIM_TXDQS1 */ + 0x00000000, /* EMC_DLI_TRIM_TXDQS2 */ + 0x00000000, /* EMC_DLI_TRIM_TXDQS3 */ + 0x00000000, /* EMC_DLL_XFORM_QUSE1 */ + 0x00000000, /* EMC_DLL_XFORM_QUSE2 */ + 0x00000000, /* EMC_DLL_XFORM_QUSE3 */ + }, + { + 0x00000046, /* MC_PTSA_GRANT_DECREMENT */ + 0x00690069, /* MC_LATENCY_ALLOWANCE_G2_0 */ + 0x00690075, /* MC_LATENCY_ALLOWANCE_G2_1 */ + 0x0081008d, /* MC_LATENCY_ALLOWANCE_NV_0 */ + 0x0000008d, /* MC_LATENCY_ALLOWANCE_NV2_0 */ + 0x008d008d, /* MC_LATENCY_ALLOWANCE_NV_2 */ + 0x00bc008d, /* MC_LATENCY_ALLOWANCE_NV_1 */ + 0x000000bc, /* MC_LATENCY_ALLOWANCE_NV2_1 */ + 0x00bc00bc, /* MC_LATENCY_ALLOWANCE_NV3 */ + 0x00ff00ff, /* MC_LATENCY_ALLOWANCE_EPP_0 */ + 0x00ff00ff, /* MC_LATENCY_ALLOWANCE_EPP_1 */ + }, + 0x00000042, /* EMC_ZCAL_WAIT_CNT after clock change */ + 0x001fffff, /* EMC_AUTO_CAL_INTERVAL */ + 0x7320000e, /* EMC_CFG */ + 0x80001221, /* Mode Register 0 */ + 0x80100003, /* Mode Register 1 */ + 0x80200008, /* Mode Register 2 */ + 0x00000000, /* Mode Register 4 */ + 10720, /* expected dvfs latency (ns) */ + }, + { + 0x41, /* Rev 4.0.3 */ + 102000, /* SDRAM frequency */ + 900, /* min voltage */ + "pll_p", /* clock source id */ + 0x40000006, /* CLK_SOURCE_EMC */ + 99, /* number of burst_regs */ + 30, /* number of trim_regs (each channel) */ + 11, /* number of up_down_regs */ + { + 0x00000004, /* EMC_RC */ + 0x0000001a, /* EMC_RFC */ + 0x00000000, /* EMC_RFC_SLR */ + 0x00000003, /* EMC_RAS */ + 0x00000001, /* EMC_RP */ + 0x00000004, /* EMC_R2W */ + 0x0000000a, /* EMC_W2R */ + 0x00000003, /* EMC_R2P */ + 0x0000000b, /* EMC_W2P */ + 0x00000001, /* EMC_RD_RCD */ + 0x00000001, /* EMC_WR_RCD */ + 0x00000003, /* EMC_RRD */ + 0x00000001, /* EMC_REXT */ + 0x00000000, /* EMC_WEXT */ + 0x00000005, /* EMC_WDV */ + 0x0000000f, /* EMC_WDV_MASK */ + 0x00000005, /* EMC_IBDLY */ + 0x00010000, /* EMC_PUTERM_EXTRA */ + 0x00000000, /* EMC_CDB_CNTL_2 */ + 0x00000004, /* EMC_QRST */ + 0x0000000e, /* EMC_RDV_MASK */ + 0x00000303, /* EMC_REFRESH */ + 0x00000000, /* EMC_BURST_REFRESH_NUM */ + 0x000000c0, /* EMC_PRE_REFRESH_REQ_CNT */ + 0x00000002, /* EMC_PDEX2WR */ + 0x00000002, /* EMC_PDEX2RD */ + 0x00000001, /* EMC_PCHG2PDEN */ + 0x00000000, /* EMC_ACT2PDEN */ + 0x00000018, /* EMC_AR2PDEN */ + 0x0000000f, /* EMC_RW2PDEN */ + 0x0000001c, /* EMC_TXSR */ + 0x0000001c, /* EMC_TXSRDLL */ + 0x00000004, /* EMC_TCKE */ + 0x00000004, /* EMC_TCKESR */ + 0x00000004, /* EMC_TPD */ + 0x00000005, /* EMC_TFAW */ + 0x00000000, /* EMC_TRPAB */ + 0x00000004, /* EMC_TCLKSTABLE */ + 0x00000005, /* EMC_TCLKSTOP */ + 0x0000031c, /* EMC_TREFBW */ + 0x00000005, /* EMC_QUSE_EXTRA */ + 0x00000020, /* EMC_ODT_WRITE */ + 0x00000000, /* EMC_ODT_READ */ + 0x0000aa88, /* EMC_FBIO_CFG5 */ + 0x002c00a0, /* EMC_CFG_DIG_DLL */ + 0x00008000, /* EMC_CFG_DIG_DLL_PERIOD */ + 0x00070000, /* EMC_DLL_XFORM_DQS4 */ + 0x00070000, /* EMC_DLL_XFORM_DQS5 */ + 0x00070000, /* EMC_DLL_XFORM_DQS6 */ + 0x00070000, /* EMC_DLL_XFORM_DQS7 */ + 0x00000000, /* EMC_DLL_XFORM_QUSE4 */ + 0x00000000, /* EMC_DLL_XFORM_QUSE5 */ + 0x00000000, /* EMC_DLL_XFORM_QUSE6 */ + 0x00000000, /* EMC_DLL_XFORM_QUSE7 */ + 0x00000000, /* EMC_DLI_TRIM_TXDQS4 */ + 0x00000000, /* EMC_DLI_TRIM_TXDQS5 */ + 0x00000000, /* EMC_DLI_TRIM_TXDQS6 */ + 0x00000000, /* EMC_DLI_TRIM_TXDQS7 */ + 0x001112a0, /* EMC_XM2CMDPADCTRL */ + 0x00000000, /* EMC_XM2CMDPADCTRL4 */ + 0x0000a11c, /* EMC_XM2DQSPADCTRL2 */ + 0x00000000, /* EMC_XM2DQPADCTRL2 */ + 0x77ffc085, /* EMC_XM2CLKPADCTRL */ + 0x81f1f108, /* EMC_XM2COMPPADCTRL */ + 0x03035504, /* EMC_XM2VTTGENPADCTRL */ + 0x0000003f, /* EMC_XM2VTTGENPADCTRL2 */ + 0x0000003f, /* EMC_DSR_VTTGEN_DRV */ + 0x00000000, /* EMC_TXDSRVTTGEN */ + 0x02000000, /* EMC_FBIO_SPARE */ + 0x00000802, /* EMC_CTT_TERM_CTRL */ + 0x00000000, /* EMC_ZCAL_INTERVAL */ + 0x00000042, /* EMC_ZCAL_WAIT_CNT */ + 0x000f000f, /* EMC_MRS_WAIT_CNT */ + 0x000f000f, /* EMC_MRS_WAIT_CNT2 */ + 0x00000000, /* EMC_AUTO_CAL_CONFIG2 */ + 0x00000000, /* EMC_AUTO_CAL_CONFIG3 */ + 0x00000000, /* EMC_CTT */ + 0x00000000, /* EMC_CTT_DURATION */ + 0x80000714, /* EMC_DYN_SELF_REF_CONTROL */ + 0x1f7df7df, /* EMC_CA_TRAINING_TIMING_CNTL1 */ + 0x0000001f, /* EMC_CA_TRAINING_TIMING_CNTL2 */ + 0x08000001, /* MC_EMEM_ARB_CFG */ + 0x80000098, /* MC_EMEM_ARB_OUTSTANDING_REQ */ + 0x00000001, /* MC_EMEM_ARB_TIMING_RCD */ + 0x00000001, /* MC_EMEM_ARB_TIMING_RP */ + 0x00000003, /* MC_EMEM_ARB_TIMING_RC */ + 0x00000000, /* MC_EMEM_ARB_TIMING_RAS */ + 0x00000002, /* MC_EMEM_ARB_TIMING_FAW */ + 0x00000001, /* MC_EMEM_ARB_TIMING_RRD */ + 0x00000002, /* MC_EMEM_ARB_TIMING_RAP2PRE */ + 0x00000008, /* MC_EMEM_ARB_TIMING_WAP2PRE */ + 0x00000002, /* MC_EMEM_ARB_TIMING_R2R */ + 0x00000001, /* MC_EMEM_ARB_TIMING_W2W */ + 0x00000003, /* MC_EMEM_ARB_TIMING_R2W */ + 0x00000006, /* MC_EMEM_ARB_TIMING_W2R */ + 0x06030102, /* MC_EMEM_ARB_DA_TURNS */ + 0x000a0403, /* MC_EMEM_ARB_DA_COVERS */ + 0x73c30504, /* MC_EMEM_ARB_MISC0 */ + 0x001f0000, /* MC_EMEM_ARB_RING1_THROTTLE */ + }, + { + 0x00000000, /* EMC_CDB_CNTL_1 */ + 0x00000006, /* EMC_FBIO_CFG6 */ + 0x00000006, /* EMC_QUSE */ + 0x00000005, /* EMC_EINPUT */ + 0x00000004, /* EMC_EINPUT_DURATION */ + 0x00070000, /* EMC_DLL_XFORM_DQS0 */ + 0x0000000a, /* EMC_QSAFE */ + 0x00000000, /* EMC_DLL_XFORM_QUSE0 */ + 0x0000000c, /* EMC_RDV */ + 0x00249249, /* EMC_XM2DQSPADCTRL4 */ + 0x20820800, /* EMC_XM2DQSPADCTRL3 */ + 0x00070000, /* EMC_DLL_XFORM_DQ0 */ + 0xa0f10000, /* EMC_AUTO_CAL_CONFIG */ + 0x00000000, /* EMC_DLL_XFORM_ADDR0 */ + 0x00000a0a, /* EMC_XM2CLKPADCTRL2 */ + 0x00000000, /* EMC_DLI_TRIM_TXDQS0 */ + 0x00000000, /* EMC_DLL_XFORM_ADDR1 */ + 0x00000000, /* EMC_DLL_XFORM_ADDR2 */ + 0x00070000, /* EMC_DLL_XFORM_DQS1 */ + 0x00070000, /* EMC_DLL_XFORM_DQS2 */ + 0x00070000, /* EMC_DLL_XFORM_DQS3 */ + 0x00070000, /* EMC_DLL_XFORM_DQ1 */ + 0x00070000, /* EMC_DLL_XFORM_DQ2 */ + 0x00070000, /* EMC_DLL_XFORM_DQ3 */ + 0x00000000, /* EMC_DLI_TRIM_TXDQS1 */ + 0x00000000, /* EMC_DLI_TRIM_TXDQS2 */ + 0x00000000, /* EMC_DLI_TRIM_TXDQS3 */ + 0x00000000, /* EMC_DLL_XFORM_QUSE1 */ + 0x00000000, /* EMC_DLL_XFORM_QUSE2 */ + 0x00000000, /* EMC_DLL_XFORM_QUSE3 */ + }, + { + 0x00000000, /* EMC_CDB_CNTL_1 */ + 0x00000006, /* EMC_FBIO_CFG6 */ + 0x00000006, /* EMC_QUSE */ + 0x00000005, /* EMC_EINPUT */ + 0x00000004, /* EMC_EINPUT_DURATION */ + 0x00070000, /* EMC_DLL_XFORM_DQS0 */ + 0x0000000a, /* EMC_QSAFE */ + 0x00000000, /* EMC_DLL_XFORM_QUSE0 */ + 0x0000000c, /* EMC_RDV */ + 0x00249249, /* EMC_XM2DQSPADCTRL4 */ + 0x20820800, /* EMC_XM2DQSPADCTRL3 */ + 0x00070000, /* EMC_DLL_XFORM_DQ0 */ + 0xa8f10000, /* EMC_AUTO_CAL_CONFIG */ + 0x00000000, /* EMC_DLL_XFORM_ADDR0 */ + 0x00000a0a, /* EMC_XM2CLKPADCTRL2 */ + 0x00000000, /* EMC_DLI_TRIM_TXDQS0 */ + 0x00000000, /* EMC_DLL_XFORM_ADDR1 */ + 0x00000000, /* EMC_DLL_XFORM_ADDR2 */ + 0x00070000, /* EMC_DLL_XFORM_DQS1 */ + 0x00070000, /* EMC_DLL_XFORM_DQS2 */ + 0x00070000, /* EMC_DLL_XFORM_DQS3 */ + 0x00070000, /* EMC_DLL_XFORM_DQ1 */ + 0x00070000, /* EMC_DLL_XFORM_DQ2 */ + 0x00070000, /* EMC_DLL_XFORM_DQ3 */ + 0x00000000, /* EMC_DLI_TRIM_TXDQS1 */ + 0x00000000, /* EMC_DLI_TRIM_TXDQS2 */ + 0x00000000, /* EMC_DLI_TRIM_TXDQS3 */ + 0x00000000, /* EMC_DLL_XFORM_QUSE1 */ + 0x00000000, /* EMC_DLL_XFORM_QUSE2 */ + 0x00000000, /* EMC_DLL_XFORM_QUSE3 */ + }, + { + 0x00000068, /* MC_PTSA_GRANT_DECREMENT */ + 0x00460046, /* MC_LATENCY_ALLOWANCE_G2_0 */ + 0x0046004e, /* MC_LATENCY_ALLOWANCE_G2_1 */ + 0x0056005e, /* MC_LATENCY_ALLOWANCE_NV_0 */ + 0x0000005e, /* MC_LATENCY_ALLOWANCE_NV2_0 */ + 0x005e005e, /* MC_LATENCY_ALLOWANCE_NV_2 */ + 0x007d005e, /* MC_LATENCY_ALLOWANCE_NV_1 */ + 0x0000007d, /* MC_LATENCY_ALLOWANCE_NV2_1 */ + 0x007d007d, /* MC_LATENCY_ALLOWANCE_NV3 */ + 0x00ff00ff, /* MC_LATENCY_ALLOWANCE_EPP_0 */ + 0x00ff00ff, /* MC_LATENCY_ALLOWANCE_EPP_1 */ + }, + 0x00000042, /* EMC_ZCAL_WAIT_CNT after clock change */ + 0x001fffff, /* EMC_AUTO_CAL_INTERVAL */ + 0x7320000e, /* EMC_CFG */ + 0x80001221, /* Mode Register 0 */ + 0x80100003, /* Mode Register 1 */ + 0x80200008, /* Mode Register 2 */ + 0x00000000, /* Mode Register 4 */ + 6890, /* expected dvfs latency (ns) */ + }, + { + 0x41, /* Rev 4.0.3 */ + 204000, /* SDRAM frequency */ + 900, /* min voltage */ + "pll_p", /* clock source id */ + 0x40000002, /* CLK_SOURCE_EMC */ + 99, /* number of burst_regs */ + 30, /* number of trim_regs (each channel) */ + 11, /* number of up_down_regs */ + { + 0x00000009, /* EMC_RC */ + 0x00000035, /* EMC_RFC */ + 0x00000000, /* EMC_RFC_SLR */ + 0x00000006, /* EMC_RAS */ + 0x00000002, /* EMC_RP */ + 0x00000004, /* EMC_R2W */ + 0x0000000a, /* EMC_W2R */ + 0x00000003, /* EMC_R2P */ + 0x0000000b, /* EMC_W2P */ + 0x00000002, /* EMC_RD_RCD */ + 0x00000002, /* EMC_WR_RCD */ + 0x00000003, /* EMC_RRD */ + 0x00000001, /* EMC_REXT */ + 0x00000000, /* EMC_WEXT */ + 0x00000005, /* EMC_WDV */ + 0x0000000f, /* EMC_WDV_MASK */ + 0x00000006, /* EMC_IBDLY */ + 0x00010000, /* EMC_PUTERM_EXTRA */ + 0x00000000, /* EMC_CDB_CNTL_2 */ + 0x00000004, /* EMC_QRST */ + 0x0000000e, /* EMC_RDV_MASK */ + 0x00000607, /* EMC_REFRESH */ + 0x00000000, /* EMC_BURST_REFRESH_NUM */ + 0x00000181, /* EMC_PRE_REFRESH_REQ_CNT */ + 0x00000002, /* EMC_PDEX2WR */ + 0x00000002, /* EMC_PDEX2RD */ + 0x00000001, /* EMC_PCHG2PDEN */ + 0x00000000, /* EMC_ACT2PDEN */ + 0x00000032, /* EMC_AR2PDEN */ + 0x0000000f, /* EMC_RW2PDEN */ + 0x00000038, /* EMC_TXSR */ + 0x00000038, /* EMC_TXSRDLL */ + 0x00000004, /* EMC_TCKE */ + 0x00000004, /* EMC_TCKESR */ + 0x00000004, /* EMC_TPD */ + 0x00000009, /* EMC_TFAW */ + 0x00000000, /* EMC_TRPAB */ + 0x00000004, /* EMC_TCLKSTABLE */ + 0x00000005, /* EMC_TCLKSTOP */ + 0x00000638, /* EMC_TREFBW */ + 0x00000006, /* EMC_QUSE_EXTRA */ + 0x00000020, /* EMC_ODT_WRITE */ + 0x00000000, /* EMC_ODT_READ */ + 0x0000aa88, /* EMC_FBIO_CFG5 */ + 0x002c00a0, /* EMC_CFG_DIG_DLL */ + 0x00008000, /* EMC_CFG_DIG_DLL_PERIOD */ + 0x00064000, /* EMC_DLL_XFORM_DQS4 */ + 0x00064000, /* EMC_DLL_XFORM_DQS5 */ + 0x00064000, /* EMC_DLL_XFORM_DQS6 */ + 0x00064000, /* EMC_DLL_XFORM_DQS7 */ + 0x00000000, /* EMC_DLL_XFORM_QUSE4 */ + 0x00000000, /* EMC_DLL_XFORM_QUSE5 */ + 0x00000000, /* EMC_DLL_XFORM_QUSE6 */ + 0x00000000, /* EMC_DLL_XFORM_QUSE7 */ + 0x00000000, /* EMC_DLI_TRIM_TXDQS4 */ + 0x00000000, /* EMC_DLI_TRIM_TXDQS5 */ + 0x00000000, /* EMC_DLI_TRIM_TXDQS6 */ + 0x00000000, /* EMC_DLI_TRIM_TXDQS7 */ + 0x001112a0, /* EMC_XM2CMDPADCTRL */ + 0x00000000, /* EMC_XM2CMDPADCTRL4 */ + 0x0000a11c, /* EMC_XM2DQSPADCTRL2 */ + 0x00000000, /* EMC_XM2DQPADCTRL2 */ + 0x77ffc085, /* EMC_XM2CLKPADCTRL */ + 0x81f1f108, /* EMC_XM2COMPPADCTRL */ + 0x05057404, /* EMC_XM2VTTGENPADCTRL */ + 0x0000003f, /* EMC_XM2VTTGENPADCTRL2 */ + 0x0000003f, /* EMC_DSR_VTTGEN_DRV */ + 0x00000000, /* EMC_TXDSRVTTGEN */ + 0x02000000, /* EMC_FBIO_SPARE */ + 0x00000802, /* EMC_CTT_TERM_CTRL */ + 0x00020000, /* EMC_ZCAL_INTERVAL */ + 0x00000100, /* EMC_ZCAL_WAIT_CNT */ + 0x000f000f, /* EMC_MRS_WAIT_CNT */ + 0x000f000f, /* EMC_MRS_WAIT_CNT2 */ + 0x00000000, /* EMC_AUTO_CAL_CONFIG2 */ + 0x00000000, /* EMC_AUTO_CAL_CONFIG3 */ + 0x00000000, /* EMC_CTT */ + 0x00000000, /* EMC_CTT_DURATION */ + 0x80000d24, /* EMC_DYN_SELF_REF_CONTROL */ + 0x1f7df7df, /* EMC_CA_TRAINING_TIMING_CNTL1 */ + 0x0000001f, /* EMC_CA_TRAINING_TIMING_CNTL2 */ + 0x01000003, /* MC_EMEM_ARB_CFG */ + 0x800000fe, /* MC_EMEM_ARB_OUTSTANDING_REQ */ + 0x00000001, /* MC_EMEM_ARB_TIMING_RCD */ + 0x00000001, /* MC_EMEM_ARB_TIMING_RP */ + 0x00000004, /* MC_EMEM_ARB_TIMING_RC */ + 0x00000002, /* MC_EMEM_ARB_TIMING_RAS */ + 0x00000004, /* MC_EMEM_ARB_TIMING_FAW */ + 0x00000001, /* MC_EMEM_ARB_TIMING_RRD */ + 0x00000002, /* MC_EMEM_ARB_TIMING_RAP2PRE */ + 0x00000008, /* MC_EMEM_ARB_TIMING_WAP2PRE */ + 0x00000002, /* MC_EMEM_ARB_TIMING_R2R */ + 0x00000001, /* MC_EMEM_ARB_TIMING_W2W */ + 0x00000003, /* MC_EMEM_ARB_TIMING_R2W */ + 0x00000006, /* MC_EMEM_ARB_TIMING_W2R */ + 0x06030102, /* MC_EMEM_ARB_DA_TURNS */ + 0x000a0404, /* MC_EMEM_ARB_DA_COVERS */ + 0x73840a05, /* MC_EMEM_ARB_MISC0 */ + 0x001f0000, /* MC_EMEM_ARB_RING1_THROTTLE */ + }, + { + 0x00000000, /* EMC_CDB_CNTL_1 */ + 0x00000004, /* EMC_FBIO_CFG6 */ + 0x00000007, /* EMC_QUSE */ + 0x00000005, /* EMC_EINPUT */ + 0x00000005, /* EMC_EINPUT_DURATION */ + 0x00064000, /* EMC_DLL_XFORM_DQS0 */ + 0x0000000a, /* EMC_QSAFE */ + 0x00000000, /* EMC_DLL_XFORM_QUSE0 */ + 0x0000000d, /* EMC_RDV */ + 0x00249249, /* EMC_XM2DQSPADCTRL4 */ + 0x20820800, /* EMC_XM2DQSPADCTRL3 */ + 0x00070000, /* EMC_DLL_XFORM_DQ0 */ + 0xa0f10000, /* EMC_AUTO_CAL_CONFIG */ + 0x00000000, /* EMC_DLL_XFORM_ADDR0 */ + 0x00000a0a, /* EMC_XM2CLKPADCTRL2 */ + 0x00000000, /* EMC_DLI_TRIM_TXDQS0 */ + 0x00000000, /* EMC_DLL_XFORM_ADDR1 */ + 0x00000000, /* EMC_DLL_XFORM_ADDR2 */ + 0x00064000, /* EMC_DLL_XFORM_DQS1 */ + 0x00064000, /* EMC_DLL_XFORM_DQS2 */ + 0x00064000, /* EMC_DLL_XFORM_DQS3 */ + 0x00070000, /* EMC_DLL_XFORM_DQ1 */ + 0x00070000, /* EMC_DLL_XFORM_DQ2 */ + 0x00070000, /* EMC_DLL_XFORM_DQ3 */ + 0x00000000, /* EMC_DLI_TRIM_TXDQS1 */ + 0x00000000, /* EMC_DLI_TRIM_TXDQS2 */ + 0x00000000, /* EMC_DLI_TRIM_TXDQS3 */ + 0x00000000, /* EMC_DLL_XFORM_QUSE1 */ + 0x00000000, /* EMC_DLL_XFORM_QUSE2 */ + 0x00000000, /* EMC_DLL_XFORM_QUSE3 */ + }, + { + 0x00000000, /* EMC_CDB_CNTL_1 */ + 0x00000004, /* EMC_FBIO_CFG6 */ + 0x00000007, /* EMC_QUSE */ + 0x00000005, /* EMC_EINPUT */ + 0x00000005, /* EMC_EINPUT_DURATION */ + 0x00064000, /* EMC_DLL_XFORM_DQS0 */ + 0x0000000a, /* EMC_QSAFE */ + 0x00000000, /* EMC_DLL_XFORM_QUSE0 */ + 0x0000000d, /* EMC_RDV */ + 0x00249249, /* EMC_XM2DQSPADCTRL4 */ + 0x20820800, /* EMC_XM2DQSPADCTRL3 */ + 0x00070000, /* EMC_DLL_XFORM_DQ0 */ + 0xa8f10000, /* EMC_AUTO_CAL_CONFIG */ + 0x00000000, /* EMC_DLL_XFORM_ADDR0 */ + 0x00000a0a, /* EMC_XM2CLKPADCTRL2 */ + 0x00000000, /* EMC_DLI_TRIM_TXDQS0 */ + 0x00000000, /* EMC_DLL_XFORM_ADDR1 */ + 0x00000000, /* EMC_DLL_XFORM_ADDR2 */ + 0x00064000, /* EMC_DLL_XFORM_DQS1 */ + 0x00064000, /* EMC_DLL_XFORM_DQS2 */ + 0x00064000, /* EMC_DLL_XFORM_DQS3 */ + 0x00070000, /* EMC_DLL_XFORM_DQ1 */ + 0x00070000, /* EMC_DLL_XFORM_DQ2 */ + 0x00070000, /* EMC_DLL_XFORM_DQ3 */ 0x00000000, /* EMC_DLI_TRIM_TXDQS1 */ 0x00000000, /* EMC_DLI_TRIM_TXDQS2 */ 0x00000000, /* EMC_DLI_TRIM_TXDQS3 */ @@ -1208,17 +3760,17 @@ static struct tegra11_emc_table p2454_h5tc4g63afr_pba_table[] = { { 0x41, /* Rev 4.0.3 */ 312000, /* SDRAM frequency */ - 1100, /* min voltage */ + 1000, /* min voltage */ "pll_c", /* clock source id */ - 0x20000002, /* CLK_SOURCE_EMC */ + 0x24000002, /* CLK_SOURCE_EMC */ 99, /* number of burst_regs */ 30, /* number of trim_regs (each channel) */ 11, /* number of up_down_regs */ { - 0x0000000e, /* EMC_RC */ - 0x0000004f, /* EMC_RFC */ + 0x0000000d, /* EMC_RC */ + 0x00000050, /* EMC_RFC */ 0x00000000, /* EMC_RFC_SLR */ - 0x0000000a, /* EMC_RAS */ + 0x00000009, /* EMC_RAS */ 0x00000003, /* EMC_RP */ 0x00000004, /* EMC_R2W */ 0x00000008, /* EMC_W2R */ @@ -1230,41 +3782,41 @@ static struct tegra11_emc_table p2454_h5tc4g63afr_pba_table[] = { 0x00000001, /* EMC_REXT */ 0x00000000, /* EMC_WEXT */ 0x00000004, /* EMC_WDV */ - 0x00000004, /* EMC_WDV_MASK */ + 0x0000000f, /* EMC_WDV_MASK */ 0x00000007, /* EMC_IBDLY */ - 0x00080006, /* EMC_PUTERM_EXTRA */ + 0x00010000, /* EMC_PUTERM_EXTRA */ 0x00000000, /* EMC_CDB_CNTL_2 */ 0x00000004, /* EMC_QRST */ - 0x0000000d, /* EMC_RDV_MASK */ - 0x000009ce, /* EMC_REFRESH */ + 0x0000000f, /* EMC_RDV_MASK */ + 0x00000945, /* EMC_REFRESH */ 0x00000000, /* EMC_BURST_REFRESH_NUM */ - 0x00000273, /* EMC_PRE_REFRESH_REQ_CNT */ + 0x00000251, /* EMC_PRE_REFRESH_REQ_CNT */ 0x00000001, /* EMC_PDEX2WR */ 0x00000008, /* EMC_PDEX2RD */ 0x00000001, /* EMC_PCHG2PDEN */ 0x00000000, /* EMC_ACT2PDEN */ - 0x0000004c, /* EMC_AR2PDEN */ + 0x0000004d, /* EMC_AR2PDEN */ 0x0000000e, /* EMC_RW2PDEN */ - 0x00000054, /* EMC_TXSR */ + 0x00000055, /* EMC_TXSR */ 0x00000200, /* EMC_TXSRDLL */ 0x00000004, /* EMC_TCKE */ 0x00000004, /* EMC_TCKESR */ 0x00000004, /* EMC_TPD */ - 0x0000000e, /* EMC_TFAW */ + 0x0000000d, /* EMC_TFAW */ 0x00000000, /* EMC_TRPAB */ 0x00000004, /* EMC_TCLKSTABLE */ 0x00000005, /* EMC_TCLKSTOP */ - 0x00000a0f, /* EMC_TREFBW */ - 0x00000007, /* EMC_QUSE_EXTRA */ + 0x00000986, /* EMC_TREFBW */ + 0x00000006, /* EMC_QUSE_EXTRA */ 0x00000020, /* EMC_ODT_WRITE */ 0x00000000, /* EMC_ODT_READ */ - 0x0000b888, /* EMC_FBIO_CFG5 */ + 0x0000ba88, /* EMC_FBIO_CFG5 */ 0x002c00a0, /* EMC_CFG_DIG_DLL */ 0x00008000, /* EMC_CFG_DIG_DLL_PERIOD */ - 0x00070000, /* EMC_DLL_XFORM_DQS4 */ - 0x00070000, /* EMC_DLL_XFORM_DQS5 */ - 0x00070000, /* EMC_DLL_XFORM_DQS6 */ - 0x00070000, /* EMC_DLL_XFORM_DQS7 */ + 0x00038000, /* EMC_DLL_XFORM_DQS4 */ + 0x00038000, /* EMC_DLL_XFORM_DQS5 */ + 0x00038000, /* EMC_DLL_XFORM_DQS6 */ + 0x00038000, /* EMC_DLL_XFORM_DQS7 */ 0x00000000, /* EMC_DLL_XFORM_QUSE4 */ 0x00000000, /* EMC_DLL_XFORM_QUSE5 */ 0x00000000, /* EMC_DLL_XFORM_QUSE6 */ @@ -1275,9 +3827,9 @@ static struct tegra11_emc_table p2454_h5tc4g63afr_pba_table[] = { 0x00000000, /* EMC_DLI_TRIM_TXDQS7 */ 0x001112a0, /* EMC_XM2CMDPADCTRL */ 0x00000000, /* EMC_XM2CMDPADCTRL4 */ - 0x0003033d, /* EMC_XM2DQSPADCTRL2 */ + 0x0001013d, /* EMC_XM2DQSPADCTRL2 */ 0x00000000, /* EMC_XM2DQPADCTRL2 */ - 0x77ffc084, /* EMC_XM2CLKPADCTRL */ + 0x77ffc085, /* EMC_XM2CLKPADCTRL */ 0x81f1f108, /* EMC_XM2COMPPADCTRL */ 0x03035504, /* EMC_XM2VTTGENPADCTRL */ 0x00000000, /* EMC_XM2VTTGENPADCTRL2 */ @@ -1287,20 +3839,20 @@ static struct tegra11_emc_table p2454_h5tc4g63afr_pba_table[] = { 0x00000802, /* EMC_CTT_TERM_CTRL */ 0x00020000, /* EMC_ZCAL_INTERVAL */ 0x00000100, /* EMC_ZCAL_WAIT_CNT */ - 0x0172000f, /* EMC_MRS_WAIT_CNT */ - 0x0172000f, /* EMC_MRS_WAIT_CNT2 */ + 0x0171000f, /* EMC_MRS_WAIT_CNT */ + 0x0171000f, /* EMC_MRS_WAIT_CNT2 */ 0x00000000, /* EMC_AUTO_CAL_CONFIG2 */ 0x00000000, /* EMC_AUTO_CAL_CONFIG3 */ 0x00000000, /* EMC_CTT */ 0x00000000, /* EMC_CTT_DURATION */ - 0x8000149f, /* EMC_DYN_SELF_REF_CONTROL */ + 0x80001395, /* EMC_DYN_SELF_REF_CONTROL */ 0x1f7df7df, /* EMC_CA_TRAINING_TIMING_CNTL1 */ 0x0000001f, /* EMC_CA_TRAINING_TIMING_CNTL2 */ - 0x0f000004, /* MC_EMEM_ARB_CFG */ - 0x8000017c, /* MC_EMEM_ARB_OUTSTANDING_REQ */ + 0x0b000004, /* MC_EMEM_ARB_CFG */ + 0x8000016a, /* MC_EMEM_ARB_OUTSTANDING_REQ */ 0x00000001, /* MC_EMEM_ARB_TIMING_RCD */ 0x00000002, /* MC_EMEM_ARB_TIMING_RP */ - 0x00000008, /* MC_EMEM_ARB_TIMING_RC */ + 0x00000007, /* MC_EMEM_ARB_TIMING_RC */ 0x00000004, /* MC_EMEM_ARB_TIMING_RAS */ 0x00000006, /* MC_EMEM_ARB_TIMING_FAW */ 0x00000001, /* MC_EMEM_ARB_TIMING_RRD */ @@ -1311,35 +3863,35 @@ static struct tegra11_emc_table p2454_h5tc4g63afr_pba_table[] = { 0x00000004, /* MC_EMEM_ARB_TIMING_R2W */ 0x00000006, /* MC_EMEM_ARB_TIMING_W2R */ 0x06040202, /* MC_EMEM_ARB_DA_TURNS */ - 0x000b0608, /* MC_EMEM_ARB_DA_COVERS */ - 0x76850f09, /* MC_EMEM_ARB_MISC0 */ + 0x000b0607, /* MC_EMEM_ARB_DA_COVERS */ + 0x76e50f08, /* MC_EMEM_ARB_MISC0 */ 0x001f0000, /* MC_EMEM_ARB_RING1_THROTTLE */ }, { 0x00000000, /* EMC_CDB_CNTL_1 */ - 0x00000004, /* EMC_FBIO_CFG6 */ - 0x00000008, /* EMC_QUSE */ + 0x00000006, /* EMC_FBIO_CFG6 */ + 0x00000007, /* EMC_QUSE */ 0x00000005, /* EMC_EINPUT */ 0x00000004, /* EMC_EINPUT_DURATION */ - 0x00070000, /* EMC_DLL_XFORM_DQS0 */ + 0x00038000, /* EMC_DLL_XFORM_DQS0 */ 0x0000000b, /* EMC_QSAFE */ 0x00000000, /* EMC_DLL_XFORM_QUSE0 */ - 0x0000000d, /* EMC_RDV */ - 0x0079e79e, /* EMC_XM2DQSPADCTRL4 */ - 0x10410400, /* EMC_XM2DQSPADCTRL3 */ - 0x00050000, /* EMC_DLL_XFORM_DQ0 */ + 0x0000000e, /* EMC_RDV */ + 0x00249249, /* EMC_XM2DQSPADCTRL4 */ + 0x20820800, /* EMC_XM2DQSPADCTRL3 */ + 0x00048000, /* EMC_DLL_XFORM_DQ0 */ 0xa0f10000, /* EMC_AUTO_CAL_CONFIG */ 0x00000000, /* EMC_DLL_XFORM_ADDR0 */ - 0x00000f0f, /* EMC_XM2CLKPADCTRL2 */ + 0x00000808, /* EMC_XM2CLKPADCTRL2 */ 0x00000000, /* EMC_DLI_TRIM_TXDQS0 */ 0x00000000, /* EMC_DLL_XFORM_ADDR1 */ 0x00000000, /* EMC_DLL_XFORM_ADDR2 */ - 0x00070000, /* EMC_DLL_XFORM_DQS1 */ - 0x00070000, /* EMC_DLL_XFORM_DQS2 */ - 0x00070000, /* EMC_DLL_XFORM_DQS3 */ - 0x00050000, /* EMC_DLL_XFORM_DQ1 */ - 0x00050000, /* EMC_DLL_XFORM_DQ2 */ - 0x00050000, /* EMC_DLL_XFORM_DQ3 */ + 0x00038000, /* EMC_DLL_XFORM_DQS1 */ + 0x00038000, /* EMC_DLL_XFORM_DQS2 */ + 0x00038000, /* EMC_DLL_XFORM_DQS3 */ + 0x00048000, /* EMC_DLL_XFORM_DQ1 */ + 0x00048000, /* EMC_DLL_XFORM_DQ2 */ + 0x00048000, /* EMC_DLL_XFORM_DQ3 */ 0x00000000, /* EMC_DLI_TRIM_TXDQS1 */ 0x00000000, /* EMC_DLI_TRIM_TXDQS2 */ 0x00000000, /* EMC_DLI_TRIM_TXDQS3 */ @@ -1349,29 +3901,29 @@ static struct tegra11_emc_table p2454_h5tc4g63afr_pba_table[] = { }, { 0x00000000, /* EMC_CDB_CNTL_1 */ - 0x00000004, /* EMC_FBIO_CFG6 */ - 0x00000008, /* EMC_QUSE */ + 0x00000006, /* EMC_FBIO_CFG6 */ + 0x00000007, /* EMC_QUSE */ 0x00000005, /* EMC_EINPUT */ 0x00000004, /* EMC_EINPUT_DURATION */ - 0x00070000, /* EMC_DLL_XFORM_DQS0 */ + 0x00038000, /* EMC_DLL_XFORM_DQS0 */ 0x0000000b, /* EMC_QSAFE */ 0x00000000, /* EMC_DLL_XFORM_QUSE0 */ - 0x0000000d, /* EMC_RDV */ - 0x0079e79e, /* EMC_XM2DQSPADCTRL4 */ - 0x10410400, /* EMC_XM2DQSPADCTRL3 */ - 0x00050000, /* EMC_DLL_XFORM_DQ0 */ + 0x0000000e, /* EMC_RDV */ + 0x00249249, /* EMC_XM2DQSPADCTRL4 */ + 0x20820800, /* EMC_XM2DQSPADCTRL3 */ + 0x00048000, /* EMC_DLL_XFORM_DQ0 */ 0xa8f10000, /* EMC_AUTO_CAL_CONFIG */ 0x00000000, /* EMC_DLL_XFORM_ADDR0 */ - 0x00000f0f, /* EMC_XM2CLKPADCTRL2 */ + 0x00000808, /* EMC_XM2CLKPADCTRL2 */ 0x00000000, /* EMC_DLI_TRIM_TXDQS0 */ 0x00000000, /* EMC_DLL_XFORM_ADDR1 */ 0x00000000, /* EMC_DLL_XFORM_ADDR2 */ - 0x00070000, /* EMC_DLL_XFORM_DQS1 */ - 0x00070000, /* EMC_DLL_XFORM_DQS2 */ - 0x00070000, /* EMC_DLL_XFORM_DQS3 */ - 0x00050000, /* EMC_DLL_XFORM_DQ1 */ - 0x00050000, /* EMC_DLL_XFORM_DQ2 */ - 0x00050000, /* EMC_DLL_XFORM_DQ3 */ + 0x00038000, /* EMC_DLL_XFORM_DQS1 */ + 0x00038000, /* EMC_DLL_XFORM_DQS2 */ + 0x00038000, /* EMC_DLL_XFORM_DQS3 */ + 0x00048000, /* EMC_DLL_XFORM_DQ1 */ + 0x00048000, /* EMC_DLL_XFORM_DQ2 */ + 0x00048000, /* EMC_DLL_XFORM_DQ3 */ 0x00000000, /* EMC_DLI_TRIM_TXDQS1 */ 0x00000000, /* EMC_DLI_TRIM_TXDQS2 */ 0x00000000, /* EMC_DLI_TRIM_TXDQS3 */ @@ -1394,7 +3946,7 @@ static struct tegra11_emc_table p2454_h5tc4g63afr_pba_table[] = { }, 0x00000042, /* EMC_ZCAL_WAIT_CNT after clock change */ 0x001fffff, /* EMC_AUTO_CAL_INTERVAL */ - 0x7310000e, /* EMC_CFG */ + 0x5320000e, /* EMC_CFG */ 0x80000321, /* Mode Register 0 */ 0x80100002, /* Mode Register 1 */ 0x80200000, /* Mode Register 2 */ @@ -1404,34 +3956,34 @@ static struct tegra11_emc_table p2454_h5tc4g63afr_pba_table[] = { { 0x41, /* Rev 4.0.3 */ 408000, /* SDRAM frequency */ - 1100, /* min voltage */ + 1000, /* min voltage */ "pll_p", /* clock source id */ 0x40000000, /* CLK_SOURCE_EMC */ 99, /* number of burst_regs */ 30, /* number of trim_regs (each channel) */ 11, /* number of up_down_regs */ { - 0x00000011, /* EMC_RC */ - 0x00000062, /* EMC_RFC */ + 0x00000012, /* EMC_RC */ + 0x00000069, /* EMC_RFC */ 0x00000000, /* EMC_RFC_SLR */ 0x0000000c, /* EMC_RAS */ 0x00000004, /* EMC_RP */ 0x00000005, /* EMC_R2W */ 0x00000009, /* EMC_W2R */ 0x00000002, /* EMC_R2P */ - 0x0000000b, /* EMC_W2P */ + 0x0000000c, /* EMC_W2P */ 0x00000004, /* EMC_RD_RCD */ 0x00000004, /* EMC_WR_RCD */ 0x00000002, /* EMC_RRD */ 0x00000001, /* EMC_REXT */ 0x00000000, /* EMC_WEXT */ 0x00000004, /* EMC_WDV */ - 0x00000004, /* EMC_WDV_MASK */ + 0x0000000f, /* EMC_WDV_MASK */ 0x00000007, /* EMC_IBDLY */ 0x00010000, /* EMC_PUTERM_EXTRA */ 0x00000000, /* EMC_CDB_CNTL_2 */ 0x00000004, /* EMC_QRST */ - 0x0000000e, /* EMC_RDV_MASK */ + 0x00000010, /* EMC_RDV_MASK */ 0x00000c2f, /* EMC_REFRESH */ 0x00000000, /* EMC_BURST_REFRESH_NUM */ 0x0000030b, /* EMC_PRE_REFRESH_REQ_CNT */ @@ -1439,9 +3991,9 @@ static struct tegra11_emc_table p2454_h5tc4g63afr_pba_table[] = { 0x00000008, /* EMC_PDEX2RD */ 0x00000001, /* EMC_PCHG2PDEN */ 0x00000000, /* EMC_ACT2PDEN */ - 0x0000005f, /* EMC_AR2PDEN */ - 0x00000010, /* EMC_RW2PDEN */ - 0x00000068, /* EMC_TXSR */ + 0x00000066, /* EMC_AR2PDEN */ + 0x00000011, /* EMC_RW2PDEN */ + 0x0000006f, /* EMC_TXSR */ 0x00000200, /* EMC_TXSRDLL */ 0x00000004, /* EMC_TCKE */ 0x00000004, /* EMC_TCKESR */ @@ -1457,10 +4009,10 @@ static struct tegra11_emc_table p2454_h5tc4g63afr_pba_table[] = { 0x0000ba88, /* EMC_FBIO_CFG5 */ 0x002c0080, /* EMC_CFG_DIG_DLL */ 0x00008000, /* EMC_CFG_DIG_DLL_PERIOD */ - 0x00030000, /* EMC_DLL_XFORM_DQS4 */ - 0x00030000, /* EMC_DLL_XFORM_DQS5 */ - 0x00030000, /* EMC_DLL_XFORM_DQS6 */ - 0x00030000, /* EMC_DLL_XFORM_DQS7 */ + 0x00028000, /* EMC_DLL_XFORM_DQS4 */ + 0x00028000, /* EMC_DLL_XFORM_DQS5 */ + 0x00028000, /* EMC_DLL_XFORM_DQS6 */ + 0x00028000, /* EMC_DLL_XFORM_DQS7 */ 0x00000000, /* EMC_DLL_XFORM_QUSE4 */ 0x00000000, /* EMC_DLL_XFORM_QUSE5 */ 0x00000000, /* EMC_DLL_XFORM_QUSE6 */ @@ -1471,9 +4023,9 @@ static struct tegra11_emc_table p2454_h5tc4g63afr_pba_table[] = { 0x00000000, /* EMC_DLI_TRIM_TXDQS7 */ 0x001112a0, /* EMC_XM2CMDPADCTRL */ 0x00000000, /* EMC_XM2CMDPADCTRL4 */ - 0x0003033d, /* EMC_XM2DQSPADCTRL2 */ + 0x0001013d, /* EMC_XM2DQSPADCTRL2 */ 0x00000000, /* EMC_XM2DQPADCTRL2 */ - 0x77ffc084, /* EMC_XM2CLKPADCTRL */ + 0x77ffc085, /* EMC_XM2CLKPADCTRL */ 0x81f1f108, /* EMC_XM2COMPPADCTRL */ 0x03035504, /* EMC_XM2VTTGENPADCTRL */ 0x00000000, /* EMC_XM2VTTGENPADCTRL2 */ @@ -1483,8 +4035,8 @@ static struct tegra11_emc_table p2454_h5tc4g63afr_pba_table[] = { 0x00000802, /* EMC_CTT_TERM_CTRL */ 0x00020000, /* EMC_ZCAL_INTERVAL */ 0x00000100, /* EMC_ZCAL_WAIT_CNT */ - 0x015f000f, /* EMC_MRS_WAIT_CNT */ - 0x015f000f, /* EMC_MRS_WAIT_CNT2 */ + 0x0158000f, /* EMC_MRS_WAIT_CNT */ + 0x0158000f, /* EMC_MRS_WAIT_CNT2 */ 0x00000000, /* EMC_AUTO_CAL_CONFIG2 */ 0x00000000, /* EMC_AUTO_CAL_CONFIG3 */ 0x00000000, /* EMC_CTT */ @@ -1501,13 +4053,13 @@ static struct tegra11_emc_table p2454_h5tc4g63afr_pba_table[] = { 0x00000008, /* MC_EMEM_ARB_TIMING_FAW */ 0x00000001, /* MC_EMEM_ARB_TIMING_RRD */ 0x00000002, /* MC_EMEM_ARB_TIMING_RAP2PRE */ - 0x00000008, /* MC_EMEM_ARB_TIMING_WAP2PRE */ + 0x00000009, /* MC_EMEM_ARB_TIMING_WAP2PRE */ 0x00000002, /* MC_EMEM_ARB_TIMING_R2R */ 0x00000002, /* MC_EMEM_ARB_TIMING_W2W */ 0x00000004, /* MC_EMEM_ARB_TIMING_R2W */ 0x00000006, /* MC_EMEM_ARB_TIMING_W2R */ 0x06040202, /* MC_EMEM_ARB_DA_TURNS */ - 0x000d0709, /* MC_EMEM_ARB_DA_COVERS */ + 0x000e0709, /* MC_EMEM_ARB_DA_COVERS */ 0x7547130a, /* MC_EMEM_ARB_MISC0 */ 0x001f0000, /* MC_EMEM_ARB_RING1_THROTTLE */ }, @@ -1517,25 +4069,25 @@ static struct tegra11_emc_table p2454_h5tc4g63afr_pba_table[] = { 0x00000007, /* EMC_QUSE */ 0x00000005, /* EMC_EINPUT */ 0x00000004, /* EMC_EINPUT_DURATION */ - 0x00030000, /* EMC_DLL_XFORM_DQS0 */ + 0x00028000, /* EMC_DLL_XFORM_DQS0 */ 0x0000000c, /* EMC_QSAFE */ 0x00000000, /* EMC_DLL_XFORM_QUSE0 */ 0x0000000e, /* EMC_RDV */ - 0x0079e79e, /* EMC_XM2DQSPADCTRL4 */ + 0x00249249, /* EMC_XM2DQSPADCTRL4 */ 0x20820800, /* EMC_XM2DQSPADCTRL3 */ 0x00038000, /* EMC_DLL_XFORM_DQ0 */ 0xa0f10000, /* EMC_AUTO_CAL_CONFIG */ 0x00000000, /* EMC_DLL_XFORM_ADDR0 */ - 0x00000606, /* EMC_XM2CLKPADCTRL2 */ + 0x00000808, /* EMC_XM2CLKPADCTRL2 */ 0x00000000, /* EMC_DLI_TRIM_TXDQS0 */ 0x00000000, /* EMC_DLL_XFORM_ADDR1 */ 0x00000000, /* EMC_DLL_XFORM_ADDR2 */ - 0x00030000, /* EMC_DLL_XFORM_DQS1 */ - 0x00030000, /* EMC_DLL_XFORM_DQS2 */ - 0x00030000, /* EMC_DLL_XFORM_DQS3 */ + 0x00028000, /* EMC_DLL_XFORM_DQS1 */ + 0x00028000, /* EMC_DLL_XFORM_DQS2 */ + 0x00028000, /* EMC_DLL_XFORM_DQS3 */ 0x00038000, /* EMC_DLL_XFORM_DQ1 */ 0x00038000, /* EMC_DLL_XFORM_DQ2 */ - 0x0003c000, /* EMC_DLL_XFORM_DQ3 */ + 0x00038000, /* EMC_DLL_XFORM_DQ3 */ 0x00000000, /* EMC_DLI_TRIM_TXDQS1 */ 0x00000000, /* EMC_DLI_TRIM_TXDQS2 */ 0x00000000, /* EMC_DLI_TRIM_TXDQS3 */ @@ -1549,25 +4101,25 @@ static struct tegra11_emc_table p2454_h5tc4g63afr_pba_table[] = { 0x00000007, /* EMC_QUSE */ 0x00000005, /* EMC_EINPUT */ 0x00000004, /* EMC_EINPUT_DURATION */ - 0x00030000, /* EMC_DLL_XFORM_DQS0 */ + 0x00028000, /* EMC_DLL_XFORM_DQS0 */ 0x0000000c, /* EMC_QSAFE */ 0x00000000, /* EMC_DLL_XFORM_QUSE0 */ 0x0000000e, /* EMC_RDV */ - 0x0079e79e, /* EMC_XM2DQSPADCTRL4 */ + 0x00249249, /* EMC_XM2DQSPADCTRL4 */ 0x20820800, /* EMC_XM2DQSPADCTRL3 */ 0x00038000, /* EMC_DLL_XFORM_DQ0 */ 0xa8f10000, /* EMC_AUTO_CAL_CONFIG */ 0x00000000, /* EMC_DLL_XFORM_ADDR0 */ - 0x00000707, /* EMC_XM2CLKPADCTRL2 */ + 0x00000808, /* EMC_XM2CLKPADCTRL2 */ 0x00000000, /* EMC_DLI_TRIM_TXDQS0 */ 0x00000000, /* EMC_DLL_XFORM_ADDR1 */ 0x00000000, /* EMC_DLL_XFORM_ADDR2 */ - 0x00030000, /* EMC_DLL_XFORM_DQS1 */ - 0x00030000, /* EMC_DLL_XFORM_DQS2 */ - 0x00030000, /* EMC_DLL_XFORM_DQS3 */ + 0x00028000, /* EMC_DLL_XFORM_DQS1 */ + 0x00028000, /* EMC_DLL_XFORM_DQS2 */ + 0x00028000, /* EMC_DLL_XFORM_DQS3 */ 0x00038000, /* EMC_DLL_XFORM_DQ1 */ 0x00038000, /* EMC_DLL_XFORM_DQ2 */ - 0x0003c000, /* EMC_DLL_XFORM_DQ3 */ + 0x00038000, /* EMC_DLL_XFORM_DQ3 */ 0x00000000, /* EMC_DLI_TRIM_TXDQS1 */ 0x00000000, /* EMC_DLI_TRIM_TXDQS2 */ 0x00000000, /* EMC_DLI_TRIM_TXDQS3 */ @@ -1590,8 +4142,8 @@ static struct tegra11_emc_table p2454_h5tc4g63afr_pba_table[] = { }, 0x00000042, /* EMC_ZCAL_WAIT_CNT after clock change */ 0x001fffff, /* EMC_AUTO_CAL_INTERVAL */ - 0x73200006, /* EMC_CFG */ - 0x80000531, /* Mode Register 0 */ + 0x53200006, /* EMC_CFG */ + 0x80000731, /* Mode Register 0 */ 0x80100002, /* Mode Register 1 */ 0x80200008, /* Mode Register 2 */ 0x00000000, /* Mode Register 4 */ @@ -1607,10 +4159,10 @@ static struct tegra11_emc_table p2454_h5tc4g63afr_pba_table[] = { 30, /* number of trim_regs (each channel) */ 11, /* number of up_down_regs */ { - 0x00000015, /* EMC_RC */ - 0x00000073, /* EMC_RFC */ + 0x00000014, /* EMC_RC */ + 0x00000074, /* EMC_RFC */ 0x00000000, /* EMC_RFC_SLR */ - 0x0000000f, /* EMC_RAS */ + 0x0000000e, /* EMC_RAS */ 0x00000005, /* EMC_RP */ 0x00000005, /* EMC_R2W */ 0x00000009, /* EMC_W2R */ @@ -1622,41 +4174,41 @@ static struct tegra11_emc_table p2454_h5tc4g63afr_pba_table[] = { 0x00000001, /* EMC_REXT */ 0x00000000, /* EMC_WEXT */ 0x00000004, /* EMC_WDV */ - 0x00000004, /* EMC_WDV_MASK */ + 0x0000000f, /* EMC_WDV_MASK */ 0x00000007, /* EMC_IBDLY */ 0x00010000, /* EMC_PUTERM_EXTRA */ 0x00000000, /* EMC_CDB_CNTL_2 */ 0x00000004, /* EMC_QRST */ - 0x0000000e, /* EMC_RDV_MASK */ - 0x00000e66, /* EMC_REFRESH */ + 0x00000010, /* EMC_RDV_MASK */ + 0x00000d79, /* EMC_REFRESH */ 0x00000000, /* EMC_BURST_REFRESH_NUM */ - 0x00000399, /* EMC_PRE_REFRESH_REQ_CNT */ + 0x0000035e, /* EMC_PRE_REFRESH_REQ_CNT */ 0x00000001, /* EMC_PDEX2WR */ - 0x0000000a, /* EMC_PDEX2RD */ + 0x00000009, /* EMC_PDEX2RD */ 0x00000001, /* EMC_PCHG2PDEN */ 0x00000000, /* EMC_ACT2PDEN */ - 0x00000070, /* EMC_AR2PDEN */ + 0x00000071, /* EMC_AR2PDEN */ 0x00000011, /* EMC_RW2PDEN */ 0x0000007a, /* EMC_TXSR */ 0x00000200, /* EMC_TXSRDLL */ 0x00000004, /* EMC_TCKE */ 0x00000004, /* EMC_TCKESR */ 0x00000004, /* EMC_TPD */ - 0x00000014, /* EMC_TFAW */ + 0x00000013, /* EMC_TFAW */ 0x00000000, /* EMC_TRPAB */ 0x00000004, /* EMC_TCLKSTABLE */ 0x00000005, /* EMC_TCLKSTOP */ - 0x00000ea6, /* EMC_TREFBW */ + 0x00000dba, /* EMC_TREFBW */ 0x00000006, /* EMC_QUSE_EXTRA */ 0x00000020, /* EMC_ODT_WRITE */ 0x00000000, /* EMC_ODT_READ */ 0x0000ba88, /* EMC_FBIO_CFG5 */ - 0xf0120091, /* EMC_CFG_DIG_DLL */ + 0x002c0080, /* EMC_CFG_DIG_DLL */ 0x00008000, /* EMC_CFG_DIG_DLL_PERIOD */ - 0x00000008, /* EMC_DLL_XFORM_DQS4 */ - 0x00000008, /* EMC_DLL_XFORM_DQS5 */ - 0x00000008, /* EMC_DLL_XFORM_DQS6 */ - 0x00000008, /* EMC_DLL_XFORM_DQS7 */ + 0x00020000, /* EMC_DLL_XFORM_DQS4 */ + 0x00020000, /* EMC_DLL_XFORM_DQS5 */ + 0x00020000, /* EMC_DLL_XFORM_DQS6 */ + 0x00020000, /* EMC_DLL_XFORM_DQS7 */ 0x00000000, /* EMC_DLL_XFORM_QUSE4 */ 0x00000000, /* EMC_DLL_XFORM_QUSE5 */ 0x00000000, /* EMC_DLL_XFORM_QUSE6 */ @@ -1667,9 +4219,9 @@ static struct tegra11_emc_table p2454_h5tc4g63afr_pba_table[] = { 0x00000000, /* EMC_DLI_TRIM_TXDQS7 */ 0x001112a0, /* EMC_XM2CMDPADCTRL */ 0x00000000, /* EMC_XM2CMDPADCTRL4 */ - 0x0003033d, /* EMC_XM2DQSPADCTRL2 */ + 0x0000013d, /* EMC_XM2DQSPADCTRL2 */ 0x00000000, /* EMC_XM2DQPADCTRL2 */ - 0x77ffc084, /* EMC_XM2CLKPADCTRL */ + 0x77ffc085, /* EMC_XM2CLKPADCTRL */ 0x81f1f108, /* EMC_XM2COMPPADCTRL */ 0x03035504, /* EMC_XM2VTTGENPADCTRL */ 0x00000000, /* EMC_XM2VTTGENPADCTRL2 */ @@ -1679,21 +4231,21 @@ static struct tegra11_emc_table p2454_h5tc4g63afr_pba_table[] = { 0x00000802, /* EMC_CTT_TERM_CTRL */ 0x00020000, /* EMC_ZCAL_INTERVAL */ 0x00000100, /* EMC_ZCAL_WAIT_CNT */ - 0x014e000f, /* EMC_MRS_WAIT_CNT */ - 0x014e000f, /* EMC_MRS_WAIT_CNT2 */ + 0x014d000f, /* EMC_MRS_WAIT_CNT */ + 0x014d000f, /* EMC_MRS_WAIT_CNT2 */ 0x00000000, /* EMC_AUTO_CAL_CONFIG2 */ 0x00000000, /* EMC_AUTO_CAL_CONFIG3 */ 0x00000000, /* EMC_CTT */ 0x00000000, /* EMC_CTT_DURATION */ - 0x80001d94, /* EMC_DYN_SELF_REF_CONTROL */ + 0x80001bc7, /* EMC_DYN_SELF_REF_CONTROL */ 0x1f7df7df, /* EMC_CA_TRAINING_TIMING_CNTL1 */ 0x0000001f, /* EMC_CA_TRAINING_TIMING_CNTL2 */ - 0x03000007, /* MC_EMEM_ARB_CFG */ + 0x0c000006, /* MC_EMEM_ARB_CFG */ 0x80000190, /* MC_EMEM_ARB_OUTSTANDING_REQ */ 0x00000002, /* MC_EMEM_ARB_TIMING_RCD */ 0x00000003, /* MC_EMEM_ARB_TIMING_RP */ 0x0000000b, /* MC_EMEM_ARB_TIMING_RC */ - 0x00000007, /* MC_EMEM_ARB_TIMING_RAS */ + 0x00000006, /* MC_EMEM_ARB_TIMING_RAS */ 0x00000009, /* MC_EMEM_ARB_TIMING_FAW */ 0x00000001, /* MC_EMEM_ARB_TIMING_RRD */ 0x00000002, /* MC_EMEM_ARB_TIMING_RAP2PRE */ @@ -1704,34 +4256,34 @@ static struct tegra11_emc_table p2454_h5tc4g63afr_pba_table[] = { 0x00000006, /* MC_EMEM_ARB_TIMING_W2R */ 0x06040202, /* MC_EMEM_ARB_DA_TURNS */ 0x000f080b, /* MC_EMEM_ARB_DA_COVERS */ - 0x7488160c, /* MC_EMEM_ARB_MISC0 */ + 0x74c7150c, /* MC_EMEM_ARB_MISC0 */ 0x001f0000, /* MC_EMEM_ARB_RING1_THROTTLE */ }, { 0x00000000, /* EMC_CDB_CNTL_1 */ - 0x00000004, /* EMC_FBIO_CFG6 */ + 0x00000006, /* EMC_FBIO_CFG6 */ 0x00000007, /* EMC_QUSE */ 0x00000005, /* EMC_EINPUT */ 0x00000004, /* EMC_EINPUT_DURATION */ - 0x00000008, /* EMC_DLL_XFORM_DQS0 */ + 0x00020000, /* EMC_DLL_XFORM_DQS0 */ 0x0000000c, /* EMC_QSAFE */ 0x00000000, /* EMC_DLL_XFORM_QUSE0 */ 0x0000000e, /* EMC_RDV */ - 0x0079e79e, /* EMC_XM2DQSPADCTRL4 */ + 0x00249249, /* EMC_XM2DQSPADCTRL4 */ 0x20820800, /* EMC_XM2DQSPADCTRL3 */ - 0x00000008, /* EMC_DLL_XFORM_DQ0 */ + 0x00028000, /* EMC_DLL_XFORM_DQ0 */ 0xa0f10000, /* EMC_AUTO_CAL_CONFIG */ 0x00000000, /* EMC_DLL_XFORM_ADDR0 */ - 0x00000606, /* EMC_XM2CLKPADCTRL2 */ + 0x00000808, /* EMC_XM2CLKPADCTRL2 */ 0x00000000, /* EMC_DLI_TRIM_TXDQS0 */ 0x00000000, /* EMC_DLL_XFORM_ADDR1 */ 0x00000000, /* EMC_DLL_XFORM_ADDR2 */ - 0x00000008, /* EMC_DLL_XFORM_DQS1 */ - 0x00000008, /* EMC_DLL_XFORM_DQS2 */ - 0x00000008, /* EMC_DLL_XFORM_DQS3 */ - 0x00000008, /* EMC_DLL_XFORM_DQ1 */ - 0x00000008, /* EMC_DLL_XFORM_DQ2 */ - 0x00000008, /* EMC_DLL_XFORM_DQ3 */ + 0x00020000, /* EMC_DLL_XFORM_DQS1 */ + 0x00020000, /* EMC_DLL_XFORM_DQS2 */ + 0x00020000, /* EMC_DLL_XFORM_DQS3 */ + 0x00028000, /* EMC_DLL_XFORM_DQ1 */ + 0x00028000, /* EMC_DLL_XFORM_DQ2 */ + 0x00028000, /* EMC_DLL_XFORM_DQ3 */ 0x00000000, /* EMC_DLI_TRIM_TXDQS1 */ 0x00000000, /* EMC_DLI_TRIM_TXDQS2 */ 0x00000000, /* EMC_DLI_TRIM_TXDQS3 */ @@ -1741,29 +4293,29 @@ static struct tegra11_emc_table p2454_h5tc4g63afr_pba_table[] = { }, { 0x00000000, /* EMC_CDB_CNTL_1 */ - 0x00000004, /* EMC_FBIO_CFG6 */ + 0x00000006, /* EMC_FBIO_CFG6 */ 0x00000007, /* EMC_QUSE */ 0x00000005, /* EMC_EINPUT */ 0x00000004, /* EMC_EINPUT_DURATION */ - 0x00000008, /* EMC_DLL_XFORM_DQS0 */ + 0x00020000, /* EMC_DLL_XFORM_DQS0 */ 0x0000000c, /* EMC_QSAFE */ 0x00000000, /* EMC_DLL_XFORM_QUSE0 */ 0x0000000e, /* EMC_RDV */ - 0x0079e79e, /* EMC_XM2DQSPADCTRL4 */ + 0x00249249, /* EMC_XM2DQSPADCTRL4 */ 0x20820800, /* EMC_XM2DQSPADCTRL3 */ - 0x00000008, /* EMC_DLL_XFORM_DQ0 */ + 0x00028000, /* EMC_DLL_XFORM_DQ0 */ 0xa8f10000, /* EMC_AUTO_CAL_CONFIG */ 0x00000000, /* EMC_DLL_XFORM_ADDR0 */ - 0x00000707, /* EMC_XM2CLKPADCTRL2 */ + 0x00000808, /* EMC_XM2CLKPADCTRL2 */ 0x00000000, /* EMC_DLI_TRIM_TXDQS0 */ 0x00000000, /* EMC_DLL_XFORM_ADDR1 */ 0x00000000, /* EMC_DLL_XFORM_ADDR2 */ - 0x00000008, /* EMC_DLL_XFORM_DQS1 */ - 0x00000008, /* EMC_DLL_XFORM_DQS2 */ - 0x00000008, /* EMC_DLL_XFORM_DQS3 */ - 0x00000008, /* EMC_DLL_XFORM_DQ1 */ - 0x00000008, /* EMC_DLL_XFORM_DQ2 */ - 0x00000008, /* EMC_DLL_XFORM_DQ3 */ + 0x00020000, /* EMC_DLL_XFORM_DQS1 */ + 0x00020000, /* EMC_DLL_XFORM_DQS2 */ + 0x00020000, /* EMC_DLL_XFORM_DQS3 */ + 0x00028000, /* EMC_DLL_XFORM_DQ1 */ + 0x00028000, /* EMC_DLL_XFORM_DQ2 */ + 0x00028000, /* EMC_DLL_XFORM_DQ3 */ 0x00000000, /* EMC_DLI_TRIM_TXDQS1 */ 0x00000000, /* EMC_DLI_TRIM_TXDQS2 */ 0x00000000, /* EMC_DLI_TRIM_TXDQS3 */ @@ -1803,8 +4355,8 @@ static struct tegra11_emc_table p2454_h5tc4g63afr_pba_table[] = { 30, /* number of trim_regs (each channel) */ 11, /* number of up_down_regs */ { - 0x00000017, /* EMC_RC */ - 0x0000007f, /* EMC_RFC */ + 0x00000018, /* EMC_RC */ + 0x00000088, /* EMC_RFC */ 0x00000000, /* EMC_RFC_SLR */ 0x00000010, /* EMC_RAS */ 0x00000006, /* EMC_RP */ @@ -1818,12 +4370,12 @@ static struct tegra11_emc_table p2454_h5tc4g63afr_pba_table[] = { 0x00000001, /* EMC_REXT */ 0x00000000, /* EMC_WEXT */ 0x00000005, /* EMC_WDV */ - 0x00000005, /* EMC_WDV_MASK */ + 0x0000000f, /* EMC_WDV_MASK */ 0x00000009, /* EMC_IBDLY */ 0x00010000, /* EMC_PUTERM_EXTRA */ 0x00000000, /* EMC_CDB_CNTL_2 */ 0x00000006, /* EMC_QRST */ - 0x00000010, /* EMC_RDV_MASK */ + 0x00000012, /* EMC_RDV_MASK */ 0x00000fde, /* EMC_REFRESH */ 0x00000000, /* EMC_BURST_REFRESH_NUM */ 0x000003f7, /* EMC_PRE_REFRESH_REQ_CNT */ @@ -1831,9 +4383,9 @@ static struct tegra11_emc_table p2454_h5tc4g63afr_pba_table[] = { 0x0000000b, /* EMC_PDEX2RD */ 0x00000001, /* EMC_PCHG2PDEN */ 0x00000000, /* EMC_ACT2PDEN */ - 0x0000007c, /* EMC_AR2PDEN */ + 0x00000085, /* EMC_AR2PDEN */ 0x00000012, /* EMC_RW2PDEN */ - 0x00000086, /* EMC_TXSR */ + 0x0000008f, /* EMC_TXSR */ 0x00000200, /* EMC_TXSRDLL */ 0x00000004, /* EMC_TCKE */ 0x00000004, /* EMC_TCKESR */ @@ -1843,16 +4395,16 @@ static struct tegra11_emc_table p2454_h5tc4g63afr_pba_table[] = { 0x00000005, /* EMC_TCLKSTABLE */ 0x00000006, /* EMC_TCLKSTOP */ 0x0000101f, /* EMC_TREFBW */ - 0x00000009, /* EMC_QUSE_EXTRA */ + 0x00000008, /* EMC_QUSE_EXTRA */ 0x00000020, /* EMC_ODT_WRITE */ 0x00000000, /* EMC_ODT_READ */ 0x0000ba88, /* EMC_FBIO_CFG5 */ 0xf0120091, /* EMC_CFG_DIG_DLL */ 0x00008000, /* EMC_CFG_DIG_DLL_PERIOD */ - 0x0000000a, /* EMC_DLL_XFORM_DQS4 */ - 0x0000000a, /* EMC_DLL_XFORM_DQS5 */ - 0x0000000a, /* EMC_DLL_XFORM_DQS6 */ - 0x0000000a, /* EMC_DLL_XFORM_DQS7 */ + 0x00000009, /* EMC_DLL_XFORM_DQS4 */ + 0x00000009, /* EMC_DLL_XFORM_DQS5 */ + 0x00000009, /* EMC_DLL_XFORM_DQS6 */ + 0x00000009, /* EMC_DLL_XFORM_DQS7 */ 0x00000000, /* EMC_DLL_XFORM_QUSE4 */ 0x00000000, /* EMC_DLL_XFORM_QUSE5 */ 0x00000000, /* EMC_DLL_XFORM_QUSE6 */ @@ -1863,11 +4415,11 @@ static struct tegra11_emc_table p2454_h5tc4g63afr_pba_table[] = { 0x00000000, /* EMC_DLI_TRIM_TXDQS7 */ 0x001112a0, /* EMC_XM2CMDPADCTRL */ 0x00000000, /* EMC_XM2CMDPADCTRL4 */ - 0x0003033d, /* EMC_XM2DQSPADCTRL2 */ + 0x0000013d, /* EMC_XM2DQSPADCTRL2 */ 0x00000000, /* EMC_XM2DQPADCTRL2 */ - 0x77ffc084, /* EMC_XM2CLKPADCTRL */ + 0x77ffc085, /* EMC_XM2CLKPADCTRL */ 0x81f1f108, /* EMC_XM2COMPPADCTRL */ - 0x07077704, /* EMC_XM2VTTGENPADCTRL */ + 0x03035504, /* EMC_XM2VTTGENPADCTRL */ 0x00000000, /* EMC_XM2VTTGENPADCTRL2 */ 0x0000003f, /* EMC_DSR_VTTGEN_DRV */ 0x00000000, /* EMC_TXDSRVTTGEN */ @@ -1875,8 +4427,8 @@ static struct tegra11_emc_table p2454_h5tc4g63afr_pba_table[] = { 0x00000802, /* EMC_CTT_TERM_CTRL */ 0x00020000, /* EMC_ZCAL_INTERVAL */ 0x00000100, /* EMC_ZCAL_WAIT_CNT */ - 0x0142000f, /* EMC_MRS_WAIT_CNT */ - 0x0142000f, /* EMC_MRS_WAIT_CNT2 */ + 0x0139000f, /* EMC_MRS_WAIT_CNT */ + 0x0139000f, /* EMC_MRS_WAIT_CNT2 */ 0x00000000, /* EMC_AUTO_CAL_CONFIG2 */ 0x00000000, /* EMC_AUTO_CAL_CONFIG3 */ 0x00000000, /* EMC_CTT */ @@ -1905,26 +4457,26 @@ static struct tegra11_emc_table p2454_h5tc4g63afr_pba_table[] = { }, { 0x00000000, /* EMC_CDB_CNTL_1 */ - 0x00000004, /* EMC_FBIO_CFG6 */ - 0x0000000a, /* EMC_QUSE */ + 0x00000006, /* EMC_FBIO_CFG6 */ + 0x00000009, /* EMC_QUSE */ 0x00000007, /* EMC_EINPUT */ 0x00000004, /* EMC_EINPUT_DURATION */ - 0x0000000a, /* EMC_DLL_XFORM_DQS0 */ + 0x00000009, /* EMC_DLL_XFORM_DQS0 */ 0x0000000c, /* EMC_QSAFE */ 0x00000000, /* EMC_DLL_XFORM_QUSE0 */ 0x00000010, /* EMC_RDV */ - 0x0079e79e, /* EMC_XM2DQSPADCTRL4 */ + 0x00249249, /* EMC_XM2DQSPADCTRL4 */ 0x20820800, /* EMC_XM2DQSPADCTRL3 */ 0x0000000b, /* EMC_DLL_XFORM_DQ0 */ 0xa0f10000, /* EMC_AUTO_CAL_CONFIG */ 0x00000000, /* EMC_DLL_XFORM_ADDR0 */ - 0x00000606, /* EMC_XM2CLKPADCTRL2 */ + 0x00000808, /* EMC_XM2CLKPADCTRL2 */ 0x00000000, /* EMC_DLI_TRIM_TXDQS0 */ 0x00000000, /* EMC_DLL_XFORM_ADDR1 */ 0x00000000, /* EMC_DLL_XFORM_ADDR2 */ - 0x0000000a, /* EMC_DLL_XFORM_DQS1 */ - 0x0000000a, /* EMC_DLL_XFORM_DQS2 */ - 0x0000000a, /* EMC_DLL_XFORM_DQS3 */ + 0x00000009, /* EMC_DLL_XFORM_DQS1 */ + 0x00000009, /* EMC_DLL_XFORM_DQS2 */ + 0x00000009, /* EMC_DLL_XFORM_DQS3 */ 0x0000000b, /* EMC_DLL_XFORM_DQ1 */ 0x0000000b, /* EMC_DLL_XFORM_DQ2 */ 0x0000000b, /* EMC_DLL_XFORM_DQ3 */ @@ -1937,26 +4489,26 @@ static struct tegra11_emc_table p2454_h5tc4g63afr_pba_table[] = { }, { 0x00000000, /* EMC_CDB_CNTL_1 */ - 0x00000004, /* EMC_FBIO_CFG6 */ - 0x0000000a, /* EMC_QUSE */ + 0x00000006, /* EMC_FBIO_CFG6 */ + 0x00000009, /* EMC_QUSE */ 0x00000007, /* EMC_EINPUT */ 0x00000004, /* EMC_EINPUT_DURATION */ - 0x0000000a, /* EMC_DLL_XFORM_DQS0 */ + 0x00000009, /* EMC_DLL_XFORM_DQS0 */ 0x0000000c, /* EMC_QSAFE */ 0x00000000, /* EMC_DLL_XFORM_QUSE0 */ 0x00000010, /* EMC_RDV */ - 0x0079e79e, /* EMC_XM2DQSPADCTRL4 */ + 0x00249249, /* EMC_XM2DQSPADCTRL4 */ 0x20820800, /* EMC_XM2DQSPADCTRL3 */ 0x0000000b, /* EMC_DLL_XFORM_DQ0 */ 0xa8f10000, /* EMC_AUTO_CAL_CONFIG */ 0x00000000, /* EMC_DLL_XFORM_ADDR0 */ - 0x00000707, /* EMC_XM2CLKPADCTRL2 */ + 0x00000808, /* EMC_XM2CLKPADCTRL2 */ 0x00000000, /* EMC_DLI_TRIM_TXDQS0 */ 0x00000000, /* EMC_DLL_XFORM_ADDR1 */ 0x00000000, /* EMC_DLL_XFORM_ADDR2 */ - 0x0000000a, /* EMC_DLL_XFORM_DQS1 */ - 0x0000000a, /* EMC_DLL_XFORM_DQS2 */ - 0x0000000a, /* EMC_DLL_XFORM_DQS3 */ + 0x00000009, /* EMC_DLL_XFORM_DQS1 */ + 0x00000009, /* EMC_DLL_XFORM_DQS2 */ + 0x00000009, /* EMC_DLL_XFORM_DQS3 */ 0x0000000b, /* EMC_DLL_XFORM_DQ1 */ 0x0000000b, /* EMC_DLL_XFORM_DQ2 */ 0x0000000b, /* EMC_DLL_XFORM_DQ3 */ @@ -1993,57 +4545,57 @@ static struct tegra11_emc_table p2454_h5tc4g63afr_pba_table[] = { 0x41, /* Rev 4.0.3 */ 624000, /* SDRAM frequency */ 1100, /* min voltage */ - "pll_m", /* clock source id */ - 0x20000000, /* CLK_SOURCE_EMC */ + "pll_c", /* clock source id */ + 0x24000000, /* CLK_SOURCE_EMC */ 99, /* number of burst_regs */ 30, /* number of trim_regs (each channel) */ 11, /* number of up_down_regs */ { - 0x0000001f, /* EMC_RC */ - 0x000000aa, /* EMC_RFC */ + 0x0000001c, /* EMC_RC */ + 0x000000a1, /* EMC_RFC */ 0x00000000, /* EMC_RFC_SLR */ - 0x00000016, /* EMC_RAS */ - 0x00000008, /* EMC_RP */ + 0x00000014, /* EMC_RAS */ + 0x00000007, /* EMC_RP */ 0x00000007, /* EMC_R2W */ 0x0000000b, /* EMC_W2R */ 0x00000003, /* EMC_R2P */ 0x00000010, /* EMC_W2P */ - 0x00000008, /* EMC_RD_RCD */ - 0x00000008, /* EMC_WR_RCD */ + 0x00000007, /* EMC_RD_RCD */ + 0x00000007, /* EMC_WR_RCD */ 0x00000002, /* EMC_RRD */ 0x00000001, /* EMC_REXT */ 0x00000000, /* EMC_WEXT */ 0x00000005, /* EMC_WDV */ - 0x00000005, /* EMC_WDV_MASK */ + 0x0000000f, /* EMC_WDV_MASK */ 0x0000000b, /* EMC_IBDLY */ - 0x000c000a, /* EMC_PUTERM_EXTRA */ + 0x00010000, /* EMC_PUTERM_EXTRA */ 0x00000000, /* EMC_CDB_CNTL_2 */ 0x00000007, /* EMC_QRST */ - 0x00000012, /* EMC_RDV_MASK */ - 0x000013dc, /* EMC_REFRESH */ + 0x00000013, /* EMC_RDV_MASK */ + 0x000012cb, /* EMC_REFRESH */ 0x00000000, /* EMC_BURST_REFRESH_NUM */ - 0x000004f7, /* EMC_PRE_REFRESH_REQ_CNT */ + 0x000004b2, /* EMC_PRE_REFRESH_REQ_CNT */ 0x00000002, /* EMC_PDEX2WR */ - 0x0000000e, /* EMC_PDEX2RD */ + 0x0000000d, /* EMC_PDEX2RD */ 0x00000001, /* EMC_PCHG2PDEN */ 0x00000000, /* EMC_ACT2PDEN */ 0x000000a5, /* EMC_AR2PDEN */ 0x00000015, /* EMC_RW2PDEN */ - 0x000000b3, /* EMC_TXSR */ + 0x000000a9, /* EMC_TXSR */ 0x00000200, /* EMC_TXSRDLL */ 0x00000005, /* EMC_TCKE */ 0x00000005, /* EMC_TCKESR */ 0x00000005, /* EMC_TPD */ - 0x0000001b, /* EMC_TFAW */ + 0x00000019, /* EMC_TFAW */ 0x00000000, /* EMC_TRPAB */ 0x00000006, /* EMC_TCLKSTABLE */ 0x00000007, /* EMC_TCLKSTOP */ - 0x0000141d, /* EMC_TREFBW */ + 0x0000130b, /* EMC_TREFBW */ 0x00000009, /* EMC_QUSE_EXTRA */ 0x00000020, /* EMC_ODT_WRITE */ 0x00000000, /* EMC_ODT_READ */ - 0x0000b888, /* EMC_FBIO_CFG5 */ - 0xf00c0191, /* EMC_CFG_DIG_DLL */ + 0x0000ba88, /* EMC_FBIO_CFG5 */ + 0xf00d0191, /* EMC_CFG_DIG_DLL */ 0x00008000, /* EMC_CFG_DIG_DLL_PERIOD */ 0x0000000a, /* EMC_DLL_XFORM_DQS4 */ 0x0000000a, /* EMC_DLL_XFORM_DQS5 */ @@ -2059,11 +4611,11 @@ static struct tegra11_emc_table p2454_h5tc4g63afr_pba_table[] = { 0x00000000, /* EMC_DLI_TRIM_TXDQS7 */ 0x001112a0, /* EMC_XM2CMDPADCTRL */ 0x00000000, /* EMC_XM2CMDPADCTRL4 */ - 0x0001013d, /* EMC_XM2DQSPADCTRL2 */ + 0x0000013d, /* EMC_XM2DQSPADCTRL2 */ 0x00000000, /* EMC_XM2DQPADCTRL2 */ - 0x77ffc084, /* EMC_XM2CLKPADCTRL */ + 0x77ffc085, /* EMC_XM2CLKPADCTRL */ 0x81f1f108, /* EMC_XM2COMPPADCTRL */ - 0x07077704, /* EMC_XM2VTTGENPADCTRL */ + 0x07077504, /* EMC_XM2VTTGENPADCTRL */ 0x00000000, /* EMC_XM2VTTGENPADCTRL2 */ 0x0000003f, /* EMC_DSR_VTTGEN_DRV */ 0x00000000, /* EMC_TXDSRVTTGEN */ @@ -2071,22 +4623,22 @@ static struct tegra11_emc_table p2454_h5tc4g63afr_pba_table[] = { 0x00000802, /* EMC_CTT_TERM_CTRL */ 0x00020000, /* EMC_ZCAL_INTERVAL */ 0x00000100, /* EMC_ZCAL_WAIT_CNT */ - 0x0119000c, /* EMC_MRS_WAIT_CNT */ - 0x0119000c, /* EMC_MRS_WAIT_CNT2 */ + 0x0122000f, /* EMC_MRS_WAIT_CNT */ + 0x0122000f, /* EMC_MRS_WAIT_CNT2 */ 0x00000000, /* EMC_AUTO_CAL_CONFIG2 */ 0x00000000, /* EMC_AUTO_CAL_CONFIG3 */ 0x00000000, /* EMC_CTT */ 0x00000000, /* EMC_CTT_DURATION */ - 0x8000283b, /* EMC_DYN_SELF_REF_CONTROL */ + 0x80002626, /* EMC_DYN_SELF_REF_CONTROL */ 0x1f7df7df, /* EMC_CA_TRAINING_TIMING_CNTL1 */ 0x0000001f, /* EMC_CA_TRAINING_TIMING_CNTL2 */ - 0x0e000009, /* MC_EMEM_ARB_CFG */ + 0x06000009, /* MC_EMEM_ARB_CFG */ 0x80000190, /* MC_EMEM_ARB_OUTSTANDING_REQ */ 0x00000003, /* MC_EMEM_ARB_TIMING_RCD */ 0x00000004, /* MC_EMEM_ARB_TIMING_RP */ - 0x00000010, /* MC_EMEM_ARB_TIMING_RC */ - 0x0000000a, /* MC_EMEM_ARB_TIMING_RAS */ - 0x0000000d, /* MC_EMEM_ARB_TIMING_FAW */ + 0x0000000f, /* MC_EMEM_ARB_TIMING_RC */ + 0x00000009, /* MC_EMEM_ARB_TIMING_RAS */ + 0x0000000c, /* MC_EMEM_ARB_TIMING_FAW */ 0x00000001, /* MC_EMEM_ARB_TIMING_RRD */ 0x00000003, /* MC_EMEM_ARB_TIMING_RAP2PRE */ 0x0000000b, /* MC_EMEM_ARB_TIMING_WAP2PRE */ @@ -2095,8 +4647,8 @@ static struct tegra11_emc_table p2454_h5tc4g63afr_pba_table[] = { 0x00000005, /* MC_EMEM_ARB_TIMING_R2W */ 0x00000007, /* MC_EMEM_ARB_TIMING_W2R */ 0x07050202, /* MC_EMEM_ARB_DA_TURNS */ - 0x00140c10, /* MC_EMEM_ARB_DA_COVERS */ - 0x736a1e11, /* MC_EMEM_ARB_MISC0 */ + 0x00130b0f, /* MC_EMEM_ARB_DA_COVERS */ + 0x736a1d10, /* MC_EMEM_ARB_MISC0 */ 0x001f0000, /* MC_EMEM_ARB_RING1_THROTTLE */ }, { @@ -2108,22 +4660,22 @@ static struct tegra11_emc_table p2454_h5tc4g63afr_pba_table[] = { 0x0000000a, /* EMC_DLL_XFORM_DQS0 */ 0x0000000c, /* EMC_QSAFE */ 0x00000000, /* EMC_DLL_XFORM_QUSE0 */ - 0x00000012, /* EMC_RDV */ - 0x00208208, /* EMC_XM2DQSPADCTRL4 */ - 0x18618620, /* EMC_XM2DQSPADCTRL3 */ - 0x007fc00a, /* EMC_DLL_XFORM_DQ0 */ + 0x00000011, /* EMC_RDV */ + 0x00249249, /* EMC_XM2DQSPADCTRL4 */ + 0x20820800, /* EMC_XM2DQSPADCTRL3 */ + 0x0000000b, /* EMC_DLL_XFORM_DQ0 */ 0xa0f10000, /* EMC_AUTO_CAL_CONFIG */ - 0x0000000a, /* EMC_DLL_XFORM_ADDR0 */ - 0x00000909, /* EMC_XM2CLKPADCTRL2 */ + 0x00000000, /* EMC_DLL_XFORM_ADDR0 */ + 0x00000808, /* EMC_XM2CLKPADCTRL2 */ 0x00000000, /* EMC_DLI_TRIM_TXDQS0 */ - 0x0000000a, /* EMC_DLL_XFORM_ADDR1 */ - 0x0000000a, /* EMC_DLL_XFORM_ADDR2 */ + 0x00000000, /* EMC_DLL_XFORM_ADDR1 */ + 0x00000000, /* EMC_DLL_XFORM_ADDR2 */ 0x0000000a, /* EMC_DLL_XFORM_DQS1 */ 0x0000000a, /* EMC_DLL_XFORM_DQS2 */ 0x0000000a, /* EMC_DLL_XFORM_DQS3 */ - 0x007fc00a, /* EMC_DLL_XFORM_DQ1 */ - 0x007fc00a, /* EMC_DLL_XFORM_DQ2 */ - 0x007fc00a, /* EMC_DLL_XFORM_DQ3 */ + 0x0000000a, /* EMC_DLL_XFORM_DQ1 */ + 0x0000000b, /* EMC_DLL_XFORM_DQ2 */ + 0x0000000b, /* EMC_DLL_XFORM_DQ3 */ 0x00000000, /* EMC_DLI_TRIM_TXDQS1 */ 0x00000000, /* EMC_DLI_TRIM_TXDQS2 */ 0x00000000, /* EMC_DLI_TRIM_TXDQS3 */ @@ -2140,22 +4692,22 @@ static struct tegra11_emc_table p2454_h5tc4g63afr_pba_table[] = { 0x0000000a, /* EMC_DLL_XFORM_DQS0 */ 0x0000000c, /* EMC_QSAFE */ 0x00000000, /* EMC_DLL_XFORM_QUSE0 */ - 0x00000012, /* EMC_RDV */ - 0x00208208, /* EMC_XM2DQSPADCTRL4 */ - 0x18618620, /* EMC_XM2DQSPADCTRL3 */ - 0x007fc00a, /* EMC_DLL_XFORM_DQ0 */ + 0x00000011, /* EMC_RDV */ + 0x00249249, /* EMC_XM2DQSPADCTRL4 */ + 0x20820800, /* EMC_XM2DQSPADCTRL3 */ + 0x0000000a, /* EMC_DLL_XFORM_DQ0 */ 0xa8f10000, /* EMC_AUTO_CAL_CONFIG */ - 0x0000000a, /* EMC_DLL_XFORM_ADDR0 */ - 0x00000909, /* EMC_XM2CLKPADCTRL2 */ + 0x00000000, /* EMC_DLL_XFORM_ADDR0 */ + 0x00000808, /* EMC_XM2CLKPADCTRL2 */ 0x00000000, /* EMC_DLI_TRIM_TXDQS0 */ - 0x0000000a, /* EMC_DLL_XFORM_ADDR1 */ - 0x0000000a, /* EMC_DLL_XFORM_ADDR2 */ + 0x00000000, /* EMC_DLL_XFORM_ADDR1 */ + 0x00000000, /* EMC_DLL_XFORM_ADDR2 */ 0x0000000a, /* EMC_DLL_XFORM_DQS1 */ 0x0000000a, /* EMC_DLL_XFORM_DQS2 */ 0x0000000a, /* EMC_DLL_XFORM_DQS3 */ - 0x007fc00a, /* EMC_DLL_XFORM_DQ1 */ - 0x007fc00a, /* EMC_DLL_XFORM_DQ2 */ - 0x007fc00a, /* EMC_DLL_XFORM_DQ3 */ + 0x0000000a, /* EMC_DLL_XFORM_DQ1 */ + 0x0000000a, /* EMC_DLL_XFORM_DQ2 */ + 0x0000000a, /* EMC_DLL_XFORM_DQ3 */ 0x00000000, /* EMC_DLI_TRIM_TXDQS1 */ 0x00000000, /* EMC_DLI_TRIM_TXDQS2 */ 0x00000000, /* EMC_DLI_TRIM_TXDQS3 */ @@ -2178,7 +4730,7 @@ static struct tegra11_emc_table p2454_h5tc4g63afr_pba_table[] = { }, 0x00000042, /* EMC_ZCAL_WAIT_CNT after clock change */ 0x001fffff, /* EMC_AUTO_CAL_INTERVAL */ - 0x53100000, /* EMC_CFG */ + 0x53200000, /* EMC_CFG */ 0x80000b61, /* Mode Register 0 */ 0x80100002, /* Mode Register 1 */ 0x80200010, /* Mode Register 2 */ @@ -2195,7 +4747,7 @@ static struct tegra11_emc_table p2454_h5tc4g63afr_pba_table[] = { 30, /* number of trim_regs (each channel) */ 11, /* number of up_down_regs */ { - 0x00000024, /* EMC_RC */ + 0x00000025, /* EMC_RC */ 0x000000cd, /* EMC_RFC */ 0x00000000, /* EMC_RFC_SLR */ 0x00000019, /* EMC_RAS */ @@ -2210,22 +4762,22 @@ static struct tegra11_emc_table p2454_h5tc4g63afr_pba_table[] = { 0x00000001, /* EMC_REXT */ 0x00000000, /* EMC_WEXT */ 0x00000006, /* EMC_WDV */ - 0x00000006, /* EMC_WDV_MASK */ - 0x0000000b, /* EMC_IBDLY */ + 0x0000000f, /* EMC_WDV_MASK */ + 0x0000000c, /* EMC_IBDLY */ 0x000d000a, /* EMC_PUTERM_EXTRA */ 0x00000000, /* EMC_CDB_CNTL_2 */ - 0x00000008, /* EMC_QRST */ - 0x00000014, /* EMC_RDV_MASK */ - 0x000017e4, /* EMC_REFRESH */ + 0x00000009, /* EMC_QRST */ + 0x00000016, /* EMC_RDV_MASK */ + 0x000017ee, /* EMC_REFRESH */ 0x00000000, /* EMC_BURST_REFRESH_NUM */ - 0x000005f9, /* EMC_PRE_REFRESH_REQ_CNT */ + 0x000005fb, /* EMC_PRE_REFRESH_REQ_CNT */ 0x00000003, /* EMC_PDEX2WR */ 0x00000012, /* EMC_PDEX2RD */ 0x00000001, /* EMC_PCHG2PDEN */ 0x00000000, /* EMC_ACT2PDEN */ 0x000000c6, /* EMC_AR2PDEN */ 0x00000018, /* EMC_RW2PDEN */ - 0x000000d6, /* EMC_TXSR */ + 0x000000d7, /* EMC_TXSR */ 0x00000200, /* EMC_TXSRDLL */ 0x00000005, /* EMC_TCKE */ 0x00000005, /* EMC_TCKESR */ @@ -2234,17 +4786,17 @@ static struct tegra11_emc_table p2454_h5tc4g63afr_pba_table[] = { 0x00000000, /* EMC_TRPAB */ 0x00000007, /* EMC_TCLKSTABLE */ 0x00000008, /* EMC_TCLKSTOP */ - 0x00001825, /* EMC_TREFBW */ - 0x0000000a, /* EMC_QUSE_EXTRA */ - 0x80000020, /* EMC_ODT_WRITE */ + 0x0000182f, /* EMC_TREFBW */ + 0x0000000b, /* EMC_QUSE_EXTRA */ + 0x80000000, /* EMC_ODT_WRITE */ 0x00000000, /* EMC_ODT_READ */ 0x0000ba88, /* EMC_FBIO_CFG5 */ 0xf0070191, /* EMC_CFG_DIG_DLL */ 0x00008000, /* EMC_CFG_DIG_DLL_PERIOD */ - 0x00004008, /* EMC_DLL_XFORM_DQS4 */ - 0x00004008, /* EMC_DLL_XFORM_DQS5 */ - 0x00004008, /* EMC_DLL_XFORM_DQS6 */ - 0x00004008, /* EMC_DLL_XFORM_DQS7 */ + 0x00000008, /* EMC_DLL_XFORM_DQS4 */ + 0x00000008, /* EMC_DLL_XFORM_DQS5 */ + 0x00000008, /* EMC_DLL_XFORM_DQS6 */ + 0x00000008, /* EMC_DLL_XFORM_DQS7 */ 0x00000000, /* EMC_DLL_XFORM_QUSE4 */ 0x00000000, /* EMC_DLL_XFORM_QUSE5 */ 0x00000000, /* EMC_DLL_XFORM_QUSE6 */ @@ -2257,7 +4809,7 @@ static struct tegra11_emc_table p2454_h5tc4g63afr_pba_table[] = { 0x00000000, /* EMC_XM2CMDPADCTRL4 */ 0x0000013d, /* EMC_XM2DQSPADCTRL2 */ 0x00000000, /* EMC_XM2DQPADCTRL2 */ - 0x77ffc084, /* EMC_XM2CLKPADCTRL */ + 0x77ffc085, /* EMC_XM2CLKPADCTRL */ 0x81f1f508, /* EMC_XM2COMPPADCTRL */ 0x07076604, /* EMC_XM2VTTGENPADCTRL */ 0x00000000, /* EMC_XM2VTTGENPADCTRL2 */ @@ -2273,7 +4825,7 @@ static struct tegra11_emc_table p2454_h5tc4g63afr_pba_table[] = { 0x00000000, /* EMC_AUTO_CAL_CONFIG3 */ 0x00000000, /* EMC_CTT */ 0x00000000, /* EMC_CTT_DURATION */ - 0x80003018, /* EMC_DYN_SELF_REF_CONTROL */ + 0x8000302b, /* EMC_DYN_SELF_REF_CONTROL */ 0x1f7df7df, /* EMC_CA_TRAINING_TIMING_CNTL1 */ 0x0000001f, /* EMC_CA_TRAINING_TIMING_CNTL2 */ 0x0e00000b, /* MC_EMEM_ARB_CFG */ @@ -2298,25 +4850,25 @@ static struct tegra11_emc_table p2454_h5tc4g63afr_pba_table[] = { { 0x00000000, /* EMC_CDB_CNTL_1 */ 0x00000006, /* EMC_FBIO_CFG6 */ - 0x0000000b, /* EMC_QUSE */ - 0x00000008, /* EMC_EINPUT */ - 0x00000006, /* EMC_EINPUT_DURATION */ - 0x00004008, /* EMC_DLL_XFORM_DQS0 */ + 0x0000000d, /* EMC_QUSE */ + 0x0000000a, /* EMC_EINPUT */ + 0x00000005, /* EMC_EINPUT_DURATION */ + 0x00000008, /* EMC_DLL_XFORM_DQS0 */ 0x0000000d, /* EMC_QSAFE */ 0x00000000, /* EMC_DLL_XFORM_QUSE0 */ - 0x00000014, /* EMC_RDV */ + 0x00000015, /* EMC_RDV */ 0x00249249, /* EMC_XM2DQSPADCTRL4 */ - 0x10410400, /* EMC_XM2DQSPADCTRL3 */ + 0x20820800, /* EMC_XM2DQSPADCTRL3 */ 0x0000000a, /* EMC_DLL_XFORM_DQ0 */ 0xa0f10f0f, /* EMC_AUTO_CAL_CONFIG */ - 0x0000000a, /* EMC_DLL_XFORM_ADDR0 */ - 0x00000b0b, /* EMC_XM2CLKPADCTRL2 */ + 0x00004000, /* EMC_DLL_XFORM_ADDR0 */ + 0x00000a0a, /* EMC_XM2CLKPADCTRL2 */ 0x00000000, /* EMC_DLI_TRIM_TXDQS0 */ - 0x0000000a, /* EMC_DLL_XFORM_ADDR1 */ - 0x0000000a, /* EMC_DLL_XFORM_ADDR2 */ - 0x00004008, /* EMC_DLL_XFORM_DQS1 */ - 0x00004008, /* EMC_DLL_XFORM_DQS2 */ - 0x00004008, /* EMC_DLL_XFORM_DQS3 */ + 0x00000000, /* EMC_DLL_XFORM_ADDR1 */ + 0x00004000, /* EMC_DLL_XFORM_ADDR2 */ + 0x00000008, /* EMC_DLL_XFORM_DQS1 */ + 0x00000008, /* EMC_DLL_XFORM_DQS2 */ + 0x00000008, /* EMC_DLL_XFORM_DQS3 */ 0x0000000a, /* EMC_DLL_XFORM_DQ1 */ 0x0000000c, /* EMC_DLL_XFORM_DQ2 */ 0x0000000a, /* EMC_DLL_XFORM_DQ3 */ @@ -2330,25 +4882,25 @@ static struct tegra11_emc_table p2454_h5tc4g63afr_pba_table[] = { { 0x00000000, /* EMC_CDB_CNTL_1 */ 0x00000006, /* EMC_FBIO_CFG6 */ - 0x0000000b, /* EMC_QUSE */ - 0x00000008, /* EMC_EINPUT */ - 0x00000006, /* EMC_EINPUT_DURATION */ - 0x00004008, /* EMC_DLL_XFORM_DQS0 */ + 0x0000000d, /* EMC_QUSE */ + 0x0000000a, /* EMC_EINPUT */ + 0x00000005, /* EMC_EINPUT_DURATION */ + 0x00000008, /* EMC_DLL_XFORM_DQS0 */ 0x0000000d, /* EMC_QSAFE */ 0x00000000, /* EMC_DLL_XFORM_QUSE0 */ - 0x00000014, /* EMC_RDV */ + 0x00000015, /* EMC_RDV */ 0x00249249, /* EMC_XM2DQSPADCTRL4 */ - 0x10410400, /* EMC_XM2DQSPADCTRL3 */ + 0x20820800, /* EMC_XM2DQSPADCTRL3 */ 0x0000000a, /* EMC_DLL_XFORM_DQ0 */ 0xa8f10f0f, /* EMC_AUTO_CAL_CONFIG */ - 0x0000000a, /* EMC_DLL_XFORM_ADDR0 */ - 0x00000b0b, /* EMC_XM2CLKPADCTRL2 */ + 0x00004000, /* EMC_DLL_XFORM_ADDR0 */ + 0x00000a0a, /* EMC_XM2CLKPADCTRL2 */ 0x00000000, /* EMC_DLI_TRIM_TXDQS0 */ - 0x0000000a, /* EMC_DLL_XFORM_ADDR1 */ - 0x0000000a, /* EMC_DLL_XFORM_ADDR2 */ - 0x00004008, /* EMC_DLL_XFORM_DQS1 */ - 0x00004008, /* EMC_DLL_XFORM_DQS2 */ - 0x00004008, /* EMC_DLL_XFORM_DQS3 */ + 0x00000000, /* EMC_DLL_XFORM_ADDR1 */ + 0x00004000, /* EMC_DLL_XFORM_ADDR2 */ + 0x00000008, /* EMC_DLL_XFORM_DQS1 */ + 0x00000008, /* EMC_DLL_XFORM_DQS2 */ + 0x00000008, /* EMC_DLL_XFORM_DQS3 */ 0x0000000a, /* EMC_DLL_XFORM_DQ1 */ 0x0000000c, /* EMC_DLL_XFORM_DQ2 */ 0x0000000a, /* EMC_DLL_XFORM_DQ3 */ @@ -2374,8 +4926,8 @@ static struct tegra11_emc_table p2454_h5tc4g63afr_pba_table[] = { }, 0x00000042, /* EMC_ZCAL_WAIT_CNT after clock change */ 0x001fffff, /* EMC_AUTO_CAL_INTERVAL */ - 0x53100000, /* EMC_CFG */ - 0x80000d71, /* Mode Register 0 */ + 0x53300000, /* EMC_CFG */ + 0x80000d05, /* Mode Register 0 */ 0x80100002, /* Mode Register 1 */ 0x80200418, /* Mode Register 2 */ 0x00000000, /* Mode Register 4 */ @@ -2391,51 +4943,51 @@ static struct tegra11_emc_table p2454_h5tc4g63afr_pba_table[] = { 30, /* number of trim_regs (each channel) */ 11, /* number of up_down_regs */ { - 0x0000002b, /* EMC_RC */ - 0x000000f1, /* EMC_RFC */ + 0x0000002a, /* EMC_RC */ + 0x000000e9, /* EMC_RFC */ 0x00000000, /* EMC_RFC_SLR */ - 0x0000001e, /* EMC_RAS */ + 0x0000001d, /* EMC_RAS */ 0x0000000b, /* EMC_RP */ - 0x00000009, /* EMC_R2W */ + 0x00000008, /* EMC_R2W */ 0x0000000f, /* EMC_W2R */ 0x00000005, /* EMC_R2P */ - 0x00000018, /* EMC_W2P */ + 0x00000016, /* EMC_W2P */ 0x0000000b, /* EMC_RD_RCD */ 0x0000000b, /* EMC_WR_RCD */ 0x00000004, /* EMC_RRD */ 0x00000001, /* EMC_REXT */ 0x00000000, /* EMC_WEXT */ 0x00000007, /* EMC_WDV */ - 0x00000007, /* EMC_WDV_MASK */ + 0x0000000f, /* EMC_WDV_MASK */ 0x0000000d, /* EMC_IBDLY */ - 0x000f000c, /* EMC_PUTERM_EXTRA */ + 0x00010000, /* EMC_PUTERM_EXTRA */ 0x00000000, /* EMC_CDB_CNTL_2 */ 0x0000000a, /* EMC_QRST */ - 0x00000016, /* EMC_RDV_MASK */ - 0x00001c39, /* EMC_REFRESH */ + 0x00000017, /* EMC_RDV_MASK */ + 0x00001b33, /* EMC_REFRESH */ 0x00000000, /* EMC_BURST_REFRESH_NUM */ - 0x0000070e, /* EMC_PRE_REFRESH_REQ_CNT */ + 0x000006cc, /* EMC_PRE_REFRESH_REQ_CNT */ 0x00000004, /* EMC_PDEX2WR */ - 0x00000015, /* EMC_PDEX2RD */ + 0x00000014, /* EMC_PDEX2RD */ 0x00000001, /* EMC_PCHG2PDEN */ 0x00000000, /* EMC_ACT2PDEN */ - 0x000000e8, /* EMC_AR2PDEN */ - 0x0000001d, /* EMC_RW2PDEN */ - 0x000000fd, /* EMC_TXSR */ + 0x000000e0, /* EMC_AR2PDEN */ + 0x0000001b, /* EMC_RW2PDEN */ + 0x000000f4, /* EMC_TXSR */ 0x00000200, /* EMC_TXSRDLL */ 0x00000006, /* EMC_TCKE */ 0x00000006, /* EMC_TCKESR */ 0x00000006, /* EMC_TPD */ - 0x00000026, /* EMC_TFAW */ + 0x00000025, /* EMC_TFAW */ 0x00000000, /* EMC_TRPAB */ - 0x00000009, /* EMC_TCLKSTABLE */ - 0x0000000a, /* EMC_TCLKSTOP */ - 0x00001c7a, /* EMC_TREFBW */ + 0x00000008, /* EMC_TCLKSTABLE */ + 0x00000009, /* EMC_TCLKSTOP */ + 0x00001b74, /* EMC_TREFBW */ 0x00000000, /* EMC_QUSE_EXTRA */ - 0x80000020, /* EMC_ODT_WRITE */ + 0x80000000, /* EMC_ODT_WRITE */ 0x00000000, /* EMC_ODT_READ */ 0x00005088, /* EMC_FBIO_CFG5 */ - 0xf0030191, /* EMC_CFG_DIG_DLL */ + 0xf0040191, /* EMC_CFG_DIG_DLL */ 0x00008000, /* EMC_CFG_DIG_DLL_PERIOD */ 0x00000008, /* EMC_DLL_XFORM_DQS4 */ 0x00000008, /* EMC_DLL_XFORM_DQS5 */ @@ -2460,35 +5012,35 @@ static struct tegra11_emc_table p2454_h5tc4g63afr_pba_table[] = { 0x0000003f, /* EMC_DSR_VTTGEN_DRV */ 0x00000000, /* EMC_TXDSRVTTGEN */ 0x02000000, /* EMC_FBIO_SPARE */ - 0x00000801, /* EMC_CTT_TERM_CTRL */ + 0x00000802, /* EMC_CTT_TERM_CTRL */ 0x00020000, /* EMC_ZCAL_INTERVAL */ 0x00000120, /* EMC_ZCAL_WAIT_CNT */ - 0x00cb000f, /* EMC_MRS_WAIT_CNT */ - 0x00cb000f, /* EMC_MRS_WAIT_CNT2 */ + 0x00d5000f, /* EMC_MRS_WAIT_CNT */ + 0x00d5000f, /* EMC_MRS_WAIT_CNT2 */ 0x00000000, /* EMC_AUTO_CAL_CONFIG2 */ 0x00000000, /* EMC_AUTO_CAL_CONFIG3 */ - 0x00000004, /* EMC_CTT */ - 0x00000004, /* EMC_CTT_DURATION */ - 0x8000388a, /* EMC_DYN_SELF_REF_CONTROL */ + 0x00000000, /* EMC_CTT */ + 0x00000000, /* EMC_CTT_DURATION */ + 0x8000368a, /* EMC_DYN_SELF_REF_CONTROL */ 0x1f7df7df, /* EMC_CA_TRAINING_TIMING_CNTL1 */ 0x0000001f, /* EMC_CA_TRAINING_TIMING_CNTL2 */ - 0x0000000e, /* MC_EMEM_ARB_CFG */ + 0x0800000d, /* MC_EMEM_ARB_CFG */ 0x80000190, /* MC_EMEM_ARB_OUTSTANDING_REQ */ 0x00000005, /* MC_EMEM_ARB_TIMING_RCD */ 0x00000006, /* MC_EMEM_ARB_TIMING_RP */ - 0x00000016, /* MC_EMEM_ARB_TIMING_RC */ + 0x00000015, /* MC_EMEM_ARB_TIMING_RC */ 0x0000000e, /* MC_EMEM_ARB_TIMING_RAS */ 0x00000012, /* MC_EMEM_ARB_TIMING_FAW */ 0x00000002, /* MC_EMEM_ARB_TIMING_RRD */ 0x00000004, /* MC_EMEM_ARB_TIMING_RAP2PRE */ - 0x0000000f, /* MC_EMEM_ARB_TIMING_WAP2PRE */ + 0x0000000e, /* MC_EMEM_ARB_TIMING_WAP2PRE */ 0x00000002, /* MC_EMEM_ARB_TIMING_R2R */ 0x00000002, /* MC_EMEM_ARB_TIMING_W2W */ 0x00000006, /* MC_EMEM_ARB_TIMING_R2W */ 0x00000009, /* MC_EMEM_ARB_TIMING_W2R */ 0x09060202, /* MC_EMEM_ARB_DA_TURNS */ - 0x001b1016, /* MC_EMEM_ARB_DA_COVERS */ - 0x734f2b17, /* MC_EMEM_ARB_MISC0 */ + 0x001a1015, /* MC_EMEM_ARB_DA_COVERS */ + 0x734e2916, /* MC_EMEM_ARB_MISC0 */ 0x001f0000, /* MC_EMEM_ARB_RING1_THROTTLE */ }, { @@ -2500,22 +5052,22 @@ static struct tegra11_emc_table p2454_h5tc4g63afr_pba_table[] = { 0x00000008, /* EMC_DLL_XFORM_DQS0 */ 0x0000000d, /* EMC_QSAFE */ 0x00018007, /* EMC_DLL_XFORM_QUSE0 */ - 0x00000016, /* EMC_RDV */ + 0x00000015, /* EMC_RDV */ 0x00249249, /* EMC_XM2DQSPADCTRL4 */ - 0x10410400, /* EMC_XM2DQSPADCTRL3 */ - 0x00004008, /* EMC_DLL_XFORM_DQ0 */ + 0x20820800, /* EMC_XM2DQSPADCTRL3 */ + 0x00008008, /* EMC_DLL_XFORM_DQ0 */ 0xa0f10202, /* EMC_AUTO_CAL_CONFIG */ 0x00000000, /* EMC_DLL_XFORM_ADDR0 */ - 0x00000f0f, /* EMC_XM2CLKPADCTRL2 */ + 0x00000a0a, /* EMC_XM2CLKPADCTRL2 */ 0x00000000, /* EMC_DLI_TRIM_TXDQS0 */ 0x00000000, /* EMC_DLL_XFORM_ADDR1 */ 0x00000000, /* EMC_DLL_XFORM_ADDR2 */ 0x00000008, /* EMC_DLL_XFORM_DQS1 */ 0x00000008, /* EMC_DLL_XFORM_DQS2 */ 0x00000008, /* EMC_DLL_XFORM_DQS3 */ - 0x00004008, /* EMC_DLL_XFORM_DQ1 */ - 0x00004008, /* EMC_DLL_XFORM_DQ2 */ - 0x00004008, /* EMC_DLL_XFORM_DQ3 */ + 0x00000008, /* EMC_DLL_XFORM_DQ1 */ + 0x00008008, /* EMC_DLL_XFORM_DQ2 */ + 0x00008008, /* EMC_DLL_XFORM_DQ3 */ 0x00000000, /* EMC_DLI_TRIM_TXDQS1 */ 0x00000000, /* EMC_DLI_TRIM_TXDQS2 */ 0x00000000, /* EMC_DLI_TRIM_TXDQS3 */ @@ -2532,22 +5084,22 @@ static struct tegra11_emc_table p2454_h5tc4g63afr_pba_table[] = { 0x00000008, /* EMC_DLL_XFORM_DQS0 */ 0x0000000d, /* EMC_QSAFE */ 0x00018007, /* EMC_DLL_XFORM_QUSE0 */ - 0x00000016, /* EMC_RDV */ + 0x00000015, /* EMC_RDV */ 0x00249249, /* EMC_XM2DQSPADCTRL4 */ - 0x10410400, /* EMC_XM2DQSPADCTRL3 */ - 0x00004008, /* EMC_DLL_XFORM_DQ0 */ + 0x20820800, /* EMC_XM2DQSPADCTRL3 */ + 0x00008008, /* EMC_DLL_XFORM_DQ0 */ 0xa8f10f0f, /* EMC_AUTO_CAL_CONFIG */ 0x00000000, /* EMC_DLL_XFORM_ADDR0 */ - 0x00000b0b, /* EMC_XM2CLKPADCTRL2 */ + 0x00000a0a, /* EMC_XM2CLKPADCTRL2 */ 0x00000000, /* EMC_DLI_TRIM_TXDQS0 */ 0x00000000, /* EMC_DLL_XFORM_ADDR1 */ 0x00000000, /* EMC_DLL_XFORM_ADDR2 */ 0x00000008, /* EMC_DLL_XFORM_DQS1 */ 0x00000008, /* EMC_DLL_XFORM_DQS2 */ 0x00000008, /* EMC_DLL_XFORM_DQS3 */ - 0x00004008, /* EMC_DLL_XFORM_DQ1 */ - 0x00004008, /* EMC_DLL_XFORM_DQ2 */ - 0x00004008, /* EMC_DLL_XFORM_DQ3 */ + 0x00000008, /* EMC_DLL_XFORM_DQ1 */ + 0x00008008, /* EMC_DLL_XFORM_DQ2 */ + 0x00008008, /* EMC_DLL_XFORM_DQ3 */ 0x00000000, /* EMC_DLI_TRIM_TXDQS1 */ 0x00000000, /* EMC_DLI_TRIM_TXDQS2 */ 0x00000000, /* EMC_DLI_TRIM_TXDQS3 */ @@ -2568,10 +5120,10 @@ static struct tegra11_emc_table p2454_h5tc4g63afr_pba_table[] = { 0x0060002d, /* MC_LATENCY_ALLOWANCE_EPP_0 */ 0x00600060, /* MC_LATENCY_ALLOWANCE_EPP_1 */ }, - 0x0000004d, /* EMC_ZCAL_WAIT_CNT after clock change */ + 0x0000004b, /* EMC_ZCAL_WAIT_CNT after clock change */ 0x001fffff, /* EMC_AUTO_CAL_INTERVAL */ 0x53000000, /* EMC_CFG */ - 0x80000115, /* Mode Register 0 */ + 0x80000f15, /* Mode Register 0 */ 0x80100002, /* Mode Register 1 */ 0x80200420, /* Mode Register 2 */ 0x00000000, /* Mode Register 4 */ @@ -2585,9 +5137,22 @@ static struct tegra11_emc_pdata p2454_h5tc4g63afr_pba_pdata = { .num_tables = ARRAY_SIZE(p2454_h5tc4g63afr_pba_table), }; +static struct tegra11_emc_pdata p2560_h5tc4g63afr_pba_pdata = { + .description = "p2560_h5tc4g63afr_pba", + .tables = p2560_h5tc4g63afr_pba_table, + .num_tables = ARRAY_SIZE(p2560_h5tc4g63afr_pba_table), +}; + static struct tegra11_emc_pdata *roth_get_emc_data(void) { - return &p2454_h5tc4g63afr_pba_pdata; + struct board_info board_info; + + tegra_get_board_info(&board_info); + + if (board_info.board_id == BOARD_P2560) + return &p2560_h5tc4g63afr_pba_pdata; + else + return &p2454_h5tc4g63afr_pba_pdata; } int __init roth_emc_init(void) |