ARM: tegra: power: Set Tegra3 CPU/core rail nominal voltage

For different Tegra3 process corners/skus/revisions/boards set nominal
voltages for CPU and core rails as well as adjust maximum clock rates
as follows.

- VDD_CORE rail nominal voltage: default value is indexed by speedo_id
of the chip (speedo_id is determined by chip sku and revision). Minimum
of the default and board specific electrical design voltage is rounded
down against core dvfs voltage ladder. The result is set as nominal
core voltage (edp voltage API is not implemented, yet).

- VDD_CPU rail nominal voltage: default value is indexed by speedo_id
of the chip. If too high, it is lowered to core nominal voltage so that
core_on_cpu dependency is resolved at nominal core level. The result is
compared with voltage required to reach CPU maximum rate as specified
in the dvfs table for the particular process corner. Again, the minimal
level is selected, and finally set as CPU nominal voltage.

After nominal voltages are determined, maximum rate for each dvfs clock
is adjusted accordingly, so that it does not exceed the rate specified
in the respective DVFS table at nominal level.

Original-Change-Id: Ia6c1c5c853f98ab185f42bf1cfd7a1d7d54d10c3
Reviewed-on: http://git-master/r/30928
Reviewed-by: Aleksandr Frid <afrid@nvidia.com>
Tested-by: Aleksandr Frid <afrid@nvidia.com>
Reviewed-by: Scott Williams <scwilliams@nvidia.com>
Reviewed-by: Diwakar Tundlam <dtundlam@nvidia.com>
Tested-by: Diwakar Tundlam <dtundlam@nvidia.com>
Reviewed-by: Narendra Damahe <ndamahe@nvidia.com>

Rebase-Id: R30393515042d199154ba708afaefb134402f551a

1 files changed, 18 insertions, 0 deletions

diff --git a/arch/arm/mach-tegra/clock.c b/arch/arm/mach-tegra/clock.c
index 9be8adf76437..992ca733276e 100644
--- a/arch/arm/mach-tegra/clock.c
+++ b/arch/arm/mach-tegra/clock.c
@@ -597,6 +597,24 @@ out:
 	return ret;
 }
 
+/* dvfs initialization may lower default maximum rate */
+void __init tegra_init_max_rate(struct clk *c, unsigned long max_rate)
+{
+	struct clk *shared_bus_user;
+
+	if (c->max_rate <= max_rate)
+		return;
+
+	pr_warning("Lowering %s maximum rate from %lu to %lu\n",
+		c->name, c->max_rate, max_rate);
+
+	c->max_rate = max_rate;
+	list_for_each_entry(shared_bus_user,
+			    &c->shared_bus_list, u.shared_bus_user.node) {
+		shared_bus_user->max_rate = max_rate;
+	}
+}
+
 static bool tegra_keep_boot_clocks = false;
 static int __init tegra_keep_boot_clocks_setup(char *__unused)
 {