ARM: tegra: clock: Re-factor extended clock operations

Re-factored extended clock operations to enumerate configuration
parameters.

Original-Change-Id: I6c1e5f07803a8e6da0ebd6690892f50bb59efcd5
Reviewed-on: http://git-master/r/15144
Tested-by: Aleksandr Frid <afrid@nvidia.com>
Reviewed-by: Jonathan Mayo <jmayo@nvidia.com>
Reviewed-by: Jin Qian <jqian@nvidia.com>
Reviewed-by: Scott Williams <scwilliams@nvidia.com>
Original-Change-Id: I25147998969b385905bad5eb3ceb2dbb89c0d93a

Rebase-Id: R815ccca27fac9a0af334c188ce77e0ec4fdad9b2

1 files changed, 14 insertions, 14 deletions

diff --git a/arch/arm/mach-tegra/clock.c b/arch/arm/mach-tegra/clock.c
index b29002b2d7d2..e4b3679029b1 100644
--- a/arch/arm/mach-tegra/clock.c
+++ b/arch/arm/mach-tegra/clock.c
@@ -507,22 +507,19 @@ void __init tegra_init_clock(void)
 	tegra_soc_init_dvfs();
 }
 
-/*
- * The SDMMC controllers have extra bits in the clock source register that
- * adjust the delay between the clock and data to compenstate for delays
- * on the PCB.
- */
-void tegra_sdmmc_tap_delay(struct clk *c, int delay)
-{
+#ifdef CONFIG_ARCH_TEGRA_2x_SOC
+/* On tegra 2 SoC the SDMMC clock source register have extra bits that
+ * adjust the SDMMC controller delay between the clock and data to
+ * compenstate  for delays on the PCB. */
+void tegra_sdmmc_tap_delay(struct clk *c, int delay) {
 	unsigned long flags;
 
-	clk_lock_save(c, &flags);
-	/* !!FIXME!! add t30 support */
-#ifdef CONFIG_ARCH_TEGRA_2x_SOC
+	clk_lock_save(c, flags);
 	tegra2_sdmmc_tap_delay(c, delay);
-#endif
-	clk_unlock_restore(c, &flags);
+
+	clk_unlock_restore(c, flags);
 }
+#endif
 
 static bool tegra_keep_boot_clocks = false;
 static int __init tegra_keep_boot_clocks_setup(char *__unused)
@@ -567,7 +564,10 @@ static int __init tegra_init_disable_boot_clocks(void)
 }
 late_initcall(tegra_init_disable_boot_clocks);
 
-int tegra_periph_clk_cfg_ex(struct clk *c, u32 setting)
+/* Several extended clock configuration bits (e.g., clock routing, clock
+ * phase control) are included in PLL and peripheral clock source
+ * registers. */
+int tegra_clk_cfg_ex(struct clk *c, enum tegra_clk_ex_param p, u32 setting)
 {
 	int ret = 0;
 	unsigned long flags;
@@ -578,7 +578,7 @@ int tegra_periph_clk_cfg_ex(struct clk *c, u32 setting)
 		ret = -ENOSYS;
 		goto out;
 	}
-	c->ops->clk_cfg_ex(c, setting);
+	ret = c->ops->clk_cfg_ex(c, p, setting);
 
 out:
 	clk_unlock_restore(c, flags);