diff options
| author | Varun Wadekar <vwadekar@nvidia.com> | 2012-04-07 01:52:57 +0530 |
|---|---|---|
| committer | Varun Wadekar <vwadekar@nvidia.com> | 2012-04-07 01:52:57 +0530 |
| commit | 97caf63d0c837f9b5c9f6f469979e68c0378e83f (patch) | |
| tree | c6fc834bcfb66268f474324eca619db419010532 /arch/arm/mach-tegra/clock.h | |
| parent | 6a1a6f4f69adf0febfd923795b45edeff63e75ed (diff) | |
Merge branch '3.4-rc1' into android-tegra-nv-3.3-rebased
Change-Id: Ib3b69ffc5ac3e07c9cc44cc49e9142088eec477e
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Diffstat (limited to 'arch/arm/mach-tegra/clock.h')
| -rw-r--r-- | arch/arm/mach-tegra/clock.h | 8 |
1 files changed, 6 insertions, 2 deletions
diff --git a/arch/arm/mach-tegra/clock.h b/arch/arm/mach-tegra/clock.h index 376999ab9511..0cf3d20f33c3 100644 --- a/arch/arm/mach-tegra/clock.h +++ b/arch/arm/mach-tegra/clock.h @@ -30,6 +30,8 @@ #define PLL_POST_LOCK_DELAY 50 /* Safety delay after lock is detected */ #endif +#include <mach/clk.h> + #define DIV_BUS (1 << 0) #define DIV_U71 (1 << 1) #define DIV_U71_FIXED (1 << 2) @@ -48,7 +50,7 @@ #define PLLX (1 << 15) #define MUX_PWM (1 << 16) #define MUX8 (1 << 17) -#define DIV_U151_UART (1 << 18) +#define DIV_U71_UART (1 << 18) #define MUX_CLK_OUT (1 << 19) #define PLLM (1 << 20) #define DIV_U71_INT (1 << 21) @@ -95,6 +97,8 @@ struct clk_ops { int (*clk_cfg_ex)(struct clk *, enum tegra_clk_ex_param, u32); void (*reset)(struct clk *, bool); int (*shared_bus_update)(struct clk *); + int (*clk_cfg_ex)(struct clk *, + enum tegra_clk_ex_param, u32); }; struct clk_stats { @@ -228,7 +232,7 @@ struct tegra_sku_rate_limit { }; void tegra2_init_clocks(void); -void tegra3_init_clocks(void); +void tegra30_init_clocks(void); void tegra_common_init_clock(void); void tegra_init_max_rate(struct clk *c, unsigned long max_rate); void clk_init(struct clk *clk); |