ARM: tegra: clock: Dynamically re-lock memory pll

So far Tegra3 EMC DFS allowed only scaling rates that can be divided
down from two fixed rate plls: memory PLLM, and peripheral PLLP. PLLM
is always running at maximum SDRAM rate set at boot time, while PLLP
rate 408MHz is fixed across all Tegra3 platforms.

This commit implements dynamic re-locking of PLLM at run time. Now
memory pll can lock either at boot rate or additional auxiliary rate
that is selected as follows: auxiliary PLLM rate must be present in
EMC DFS table, it must exactly match one of the rate steps for Tegra3
graphics bus with PLLC clock source (cbus), and must not be a proper
factor of boot PLLM rate or PLLP fixed rate.

When switching PLLM between boot and auxiliary rate, PLLC is used as
backup memory pll, and during this time cbus is locked at auxiliary
rate. In addition system bus is forced to temporarily use PLLP as
a clock source (this is necessary as sbus main clock source is PLLM
secondary divider PLLM_OUT1).

Limitations:
- only one auxiliary rate is supported, and it should be below PLLM
boot rate, but above half of boot rate
- dynamic re-lock is allowed only on LPDDR2 platforms
- no clock other than EMC and system bus could use PLLM as a source;
so for dynamic re-lock to work CONFIG_TEGRA_PLLM_RESTRICTED must be
selected, and VI clock (not covered by PLLM restricted configuration)
must be moved to PLLP.

Bug 1005576

Change-Id: I6177107c89c3cbe975a1d940927efa1ed0ea61ec
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/111438
Reviewed-by: Rohan Somvanshi <rsomvanshi@nvidia.com>
Tested-by: Rohan Somvanshi <rsomvanshi@nvidia.com>
(cherry picked from commit dc4d468a6acabfb268e7a7f44b45bb7354e9a99a)
Reviewed-on: http://git-master/r/114760
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Jihoon Bang <jbang@nvidia.com>
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>

1 files changed, 3 insertions, 0 deletions

diff --git a/arch/arm/mach-tegra/clock.h b/arch/arm/mach-tegra/clock.h
index 8af1e1b21787..c27176b1cc0d 100644
--- a/arch/arm/mach-tegra/clock.h
+++ b/arch/arm/mach-tegra/clock.h
@@ -255,9 +255,12 @@ long tegra_emc_round_rate(unsigned long rate);
 struct clk *tegra_emc_predict_parent(unsigned long rate, u32 *div_value);
 void tegra_emc_timing_invalidate(void);
 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
+static inline int tegra_emc_backup(unsigned long rate)
+{ return 0; }
 static inline bool tegra_clk_is_parent_allowed(struct clk *c, struct clk *p)
 { return true; }
 #else
+int tegra_emc_backup(unsigned long rate);
 bool tegra_clk_is_parent_allowed(struct clk *c, struct clk *p);
 #endif