diff options
| author | Scott Williams <scwilliams@nvidia.com> | 2010-12-07 11:19:20 -0800 |
|---|---|---|
| committer | Dan Willemsen <dwillemsen@nvidia.com> | 2011-11-30 21:42:02 -0800 |
| commit | 816ab05de4f2171e20171db01fa916634ed7bee6 (patch) | |
| tree | 963ce2c1724c63598deb279d9f6ed54cfc93d1e3 /arch/arm/mach-tegra/clock.h | |
| parent | 7d8324d8f3dfc27407d7514fcbd605649c9bd210 (diff) | |
[ARM/tegra] Add Tegra3 support
Bug 764354
Original-Change-Id: I8a390eb4dae87dceacb97461f23d13554868b046
Reviewed-on: http://git-master/r/12228
Reviewed-by: Scott Williams <scwilliams@nvidia.com>
Tested-by: Scott Williams <scwilliams@nvidia.com>
Original-Change-Id: I8e6b8303898796419fb5a759cd16edff9aeac081
Rebase-Id: R2866240384c6c24f46bd7ef54bc3dc9140d9e96b
Diffstat (limited to 'arch/arm/mach-tegra/clock.h')
| -rw-r--r-- | arch/arm/mach-tegra/clock.h | 26 |
1 files changed, 22 insertions, 4 deletions
diff --git a/arch/arm/mach-tegra/clock.h b/arch/arm/mach-tegra/clock.h index fed02b294ae0..4f32594286ef 100644 --- a/arch/arm/mach-tegra/clock.h +++ b/arch/arm/mach-tegra/clock.h @@ -20,10 +20,12 @@ #ifndef __MACH_TEGRA_CLOCK_H #define __MACH_TEGRA_CLOCK_H -#include <linux/clkdev.h> -#include <linux/list.h> -#include <linux/mutex.h> -#include <linux/spinlock.h> +#ifdef CONFIG_ARCH_TEGRA_2x_SOC +#define USE_PLL_LOCK_BITS 0 /* Never use lock bits on Tegra2 */ +#else +/* !!!FIXME!!! PLL lock bits should work on Tegra3 */ +#define USE_PLL_LOCK_BITS 0 /* Use lock bits for PLL stabiliation */ +#endif #define DIV_BUS (1 << 0) #define DIV_U71 (1 << 1) @@ -40,8 +42,18 @@ #define PERIPH_MANUAL_RESET (1 << 12) #define PLL_ALT_MISC_REG (1 << 13) #define PLLU (1 << 14) +#define PLLX (1 << 15) +#define MUX_PWM (1 << 16) +#define MUX8 (1 << 17) #define ENABLE_ON_INIT (1 << 28) +#ifndef __ASSEMBLY__ + +#include <linux/clkdev.h> +#include <linux/list.h> +#include <linux/mutex.h> +#include <linux/spinlock.h> + #define MAX_SAME_LIMIT_SKU_IDS 16 struct clk; @@ -67,6 +79,8 @@ struct clk_ops { int (*set_parent)(struct clk *, struct clk *); int (*set_rate)(struct clk *, unsigned long); long (*round_rate)(struct clk *, unsigned long); + unsigned long (*get_max_rate)(struct clk *); + void (*recalculate_rate)(struct clk *); void (*reset)(struct clk *, bool); }; @@ -121,6 +135,7 @@ struct clk { unsigned long vco_max; const struct clk_pll_freq_table *freq_table; int lock_delay; + unsigned long fixed_rate; } pll; struct { u32 sel; @@ -129,6 +144,7 @@ struct clk { struct { struct clk *main; struct clk *backup; + unsigned long lp_max_rate; } cpu; struct { struct list_head node; @@ -159,6 +175,7 @@ struct tegra_sku_rate_limit { int sku_ids[MAX_SAME_LIMIT_SKU_IDS]; }; +void tegra_soc_init_clocks(void); void tegra2_init_clocks(void); void tegra2_periph_reset_deassert(struct clk *c); void tegra2_periph_reset_assert(struct clk *c); @@ -223,3 +240,4 @@ struct tegra_cpufreq_table_data *tegra_cpufreq_table_get(void); #endif #endif +#endif |