diff options
| author | Scott Williams <scwilliams@nvidia.com> | 2011-05-23 22:08:42 -0700 |
|---|---|---|
| committer | Dan Willemsen <dwillemsen@nvidia.com> | 2011-11-30 21:42:43 -0800 |
| commit | 07fc331f7ca9eb8b6c4958cafb302b0e9def78bd (patch) | |
| tree | 19c95e9b0bd000a69b737068afc372116d79faf3 /arch/arm/mach-tegra/common.c | |
| parent | d3b4e36da94f5fe2d69beab2e3f9ade8b5ab68bb (diff) | |
arm: tegra: Clean up SOC conditionals
Change SOC conditionals to make them more forward-looking.
Original-Change-Id: Ib60db4e690c2f396afdec962616d735548b5a8a9
Reviewed-on: http://git-master/r/32706
Reviewed-by: Niket Sirsi <nsirsi@nvidia.com>
Tested-by: Niket Sirsi <nsirsi@nvidia.com>
Rebase-Id: R77c675a1995116098b58f1f775bc7c3cc8722998
Diffstat (limited to 'arch/arm/mach-tegra/common.c')
| -rw-r--r-- | arch/arm/mach-tegra/common.c | 19 |
1 files changed, 9 insertions, 10 deletions
diff --git a/arch/arm/mach-tegra/common.c b/arch/arm/mach-tegra/common.c index a5d7eb4af7a1..091cc0600667 100644 --- a/arch/arm/mach-tegra/common.c +++ b/arch/arm/mach-tegra/common.c @@ -86,7 +86,13 @@ static __initdata struct tegra_clk_init_table common_clk_init_table[] = { { "pll_p_out2", "pll_p", 48000000, true }, { "pll_p_out3", "pll_p", 72000000, true }, { "pll_p_out4", "pll_p", 108000000, true }, -#ifdef CONFIG_ARCH_TEGRA_3x_SOC +#ifdef CONFIG_ARCH_TEGRA_2x_SOC + { "pll_m", "clk_m", 600000000, true }, + { "pll_m_out1", "pll_m", 120000000, true }, + { "sclk", "pll_m_out1", 40000000, true }, + { "hclk", "sclk", 40000000, true }, + { "pclk", "hclk", 40000000, true }, +#else { "pll_m_out1", "pll_m", 275000000, true }, { "pll_c", NULL, ULONG_MAX, false }, { "pll_c_out1", "pll_c", 208000000, false }, @@ -94,12 +100,6 @@ static __initdata struct tegra_clk_init_table common_clk_init_table[] = { { "sclk", "pll_p_out4", 108000000, true }, { "hclk", "sclk", 108000000, true }, { "pclk", "hclk", 54000000, true }, -#else - { "pll_m", "clk_m", 600000000, true }, - { "pll_m_out1", "pll_m", 120000000, true }, - { "sclk", "pll_m_out1", 40000000, true }, - { "hclk", "sclk", 40000000, true }, - { "pclk", "hclk", 40000000, true }, #endif { "csite", NULL, 0, true }, { "emc", NULL, 0, true }, @@ -109,7 +109,7 @@ static __initdata struct tegra_clk_init_table common_clk_init_table[] = { { "sdmmc1", "pll_c", 48000000, false}, { "sdmmc3", "pll_p", 48000000, false}, { "sdmmc4", "pll_p", 48000000, false}, -#ifdef CONFIG_ARCH_TEGRA_3x_SOC +#ifndef CONFIG_ARCH_TEGRA_2x_SOC { "vde", "pll_c", ULONG_MAX, false }, { "host1x", "pll_c", 0, false }, { "mpe", "pll_c", 0, false }, @@ -163,8 +163,7 @@ static void __init tegra_init_power(void) { tegra_powergate_power_off(TEGRA_POWERGATE_MPE); tegra_powergate_power_off(TEGRA_POWERGATE_3D); -#ifndef CONFIG_ARCH_TEGRA_3x_SOC - /* for TEGRA_3x_SOC it will be handled seperately */ +#ifdef CONFIG_ARCH_TEGRA_2x_SOC tegra_powergate_power_off(TEGRA_POWERGATE_PCIE); #endif } |