summaryrefslogtreecommitdiff
path: root/arch/arm/mach-tegra/common.c
diff options
context:
space:
mode:
authorAlex Frid <afrid@nvidia.com>2011-05-17 18:14:36 -0700
committerDan Willemsen <dwillemsen@nvidia.com>2011-11-30 21:42:41 -0800
commit623a893e686ad43ad1c4efb2621034861d279967 (patch)
treea2f5ab3e26ef7b3a1e065ab781d90fbe6fa8a832 /arch/arm/mach-tegra/common.c
parentbbd494faa3f6efd86dcc015bec54d1ae07a464f2 (diff)
ARM: tegra: power: Update Tegra3 core dvfs tables
Updated Tegra3 core dvfs tables with new characterization data. Respectively raised maximum frequency limits for CPU in LP mode, VDE/MPE/3D/2d/Epp and system bus clocks. Original-Change-Id: I79b58e482005896d55219e4fb9b9421f37dd46a1 Reviewed-on: http://git-master/r/32066 Reviewed-by: Niket Sirsi <nsirsi@nvidia.com> Tested-by: Niket Sirsi <nsirsi@nvidia.com> Rebase-Id: R5e1c897eb4b1b8f3471fe7bd350ec5a8f378cb5d
Diffstat (limited to 'arch/arm/mach-tegra/common.c')
-rw-r--r--arch/arm/mach-tegra/common.c6
1 files changed, 3 insertions, 3 deletions
diff --git a/arch/arm/mach-tegra/common.c b/arch/arm/mach-tegra/common.c
index 04caa123bbd8..a5d7eb4af7a1 100644
--- a/arch/arm/mach-tegra/common.c
+++ b/arch/arm/mach-tegra/common.c
@@ -88,7 +88,7 @@ static __initdata struct tegra_clk_init_table common_clk_init_table[] = {
{ "pll_p_out4", "pll_p", 108000000, true },
#ifdef CONFIG_ARCH_TEGRA_3x_SOC
{ "pll_m_out1", "pll_m", 275000000, true },
- { "pll_c", NULL, 832000000, false },
+ { "pll_c", NULL, ULONG_MAX, false },
{ "pll_c_out1", "pll_c", 208000000, false },
{ "pll_p_out4", "pll_p", 108000000, true },
{ "sclk", "pll_p_out4", 108000000, true },
@@ -110,8 +110,8 @@ static __initdata struct tegra_clk_init_table common_clk_init_table[] = {
{ "sdmmc3", "pll_p", 48000000, false},
{ "sdmmc4", "pll_p", 48000000, false},
#ifdef CONFIG_ARCH_TEGRA_3x_SOC
- { "vde", "pll_c", 416000000, false },
- { "host1x", "pll_c", 208000000, false },
+ { "vde", "pll_c", ULONG_MAX, false },
+ { "host1x", "pll_c", 0, false },
{ "mpe", "pll_c", 0, false },
{ "3d", "pll_c", 0, false },
{ "3d2", "pll_c", 0, false },