diff options
| author | Alex Frid <afrid@nvidia.com> | 2011-05-28 00:21:30 -0700 |
|---|---|---|
| committer | Dan Willemsen <dwillemsen@nvidia.com> | 2011-11-30 21:42:46 -0800 |
| commit | c86c2259fec1d947f16ca3a65085d481f320c4bb (patch) | |
| tree | f15315b66fad5b891d0a4549581464818d707450 /arch/arm/mach-tegra/common.c | |
| parent | 3ea1f8b4b62acb995114da701ef2ebf420d02cd2 (diff) | |
ARM: tegra: clock: Change Tegra3 PLLP output frequency
On Tegra3 fixed PLLP output frequency has been set to 408MHz
(instead of 216MHz). Respectively changed:
- Tegra3 broads setting for UART, and audio clocks
- Tegra3 common clock setting for PLLP output dividers, SDMMC,
and system buses
- Tegra3 CPU backup configuration to guarantee safe backup at
any voltage
Bug 829081
Original-Change-Id: Ied0c75204ccb2e4a428f0b8a124f0f3e053aa386
Reviewed-on: http://git-master/r/34813
Reviewed-by: Aleksandr Frid <afrid@nvidia.com>
Tested-by: Aleksandr Frid <afrid@nvidia.com>
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
Reviewed-by: Scott Williams <scwilliams@nvidia.com>
Rebase-Id: Rb9a445970ed83922394a24a732372c5541d8ef47
Diffstat (limited to 'arch/arm/mach-tegra/common.c')
| -rw-r--r-- | arch/arm/mach-tegra/common.c | 16 |
1 files changed, 10 insertions, 6 deletions
diff --git a/arch/arm/mach-tegra/common.c b/arch/arm/mach-tegra/common.c index 951a4cc3a061..fbbdb7ccd960 100644 --- a/arch/arm/mach-tegra/common.c +++ b/arch/arm/mach-tegra/common.c @@ -109,32 +109,36 @@ void tegra_assert_system_reset(char mode, const char *cmd) static __initdata struct tegra_clk_init_table common_clk_init_table[] = { /* name parent rate enabled */ { "clk_m", NULL, 0, true }, +#ifdef CONFIG_ARCH_TEGRA_2x_SOC { "pll_p", NULL, 216000000, true }, { "pll_p_out1", "pll_p", 28800000, true }, { "pll_p_out2", "pll_p", 48000000, true }, { "pll_p_out3", "pll_p", 72000000, true }, { "pll_p_out4", "pll_p", 108000000, true }, -#ifdef CONFIG_ARCH_TEGRA_2x_SOC { "pll_m", "clk_m", 600000000, true }, { "pll_m_out1", "pll_m", 120000000, true }, { "sclk", "pll_m_out1", 40000000, true }, { "hclk", "sclk", 40000000, true }, { "pclk", "hclk", 40000000, true }, #else + { "pll_p", NULL, 408000000, true }, + { "pll_p_out1", "pll_p", 9600000, true }, + { "pll_p_out2", "pll_p", 48000000, true }, + { "pll_p_out3", "pll_p", 102000000, true }, { "pll_m_out1", "pll_m", 275000000, true }, { "pll_c", NULL, ULONG_MAX, false }, { "pll_c_out1", "pll_c", 208000000, false }, - { "pll_p_out4", "pll_p", 108000000, true }, - { "sclk", "pll_p_out4", 108000000, true }, - { "hclk", "sclk", 108000000, true }, - { "pclk", "hclk", 54000000, true }, + { "pll_p_out4", "pll_p", 102000000, true }, + { "sclk", "pll_p_out4", 102000000, true }, + { "hclk", "sclk", 102000000, true }, + { "pclk", "hclk", 51000000, true }, #endif { "csite", NULL, 0, true }, { "emc", NULL, 0, true }, { "cpu", NULL, 0, true }, { "kfuse", NULL, 0, true }, { "pll_u", NULL, 480000000, false }, - { "sdmmc1", "pll_c", 48000000, false}, + { "sdmmc1", "pll_p", 48000000, false}, { "sdmmc3", "pll_p", 48000000, false}, { "sdmmc4", "pll_p", 48000000, false}, #ifndef CONFIG_ARCH_TEGRA_2x_SOC |