diff options
| author | Yudong Tan <ytan@nvidia.com> | 2011-07-01 11:26:17 -0700 |
|---|---|---|
| committer | Dan Willemsen <dwillemsen@nvidia.com> | 2011-11-30 21:47:19 -0800 |
| commit | f8cd6295ec46744ca93a76cc430faacbaac664a4 (patch) | |
| tree | 2913d021afa34b271b3fd1f0fa778de23e309f13 /arch/arm/mach-tegra/common.c | |
| parent | 607cfa68323723eb2566f7259c6de9fe94703292 (diff) | |
arm: tegra: Use new platform types
This change is needed to support three different platforms, silicon,
fpga and simulation.
Change-Id: I407853e1d86accbe3686deb4f34571fe6b10bcce
Reviewed-on: http://git-master/r/36351
Reviewed-by: Varun Colbert <vcolbert@nvidia.com>
Tested-by: Varun Colbert <vcolbert@nvidia.com>
Rebase-Id: Rc4b424f1a55ffb71245f3a8330559258124e2a19
Diffstat (limited to 'arch/arm/mach-tegra/common.c')
| -rw-r--r-- | arch/arm/mach-tegra/common.c | 10 |
1 files changed, 5 insertions, 5 deletions
diff --git a/arch/arm/mach-tegra/common.c b/arch/arm/mach-tegra/common.c index 6d62efd1dd49..3513b6912131 100644 --- a/arch/arm/mach-tegra/common.c +++ b/arch/arm/mach-tegra/common.c @@ -118,7 +118,7 @@ void tegra_assert_system_reset(char mode, const char *cmd) static __initdata struct tegra_clk_init_table common_clk_init_table[] = { /* name parent rate enabled */ { "clk_m", NULL, 0, true }, -#ifndef CONFIG_TEGRA_FPGA_PLATFORM +#ifdef CONFIG_TEGRA_SILICON_PLATFORM #ifdef CONFIG_ARCH_TEGRA_2x_SOC { "pll_p", NULL, 216000000, true }, { "pll_p_out1", "pll_p", 28800000, true }, @@ -180,10 +180,7 @@ void tegra_init_cache(void) writel_relaxed(0x441, p + L2X0_DATA_LATENCY_CTRL); #elif defined(CONFIG_ARCH_TEGRA_3x_SOC) -#ifdef CONFIG_TEGRA_FPGA_PLATFORM - writel(0x770, p + L2X0_TAG_LATENCY_CTRL); - writel(0x770, p + L2X0_DATA_LATENCY_CTRL); -#else +#ifdef CONFIG_TEGRA_SILICON_PLATFORM /* PL310 RAM latency is CPU dependent. NOTE: Changes here must also be reflected in __cortex_a9_l2x0_restart */ @@ -194,6 +191,9 @@ void tegra_init_cache(void) writel(0x331, p + L2X0_TAG_LATENCY_CTRL); writel(0x441, p + L2X0_DATA_LATENCY_CTRL); } +#else + writel(0x770, p + L2X0_TAG_LATENCY_CTRL); + writel(0x770, p + L2X0_DATA_LATENCY_CTRL); #endif /* Enable PL310 double line fill feature. */ |