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| author | Marcel Ziswiler <marcel.ziswiler@toradex.com> | 2012-06-08 20:36:31 +0200 |
|---|---|---|
| committer | Marcel Ziswiler <marcel.ziswiler@toradex.com> | 2012-06-08 20:36:31 +0200 |
| commit | 37440f3ed07a6f588b05b8f98d0b3025c1949371 (patch) | |
| tree | 4908a32c084044a3725e6c3f4001cc1242c17904 /arch/arm/mach-tegra/common.c | |
| parent | e6d7d2f5e4028455655cbd7c35f086f71a4aba02 (diff) | |
Initial Toradex Colibri T20 L4T R15 support.
Diffstat (limited to 'arch/arm/mach-tegra/common.c')
| -rw-r--r-- | arch/arm/mach-tegra/common.c | 4 |
1 files changed, 3 insertions, 1 deletions
diff --git a/arch/arm/mach-tegra/common.c b/arch/arm/mach-tegra/common.c index f0c0cb69896f..200604694508 100644 --- a/arch/arm/mach-tegra/common.c +++ b/arch/arm/mach-tegra/common.c @@ -168,7 +168,9 @@ static __initdata struct tegra_clk_init_table common_clk_init_table[] = { { "pll_p_out4", "pll_p", 108000000, false }, { "pll_m", "clk_m", 0, true }, { "pll_m_out1", "pll_m", 120000000, true }, - { "sclk", "pll_c_out1", 40000000, true }, +//[ 0.000000] Failed to set parent pll_c_out1 for sclk (violates clock limit 240000000) +//[ 0.000000] Unable to set parent pll_c_out1 of clock sclk: -22 + { "sclk", "pll_p_out3", 72000000, true }, { "hclk", "sclk", 40000000, true }, { "pclk", "hclk", 40000000, true }, { "mpe", "pll_c", 0, false }, |