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authorScottPeterson <speterson@nvidia.com>2011-08-02 13:47:42 -0700
committerVarun Colbert <vcolbert@nvidia.com>2011-08-03 15:03:25 -0700
commit7ead8fdb4882176414a87299e037968bc7de7ace (patch)
treee375d9ff10e4d799ed2d914b9e946df55aaf0dc1 /arch/arm/mach-tegra/dam.c
parent18df471d781c479ea6094436e9c76e665b2f436f (diff)
arm:tegra: Fix error in DAM functions
Fixed error in dam_chX_set_gain function which was ORring the value without a mask when setting the DAM gain register. Change-Id: I6c8cb51daf0f23602863d14525432ddd94ee0ba7 Reviewed-on: http://git-master/r/44611 Reviewed-by: Songhee Baek <sbaek@nvidia.com> Tested-by: Songhee Baek <sbaek@nvidia.com> Reviewed-by: Scott Peterson <speterson@nvidia.com> Tested-by: Scott Peterson <speterson@nvidia.com>
Diffstat (limited to 'arch/arm/mach-tegra/dam.c')
-rw-r--r--arch/arm/mach-tegra/dam.c18
1 files changed, 2 insertions, 16 deletions
diff --git a/arch/arm/mach-tegra/dam.c b/arch/arm/mach-tegra/dam.c
index 47510409fd8c..0940fd117f7f 100644
--- a/arch/arm/mach-tegra/dam.c
+++ b/arch/arm/mach-tegra/dam.c
@@ -410,15 +410,8 @@ void dam_ch0_set_datasync(int ifc,int datasync)
void dam_ch0_set_gain(int ifc, int gain)
{
- u32 val;
-
check_dam_ifc(ifc);
-
- val = dam_readl(ifc, DAM_CH0_CONV_0);
-
- val |= gain << DAM_GAIN_SHIFT;
-
- dam_writel(ifc, val, DAM_CH0_CONV_0);
+ dam_writel(ifc, gain, DAM_CH0_CONV_0);
}
void dam_ch1_enable(int ifc,int on)
@@ -449,15 +442,8 @@ void dam_ch1_set_datasync(int ifc,int datasync)
void dam_ch1_set_gain(int ifc,int gain)
{
- u32 val;
-
check_dam_ifc(ifc);
-
- val = dam_readl(ifc, DAM_CH1_CONV_0);
-
- val |= gain << DAM_GAIN_SHIFT;
-
- dam_writel(ifc, val, DAM_CH1_CONV_0);
+ dam_writel(ifc, gain, DAM_CH1_CONV_0);
}
void dam_save_ctrl_registers(int ifc)