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authorAnshul Jain <anshulj@nvidia.com>2012-07-23 14:59:32 -0700
committerSimone Willett <swillett@nvidia.com>2012-07-30 20:46:28 -0700
commit4582bcef392ae029336673f5685a18fc67ac041a (patch)
tree3f0da45b86faadf3f3f2efde51871ed5b0efd235 /arch/arm/mach-tegra/dvfs.h
parent4012b752d64fd88efc3797e42ad8fedb29045e06 (diff)
ARM: tegra: dvfs: Adjust VDD_CPU to offset aging
Add silicon aging for VDD_CPU, this recovers some of millivolts based on the age of the chip. BUG 1006420 Change-Id: Idddb5861ab039e7ece262dec3697a69c3534ccf2 Signed-off-by: Anshul Jain <anshulj@nvidia.com> Reviewed-on: http://git-master/r/116911 Reviewed-by: Aleksandr Frid <afrid@nvidia.com> Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Diwakar Tundlam <dtundlam@nvidia.com> GVS: Gerrit_Virtual_Submit
Diffstat (limited to 'arch/arm/mach-tegra/dvfs.h')
-rw-r--r--arch/arm/mach-tegra/dvfs.h5
1 files changed, 4 insertions, 1 deletions
diff --git a/arch/arm/mach-tegra/dvfs.h b/arch/arm/mach-tegra/dvfs.h
index 91901b361724..7cacd954b914 100644
--- a/arch/arm/mach-tegra/dvfs.h
+++ b/arch/arm/mach-tegra/dvfs.h
@@ -22,7 +22,7 @@
#define _TEGRA_DVFS_H_
#define MAX_DVFS_FREQS 40
-#define DVFS_RAIL_STATS_TOP_BIN 40
+#define DVFS_RAIL_STATS_TOP_BIN 42
struct clk;
struct dvfs_rail;
@@ -165,11 +165,14 @@ static inline int tegra_cpu_dvfs_alter(int edp_thermal_index,
#ifndef CONFIG_ARCH_TEGRA_2x_SOC
int tegra_dvfs_rail_disable_prepare(struct dvfs_rail *rail);
int tegra_dvfs_rail_post_enable(struct dvfs_rail *rail);
+void tegra_dvfs_age_cpu(int cur_linear_age);
#else
static inline int tegra_dvfs_rail_disable_prepare(struct dvfs_rail *rail)
{ return 0; }
static inline int tegra_dvfs_rail_post_enable(struct dvfs_rail *rail)
{ return 0; }
+static inline void tegra_dvfs_age_cpu(int cur_linear_age)
+{ return; }
#endif
#endif