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authorDiwakar Tundlam <dtundlam@nvidia.com>2011-05-18 16:58:03 -0700
committerDan Willemsen <dwillemsen@nvidia.com>2011-11-30 21:42:41 -0800
commit7a3a6cecdf050e0d988b5ab8e32d94e8d4ea4bda (patch)
tree5bfd5aa5969b7dc192711e76591d6588e4f9b66d /arch/arm/mach-tegra/fuse.c
parent198ce6b3b5ce5e48667bfb624b966f1e3842aa4e (diff)
ARM: tegra: clock: Set speedo_id according to actual fused SKU
- Read SKU_INFO fuse to get A02 SKU info - Update CPU DVFS to use actual SKU info obtained - Enable main table for EDP capping and thermal throttling Original-Change-Id: I7ff3b06476998d77cc3f7a4fc03fb72e26b570db Reviewed-on: http://git-master/r/32084 Reviewed-by: Niket Sirsi <nsirsi@nvidia.com> Tested-by: Niket Sirsi <nsirsi@nvidia.com> Rebase-Id: Re91f616032d8045ea2c28822e40f815f3e449931
Diffstat (limited to 'arch/arm/mach-tegra/fuse.c')
-rw-r--r--arch/arm/mach-tegra/fuse.c5
1 files changed, 3 insertions, 2 deletions
diff --git a/arch/arm/mach-tegra/fuse.c b/arch/arm/mach-tegra/fuse.c
index 9a98f2e96929..61bbac3271ee 100644
--- a/arch/arm/mach-tegra/fuse.c
+++ b/arch/arm/mach-tegra/fuse.c
@@ -87,10 +87,11 @@ void tegra_init_fuse(void)
writel(reg, IO_TO_VIRT(TEGRA_CLK_RESET_BASE + 0x48));
tegra_init_speedo_data();
- pr_info("Tegra Revision: %s SKU: %d CPU Process: %d Core Process: %d\n",
+ pr_info("Tegra Revision: %s SKU: %d CPU Process: %d Core Process: %d "
+ "Speedo ID: %d\n",
tegra_get_revision_name(),
tegra_sku_id(), tegra_cpu_process_id(),
- tegra_core_process_id());
+ tegra_core_process_id(), tegra_soc_speedo_id());
}
unsigned long long tegra_chip_uid(void)