diff options
| author | Scott Williams <scwilliams@nvidia.com> | 2012-02-03 11:00:50 -0800 |
|---|---|---|
| committer | Dan Willemsen <dwillemsen@nvidia.com> | 2013-09-14 12:09:52 -0700 |
| commit | 5d41256260ae2fdfbebbcabb906246bc23e899bd (patch) | |
| tree | 3a2223edf510134ab4b775a18193e77856529209 /arch/arm/mach-tegra/headsmp.S | |
| parent | bc5f001c39280e26da7984f084f5546b531f25e0 (diff) | |
ARM: tegra: smp: Add support for Cortex-A15 boot_secondary
Cortex-A15 does not have a memory-mapped SCU in the PERIPHBASE
aperture. Instead, the number of CPUs present is obtained from
the architectural L2 Cache Control (L2CTLR) register.
Enable HAVE_ARM_SCU only on platforms that have a memory-mapped
SCU and add the necessary conditionals to prevent access to the
memory-mapped SCU address range on platforms that don't.
Change-Id: I4027d034fe79339fab0030a44780240785206cba
Signed-off-by: Scott Williams <scwilliams@nvidia.com>
Reviewed-on: http://git-master/r/79341
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Mark Stadler <mastadler@nvidia.com>
Reviewed-by: Jeff Smith <jsmith@nvidia.com>
Reviewed-by: Bo Yan <byan@nvidia.com>
Reviewed-by: Aleksandr Frid <afrid@nvidia.com>
Rebase-Id: R62dcd56e7abed8ef5cef60325c6ca52fbfb43b22
Diffstat (limited to 'arch/arm/mach-tegra/headsmp.S')
| -rw-r--r-- | arch/arm/mach-tegra/headsmp.S | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/arch/arm/mach-tegra/headsmp.S b/arch/arm/mach-tegra/headsmp.S index ad82faa9e59c..f93d30a6949f 100644 --- a/arch/arm/mach-tegra/headsmp.S +++ b/arch/arm/mach-tegra/headsmp.S @@ -81,6 +81,7 @@ ENTRY(tegra_resume) str r1, [r2] #endif +#ifdef CONFIG_HAVE_ARM_SCU /* enable SCU */ mov32 r0, TEGRA_ARM_PERIF_BASE ldr r1, [r0] @@ -91,6 +92,7 @@ ENTRY(tegra_resume) orr r1, r1, #(1 << 6) @ Enable SCU standby. #endif str r1, [r0] +#endif #ifdef CONFIG_TRUSTED_FOUNDATIONS /* wake up (should have specified args?) */ |