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authorvdumpa <vdumpa@nvidia.com>2011-05-04 11:48:38 -0700
committerDan Willemsen <dwillemsen@nvidia.com>2013-09-14 00:57:32 -0700
commitcccc00d79f7f5cdf881af4064566dc5f041e7e08 (patch)
treeedab6e012ab0d320795535d89098cf54ffb3c567 /arch/arm/mach-tegra/headsmp.S
parent76fe1117afa913987fd53cf1acbbc687e76ed1b3 (diff)
ARM: tegra: power: restore ARM errata fixes after cpu power/rail gating.
Bug 804805 (cherry picked from commit 068e6789bd335640ad2b444fae1e74fd9ca974c5) Change-Id: If79b491133e6080b8b9c90c5adb0f59239ea275f Reviewed-on: http://git-master/r/54842 Reviewed-by: Scott Williams <scwilliams@nvidia.com> Reviewed-by: Krishna Reddy <vdumpa@nvidia.com> Tested-by: Krishna Reddy <vdumpa@nvidia.com> Rebase-Id: R16eabb01ed2c8197632d6063b5c9f35bed5714dd
Diffstat (limited to 'arch/arm/mach-tegra/headsmp.S')
-rw-r--r--arch/arm/mach-tegra/headsmp.S16
1 files changed, 16 insertions, 0 deletions
diff --git a/arch/arm/mach-tegra/headsmp.S b/arch/arm/mach-tegra/headsmp.S
index 07e04108bebf..b5957261dc1f 100644
--- a/arch/arm/mach-tegra/headsmp.S
+++ b/arch/arm/mach-tegra/headsmp.S
@@ -164,7 +164,23 @@ ENTRY(__tegra_cpu_reset_handler)
mcr p14, 0, r0, c7, c12, 6 @ Enable CoreSight access
b .
#endif
+#ifndef CONFIG_TRUSTED_FOUNDATIONS
cpsid aif, 0x13 @ SVC mode, interrupts disabled
+ mrc p15, 0, r0, c0, c0, 0 @ read main ID register
+ and r5, r0, #0x00f00000 @ variant
+ and r6, r0, #0x0000000f @ revision
+ orr r6, r6, r5, lsr #20-4 @ combine variant and revision
+#ifdef CONFIG_ARM_ERRATA_743622
+ teq r6, #0x20 @ present in r2p0
+ teqne r6, #0x21 @ present in r2p1
+ teqne r6, #0x22 @ present in r2p2
+ teqne r6, #0x27 @ present in r2p7
+ teqne r6, #0x29 @ present in r2p9
+ mrceq p15, 0, r10, c15, c0, 1 @ read diagnostic register
+ orreq r10, r10, #1 << 6 @ set bit #6
+ mcreq p15, 0, r10, c15, c0, 1 @ write diagnostic register
+#endif
+#endif
mrc p15, 0, r10, c0, c0, 5 @ MPIDR
and r10, r10, #0x3 @ R10 = CPU number
mov r11, #1