diff options
| author | Edgardo Handal <ehandal@nvidia.com> | 2013-05-29 15:05:00 -0500 |
|---|---|---|
| committer | Dan Willemsen <dwillemsen@nvidia.com> | 2013-09-14 13:27:37 -0700 |
| commit | 37e00c7a4c092b0f20d71cdf805de4ea7cdaacae (patch) | |
| tree | 8a7e85eccdf46040d01f3caa5333d8ed8d28347f /arch/arm/mach-tegra/headsmp.S | |
| parent | 802f6f8f1f9b9834ce9a7effa6f297f53281ea88 (diff) | |
ARM: Tegra: don't clobber SCTLR
Do read-modify-write on SCTLR when enabling caches and branch
prediction rather than just overwriting the register.
Bug 1292766
Change-Id: Ib76b3100ebb657250ce863e697f7b712d27638ea
Signed-off-by: Edgardo Handal <ehandal@nvidia.com>
Reviewed-on: http://git-master/r/233824
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Bo Yan <byan@nvidia.com>
Reviewed-by: Nitin Kumbhar <nkumbhar@nvidia.com>
Reviewed-by: Matthew Pedro <mapedro@nvidia.com>
Reviewed-by: Allen Martin <amartin@nvidia.com>
Diffstat (limited to 'arch/arm/mach-tegra/headsmp.S')
| -rw-r--r-- | arch/arm/mach-tegra/headsmp.S | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/arch/arm/mach-tegra/headsmp.S b/arch/arm/mach-tegra/headsmp.S index 473cc1f6fcc1..d41f6b83a8f1 100644 --- a/arch/arm/mach-tegra/headsmp.S +++ b/arch/arm/mach-tegra/headsmp.S @@ -264,7 +264,8 @@ __invalidate_cpu_state: orr r0, r0, #0x80 @ hazard detection timeout mcr p15, 0x1, r0, c15, c0, 0 __enable_i_cache_branch_pred: - mov r0, #0x1800 + mrc p15, 0, r0, c1, c0, 0 + orr r0, r0, #0x1800 mcr p15, 0, r0, c1, c0, 0 @ enable branch prediction, i-cache mov pc, lr /* no fall through, just return to the caller */ |