diff options
| author | Peter De Schrijver <pdeschrijver@nvidia.com> | 2012-02-10 01:47:50 +0200 |
|---|---|---|
| committer | Olof Johansson <olof@lixom.net> | 2012-02-26 14:44:46 -0800 |
| commit | 86e51a2ee471062184d2f74b46c45d344a2b9b38 (patch) | |
| tree | 515e410e2fa652b368e31f350c50b73d477d8521 /arch/arm/mach-tegra/headsmp.S | |
| parent | 65fe31da5cede3597938b0f3bba99f604369018d (diff) | |
ARM: tegra: support for secondary cores on Tegra30
Add support for bringing up secondary cores on Tegra30. On Tegra30 secondary
CPU cores are powergated, so we need to turn on the domains before we can bring
the CPU cores online. Bringing secondary cores online happens early during the
sytem boot, so we call powergating initialization from platform early_init
function.
Based on work by:
Scott Williams <scwilliams@nvidia.com>
Colin Cross <ccross@android.com>
Alex Frid <afrid@nvidia.com>
Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
Acked-by: Stephen Warren <swarren@nvidia.com>
Tested-by: Stephen Warren <swarren@nvidia.com>
Acked-by: Colin Cross <ccross@android.com>
Signed-off-by: Olof Johansson <olof@lixom.net>
Diffstat (limited to 'arch/arm/mach-tegra/headsmp.S')
| -rw-r--r-- | arch/arm/mach-tegra/headsmp.S | 32 |
1 files changed, 32 insertions, 0 deletions
diff --git a/arch/arm/mach-tegra/headsmp.S b/arch/arm/mach-tegra/headsmp.S index 37d6dd96d62f..fef9c2c51370 100644 --- a/arch/arm/mach-tegra/headsmp.S +++ b/arch/arm/mach-tegra/headsmp.S @@ -164,6 +164,38 @@ __die: str r1, [r7, #0x340] @ CLK_RST_CPU_CMPLX_SET #endif 1: +#ifdef CONFIG_ARCH_TEGRA_3x_SOC + mov32 r6, TEGRA_FLOW_CTRL_BASE + + cmp r10, #0 + moveq r1, #FLOW_CTRL_HALT_CPU0_EVENTS + moveq r2, #FLOW_CTRL_CPU0_CSR + movne r1, r10, lsl #3 + addne r2, r1, #(FLOW_CTRL_CPU1_CSR-8) + addne r1, r1, #(FLOW_CTRL_HALT_CPU1_EVENTS-8) + + /* Clear CPU "event" and "interrupt" flags and power gate + it when halting but not before it is in the "WFI" state. */ + ldr r0, [r6, +r2] + orr r0, r0, #FLOW_CTRL_CSR_INTR_FLAG | FLOW_CTRL_CSR_EVENT_FLAG + orr r0, r0, #FLOW_CTRL_CSR_ENABLE + str r0, [r6, +r2] + + /* Unconditionally halt this CPU */ + mov r0, #FLOW_CTRL_WAITEVENT + str r0, [r6, +r1] + ldr r0, [r6, +r1] @ memory barrier + + dsb + isb + wfi @ CPU should be power gated here + + /* If the CPU didn't power gate above just kill it's clock. */ + + mov r0, r11, lsl #8 + str r0, [r7, #348] @ CLK_CPU_CMPLX_SET +#endif + /* If the CPU still isn't dead, just spin here. */ b . ENDPROC(__tegra_cpu_reset_handler) |