summaryrefslogtreecommitdiff
path: root/arch/arm/mach-tegra/hotplug.c
diff options
context:
space:
mode:
authorScott Williams <scwilliams@nvidia.com>2012-02-02 15:20:15 -0800
committerDan Willemsen <dwillemsen@nvidia.com>2013-09-14 12:09:46 -0700
commitded7385bc677dfcc31c81747f7900f34eeba6c5f (patch)
tree57b44f399772194696c6ceaf7862ba391fa8a23b /arch/arm/mach-tegra/hotplug.c
parentcfb3a68ce42b6cf8c3c1ebaa1663c6fc3629ccff (diff)
ARM: tegra: Remove GIC bypass mode for hotplug
Every call to tegra_gic_pass_through_disable() is preceded by a call to tegra_gic_cpu_disable(). However, the call from hotplug shutdown is superfluous on Cortex-A9 and wrong on Cortex-A15. Consolidate the two disable functions into a single function taking a parameter that indicates whether to enable bypass mode: the call from the hotplug shutdown path does not enable bypass, the call from the CPU suspend path does. BUG 929216 Change-Id: I0b11dc89b27aeb42b3ddffb0cfe1a65eb7a50f93 Signed-off-by: Scott Williams <scwilliams@nvidia.com> Reviewed-on: http://git-master/r/79092 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Jin Qian <jqian@nvidia.com> Reviewed-by: Varun Wadekar <vwadekar@nvidia.com> Rebase-Id: Re1f145785b568cdd45bc5656e1d009298698b580
Diffstat (limited to 'arch/arm/mach-tegra/hotplug.c')
-rw-r--r--arch/arm/mach-tegra/hotplug.c8
1 files changed, 1 insertions, 7 deletions
diff --git a/arch/arm/mach-tegra/hotplug.c b/arch/arm/mach-tegra/hotplug.c
index 2d0f7bdc086b..f91c84c75c5c 100644
--- a/arch/arm/mach-tegra/hotplug.c
+++ b/arch/arm/mach-tegra/hotplug.c
@@ -43,13 +43,7 @@ void tegra_cpu_die(unsigned int cpu)
#ifndef CONFIG_ARCH_TEGRA_2x_SOC
/* Disable GIC CPU interface for this CPU. */
- tegra_gic_cpu_disable();
-
- /* Tegra3 enters LPx states via WFI - do not propagate legacy IRQs
- to CPU core to avoid fall through WFI; then GIC output will be
- enabled, however at this time - CPU is dying - no interrupt should
- have affinity to this CPU. */
- tegra_gic_pass_through_disable();
+ tegra_gic_cpu_disable(false);
#endif
/* Flush the L1 data cache. */