diff options
| author | Antti P Miettinen <amiettinen@nvidia.com> | 2012-09-19 14:44:59 +0300 |
|---|---|---|
| committer | Dan Willemsen <dwillemsen@nvidia.com> | 2013-09-14 12:34:53 -0700 |
| commit | ff364e62af398c217683d4cc96a0e8afc4d2bdc6 (patch) | |
| tree | 93729ebe147e9fbbbef5e2252e50e8b2a9d28268 /arch/arm/mach-tegra/hotplug.c | |
| parent | 0129942c52743759453354a1b7f463d7ffe92234 (diff) | |
ARM: Tegra: Move cache disable to flush function
During power gating we need to make sure that all state is
properly flushed to ungated part of the chip. To ensure
that data cache is completely cleaned after flush, the
cache needs to be disabled before flush. When data cache
is disabled we naturally cannot write to cacheable memory.
Therefore handle the disable inside the flush function.
Bug 1045096
Change-Id: I740ffdfd43c4b75bf58aaad4279092040a8c7405
Signed-off-by: Antti P Miettinen <amiettinen@nvidia.com>
Reviewed-on: http://git-master/r/133799
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>
Rebase-Id: R4496004d2a32b2dfda731c77502a9489c0eb6b08
Diffstat (limited to 'arch/arm/mach-tegra/hotplug.c')
| -rw-r--r-- | arch/arm/mach-tegra/hotplug.c | 16 |
1 files changed, 0 insertions, 16 deletions
diff --git a/arch/arm/mach-tegra/hotplug.c b/arch/arm/mach-tegra/hotplug.c index f14ea9ee786e..ba2166876a91 100644 --- a/arch/arm/mach-tegra/hotplug.c +++ b/arch/arm/mach-tegra/hotplug.c @@ -42,24 +42,8 @@ void tegra_cpu_die(unsigned int cpu) cpu = cpu_logical_map(cpu); #ifndef CONFIG_ARCH_TEGRA_2x_SOC -#ifdef CONFIG_ARCH_TEGRA_11x_SOC - unsigned int r = 0; -#endif - /* Disable GIC CPU interface for this CPU. */ tegra_gic_cpu_disable(false); - -#ifdef CONFIG_ARCH_TEGRA_11x_SOC - /* disable cache */ - asm volatile( - " mrc p15, 0, %0, c1, c0, 0\n" - " bic %0, %0, #0x4 \n" - " mcr p15, 0, %0, c1, c0, 0\n" - : "=r" (r) - : "r" (r) - : "cc" - ); -#endif #endif /* Flush the L1 data cache. */ |