diff options
| author | tkasivajhula <tkasivajhula@nvidia.com> | 2010-01-27 15:09:33 -0800 |
|---|---|---|
| committer | tkasivajhula <tkasivajhula@nvidia.com> | 2010-02-05 11:59:47 -0800 |
| commit | eac3c8be27c6ebafa25995b0158d793fea3e2b85 (patch) | |
| tree | 1f0f0f48cc8ef90052e6a6ad715eb9beb7a1fa9b /arch/arm/mach-tegra/idle-t2.c | |
| parent | 0835535d3153952fb3fe13f8be30d6e2dc0524a4 (diff) | |
tegra power: Fix various LP0 (deep sleep) bugs.
Change-Id: Ie35fa84abe09c260827052a0facdee2e220334d4
Diffstat (limited to 'arch/arm/mach-tegra/idle-t2.c')
| -rw-r--r-- | arch/arm/mach-tegra/idle-t2.c | 15 |
1 files changed, 14 insertions, 1 deletions
diff --git a/arch/arm/mach-tegra/idle-t2.c b/arch/arm/mach-tegra/idle-t2.c index ff986f1d0456..134b477937f7 100644 --- a/arch/arm/mach-tegra/idle-t2.c +++ b/arch/arm/mach-tegra/idle-t2.c @@ -36,12 +36,13 @@ extern NvRmDeviceHandle s_hRmGlobal; extern void cpu_ap20_do_lp2(void); +extern void cpu_ap20_do_lp0(void); extern void resume(unsigned int state); extern uintptr_t g_resume, g_contextSavePA, g_contextSaveVA; extern NvU32 g_NumActiveCPUs, g_ArmPerif; extern NvU32 g_enterLP2PA; extern volatile void *g_pPMC, *g_pAHB, *g_pCLK_RST_CONTROLLER; -extern volatile void *g_pEMC, *g_pMC, *g_pAPB_MISC, *g_pIRAM; +extern volatile void *g_pEMC, *g_pMC, *g_pAPB_MISC, *g_pIRAM, *g_pTimerus; #ifdef CONFIG_WAKELOCK extern struct wake_lock main_wake_lock; #endif @@ -187,6 +188,18 @@ void __init NvAp20InitFlowController(void) return; } + NvRmModuleGetBaseAddress(s_hRmGlobal, + NVRM_MODULE_ID(NvRmModuleID_TimerUs, 0), &pa, &len); + + if (NvRmPhysicalMemMap(pa, len, NVOS_MEM_READ_WRITE, + NvOsMemAttribute_Uncached, + (void**)&g_pTimerus)!=NvSuccess) + { + printk(KERN_INFO "failed to map iram; DVFS will not function" + " correctly as a result\n"); + return; + } + s_pFlowCtrl = pTempFc; g_ArmPerif = (NvU32)pTempArmPerif; |