[ARM/tegra] add cryptographic engine (AES) driver

Supports CBC & ECB encryption/decryption, AnsiX9.31 RNG, SSK/SBK/User Key, fine-grain uid/gid access control and ability for privileged user to reset the engine. A device node (/dev/nvaes) is provided to enable access from user-land. based on work done by David Le Tacon (dletacon@nvidia.com) Change-Id: I1a9c29b964ca15e6fec70389c2000306ef604086 Reviewed-on: http://git-master/r/2216 Reviewed-by: David Le Tacon <dletacon@nvidia.com> Reviewed-by: Gary King <gking@nvidia.com> Tested-by: Gary King <gking@nvidia.com>
author: Gary King <gking@nvidia.com> 2010-06-07 09:46:21 -0700
committer: Gary King <gking@nvidia.com> 2010-06-07 12:35:55 -0700
commit: 4dcd7a1c7fc8a02c93f9bdf954dda9eab6cad44f (patch)
tree: f27737f0bd8b03a11902e0ce7dc8ac9627362723 /arch/arm/mach-tegra/include/ap20
parent: 5ce1e0a1a36b2034708366a47a88fce38ef4a252 (diff)
2 files changed, 1604 insertions, 0 deletions
diff --git a/arch/arm/mach-tegra/include/ap20/aravp_bsea_aes.h b/arch/arm/mach-tegra/include/ap20/aravp_bsea_aes.h
new file mode 100644
index 000000000000..85abc56bf201
--- /dev/null
+++ b/arch/arm/mach-tegra/include/ap20/aravp_bsea_aes.h
@@ -0,0 +1,791 @@
+//
+// DO NOT EDIT - generated by simspec!
+//
+
+#ifndef ___ARAVP_BSEA_AES_H_INC_
+#define ___ARAVP_BSEA_AES_H_INC_
+
+/*
+ * Copyright (c) 2009 NVIDIA Corporation.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of the NVIDIA Corporation nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+// Register AVPBSEA_ICMDQUE_WR_0
+#define AVPBSEA_ICMDQUE_WR_0                    _MK_ADDR_CONST(0x0)
+#define AVPBSEA_ICMDQUE_WR_0_SECURE                     0x0
+#define AVPBSEA_ICMDQUE_WR_0_WORD_COUNT                         0x1
+#define AVPBSEA_ICMDQUE_WR_0_RESET_VAL                  _MK_MASK_CONST(0x0)
+#define AVPBSEA_ICMDQUE_WR_0_RESET_MASK                         _MK_MASK_CONST(0x0)
+#define AVPBSEA_ICMDQUE_WR_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define AVPBSEA_ICMDQUE_WR_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define AVPBSEA_ICMDQUE_WR_0_READ_MASK                  _MK_MASK_CONST(0xffffffff)
+#define AVPBSEA_ICMDQUE_WR_0_WRITE_MASK                         _MK_MASK_CONST(0xffffffff)
+#define AVPBSEA_ICMDQUE_WR_0_ICMDQUE_WDATA_SHIFT                        _MK_SHIFT_CONST(0)
+#define AVPBSEA_ICMDQUE_WR_0_ICMDQUE_WDATA_FIELD                        (_MK_MASK_CONST(0xffffffff) << AVPBSEA_ICMDQUE_WR_0_ICMDQUE_WDATA_SHIFT)
+#define AVPBSEA_ICMDQUE_WR_0_ICMDQUE_WDATA_RANGE                        31:0
+#define AVPBSEA_ICMDQUE_WR_0_ICMDQUE_WDATA_WOFFSET                      0x0
+#define AVPBSEA_ICMDQUE_WR_0_ICMDQUE_WDATA_DEFAULT                      _MK_MASK_CONST(0x0)
+#define AVPBSEA_ICMDQUE_WR_0_ICMDQUE_WDATA_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define AVPBSEA_ICMDQUE_WR_0_ICMDQUE_WDATA_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define AVPBSEA_ICMDQUE_WR_0_ICMDQUE_WDATA_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+// Register AVPBSEA_CMDQUE_CONTROL_0
+#define AVPBSEA_CMDQUE_CONTROL_0                        _MK_ADDR_CONST(0x8)
+#define AVPBSEA_CMDQUE_CONTROL_0_SECURE                         0x0
+#define AVPBSEA_CMDQUE_CONTROL_0_WORD_COUNT                     0x1
+#define AVPBSEA_CMDQUE_CONTROL_0_RESET_VAL                      _MK_MASK_CONST(0x703)
+#define AVPBSEA_CMDQUE_CONTROL_0_RESET_MASK                     _MK_MASK_CONST(0xf3f)
+#define AVPBSEA_CMDQUE_CONTROL_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
+#define AVPBSEA_CMDQUE_CONTROL_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define AVPBSEA_CMDQUE_CONTROL_0_READ_MASK                      _MK_MASK_CONST(0xf3f)
+#define AVPBSEA_CMDQUE_CONTROL_0_WRITE_MASK                     _MK_MASK_CONST(0xf3f)
+
+// Register AVPBSEA_INTR_STATUS_0
+#define AVPBSEA_INTR_STATUS_0                   _MK_ADDR_CONST(0x18)
+#define AVPBSEA_INTR_STATUS_0_SECURE                    0x0
+#define AVPBSEA_INTR_STATUS_0_WORD_COUNT                        0x1
+#define AVPBSEA_INTR_STATUS_0_RESET_VAL                         _MK_MASK_CONST(0x58)
+#define AVPBSEA_INTR_STATUS_0_RESET_MASK                        _MK_MASK_CONST(0xff5fca7f)
+#define AVPBSEA_INTR_STATUS_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define AVPBSEA_INTR_STATUS_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define AVPBSEA_INTR_STATUS_0_READ_MASK                         _MK_MASK_CONST(0xff5fca7f)
+#define AVPBSEA_INTR_STATUS_0_WRITE_MASK                        _MK_MASK_CONST(0x5fc802)
+
+// DMA engine is still busy (asserted by DMASetup and de-asserted by DMAFinish) (RO)
+#define AVPBSEA_INTR_STATUS_0_DMA_BUSY_SHIFT                    _MK_SHIFT_CONST(9)
+#define AVPBSEA_INTR_STATUS_0_DMA_BUSY_FIELD                    (_MK_MASK_CONST(0x1) << AVPBSEA_INTR_STATUS_0_DMA_BUSY_SHIFT)
+#define AVPBSEA_INTR_STATUS_0_DMA_BUSY_RANGE                    9:9
+#define AVPBSEA_INTR_STATUS_0_DMA_BUSY_WOFFSET                  0x0
+#define AVPBSEA_INTR_STATUS_0_DMA_BUSY_DEFAULT                  _MK_MASK_CONST(0x0)
+#define AVPBSEA_INTR_STATUS_0_DMA_BUSY_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define AVPBSEA_INTR_STATUS_0_DMA_BUSY_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define AVPBSEA_INTR_STATUS_0_DMA_BUSY_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+// Interactive command queue is empty (RO)
+#define AVPBSEA_INTR_STATUS_0_ICQ_EMPTY_SHIFT                   _MK_SHIFT_CONST(3)
+#define AVPBSEA_INTR_STATUS_0_ICQ_EMPTY_FIELD                   (_MK_MASK_CONST(0x1) << AVPBSEA_INTR_STATUS_0_ICQ_EMPTY_SHIFT)
+#define AVPBSEA_INTR_STATUS_0_ICQ_EMPTY_RANGE                   3:3
+#define AVPBSEA_INTR_STATUS_0_ICQ_EMPTY_WOFFSET                 0x0
+#define AVPBSEA_INTR_STATUS_0_ICQ_EMPTY_DEFAULT                 _MK_MASK_CONST(0x1)
+#define AVPBSEA_INTR_STATUS_0_ICQ_EMPTY_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define AVPBSEA_INTR_STATUS_0_ICQ_EMPTY_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define AVPBSEA_INTR_STATUS_0_ICQ_EMPTY_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+// AES busy (RO)
+#define AVPBSEA_INTR_STATUS_0_ENGINE_BUSY_SHIFT                 _MK_SHIFT_CONST(0)
+#define AVPBSEA_INTR_STATUS_0_ENGINE_BUSY_FIELD                 (_MK_MASK_CONST(0x1) << AVPBSEA_INTR_STATUS_0_ENGINE_BUSY_SHIFT)
+#define AVPBSEA_INTR_STATUS_0_ENGINE_BUSY_RANGE                 0:0
+#define AVPBSEA_INTR_STATUS_0_ENGINE_BUSY_WOFFSET                       0x0
+#define AVPBSEA_INTR_STATUS_0_ENGINE_BUSY_DEFAULT                       _MK_MASK_CONST(0x0)
+#define AVPBSEA_INTR_STATUS_0_ENGINE_BUSY_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define AVPBSEA_INTR_STATUS_0_ENGINE_BUSY_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define AVPBSEA_INTR_STATUS_0_ENGINE_BUSY_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// Register AVPBSEA_BSE_CONFIG_0
+#define AVPBSEA_BSE_CONFIG_0                    _MK_ADDR_CONST(0x44)
+#define AVPBSEA_BSE_CONFIG_0_SECURE                     0x0
+#define AVPBSEA_BSE_CONFIG_0_WORD_COUNT                         0x1
+#define AVPBSEA_BSE_CONFIG_0_RESET_VAL                  _MK_MASK_CONST(0x2405)
+#define AVPBSEA_BSE_CONFIG_0_RESET_MASK                         _MK_MASK_CONST(0xf4df)
+#define AVPBSEA_BSE_CONFIG_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define AVPBSEA_BSE_CONFIG_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define AVPBSEA_BSE_CONFIG_0_READ_MASK                  _MK_MASK_CONST(0xf4df)
+#define AVPBSEA_BSE_CONFIG_0_WRITE_MASK                         _MK_MASK_CONST(0xf4df)
+
+// Must be set to 1.
+#define AVPBSEA_BSE_CONFIG_0_ENDIAN_ENB_SHIFT                   _MK_SHIFT_CONST(10)
+#define AVPBSEA_BSE_CONFIG_0_ENDIAN_ENB_FIELD                   (_MK_MASK_CONST(0x1) << AVPBSEA_BSE_CONFIG_0_ENDIAN_ENB_SHIFT)
+#define AVPBSEA_BSE_CONFIG_0_ENDIAN_ENB_RANGE                   10:10
+#define AVPBSEA_BSE_CONFIG_0_ENDIAN_ENB_WOFFSET                 0x0
+#define AVPBSEA_BSE_CONFIG_0_ENDIAN_ENB_DEFAULT                 _MK_MASK_CONST(0x1)
+#define AVPBSEA_BSE_CONFIG_0_ENDIAN_ENB_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define AVPBSEA_BSE_CONFIG_0_ENDIAN_ENB_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define AVPBSEA_BSE_CONFIG_0_ENDIAN_ENB_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+// 00000: CRYPTO mode
+#define AVPBSEA_BSE_CONFIG_0_BSE_MODE_SEL_SHIFT                 _MK_SHIFT_CONST(0)
+#define AVPBSEA_BSE_CONFIG_0_BSE_MODE_SEL_FIELD                 (_MK_MASK_CONST(0x1f) << AVPBSEA_BSE_CONFIG_0_BSE_MODE_SEL_SHIFT)
+#define AVPBSEA_BSE_CONFIG_0_BSE_MODE_SEL_RANGE                 4:0
+#define AVPBSEA_BSE_CONFIG_0_BSE_MODE_SEL_WOFFSET                       0x0
+#define AVPBSEA_BSE_CONFIG_0_BSE_MODE_SEL_DEFAULT                       _MK_MASK_CONST(0x5)
+#define AVPBSEA_BSE_CONFIG_0_BSE_MODE_SEL_DEFAULT_MASK                  _MK_MASK_CONST(0x1f)
+#define AVPBSEA_BSE_CONFIG_0_BSE_MODE_SEL_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define AVPBSEA_BSE_CONFIG_0_BSE_MODE_SEL_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// Register AVPBSEA_SECURE_DEST_ADDR_0
+#define AVPBSEA_SECURE_DEST_ADDR_0                      _MK_ADDR_CONST(0x100)
+#define AVPBSEA_SECURE_DEST_ADDR_0_SECURE                       0x0
+#define AVPBSEA_SECURE_DEST_ADDR_0_WORD_COUNT                   0x1
+#define AVPBSEA_SECURE_DEST_ADDR_0_RESET_VAL                    _MK_MASK_CONST(0x0)
+#define AVPBSEA_SECURE_DEST_ADDR_0_RESET_MASK                   _MK_MASK_CONST(0xffffffff)
+#define AVPBSEA_SECURE_DEST_ADDR_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define AVPBSEA_SECURE_DEST_ADDR_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define AVPBSEA_SECURE_DEST_ADDR_0_READ_MASK                    _MK_MASK_CONST(0xffffffff)
+#define AVPBSEA_SECURE_DEST_ADDR_0_WRITE_MASK                   _MK_MASK_CONST(0xffffffff)
+
+// SECURE engine: write back destination write address
+#define AVPBSEA_SECURE_DEST_ADDR_0_SECURE_DEST_ADDR_SHIFT                       _MK_SHIFT_CONST(0)
+#define AVPBSEA_SECURE_DEST_ADDR_0_SECURE_DEST_ADDR_FIELD                       (_MK_MASK_CONST(0xffffffff) << AVPBSEA_SECURE_DEST_ADDR_0_SECURE_DEST_ADDR_SHIFT)
+#define AVPBSEA_SECURE_DEST_ADDR_0_SECURE_DEST_ADDR_RANGE                       31:0
+#define AVPBSEA_SECURE_DEST_ADDR_0_SECURE_DEST_ADDR_WOFFSET                     0x0
+#define AVPBSEA_SECURE_DEST_ADDR_0_SECURE_DEST_ADDR_DEFAULT                     _MK_MASK_CONST(0x0)
+#define AVPBSEA_SECURE_DEST_ADDR_0_SECURE_DEST_ADDR_DEFAULT_MASK                        _MK_MASK_CONST(0xffffffff)
+#define AVPBSEA_SECURE_DEST_ADDR_0_SECURE_DEST_ADDR_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define AVPBSEA_SECURE_DEST_ADDR_0_SECURE_DEST_ADDR_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+// Register AVPBSEA_SECURE_INPUT_SELECT_0
+#define AVPBSEA_SECURE_INPUT_SELECT_0                   _MK_ADDR_CONST(0x104)
+#define AVPBSEA_SECURE_INPUT_SELECT_0_SECURE                    0x0
+#define AVPBSEA_SECURE_INPUT_SELECT_0_WORD_COUNT                        0x1
+#define AVPBSEA_SECURE_INPUT_SELECT_0_RESET_VAL                         _MK_MASK_CONST(0x10800000)
+#define AVPBSEA_SECURE_INPUT_SELECT_0_RESET_MASK                        _MK_MASK_CONST(0xffff0fff)
+#define AVPBSEA_SECURE_INPUT_SELECT_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define AVPBSEA_SECURE_INPUT_SELECT_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define AVPBSEA_SECURE_INPUT_SELECT_0_READ_MASK                         _MK_MASK_CONST(0xffff0fff)
+#define AVPBSEA_SECURE_INPUT_SELECT_0_WRITE_MASK                        _MK_MASK_CONST(0xffff0fff)
+
+// SECURE engine: random number generator enable
+#define AVPBSEA_SECURE_INPUT_SELECT_0_SECURE_RNG_ENB_SHIFT                      _MK_SHIFT_CONST(11)
+#define AVPBSEA_SECURE_INPUT_SELECT_0_SECURE_RNG_ENB_FIELD                      (_MK_MASK_CONST(0x1) << AVPBSEA_SECURE_INPUT_SELECT_0_SECURE_RNG_ENB_SHIFT)
+#define AVPBSEA_SECURE_INPUT_SELECT_0_SECURE_RNG_ENB_RANGE                      11:11
+#define AVPBSEA_SECURE_INPUT_SELECT_0_SECURE_RNG_ENB_WOFFSET                    0x0
+#define AVPBSEA_SECURE_INPUT_SELECT_0_SECURE_RNG_ENB_DEFAULT                    _MK_MASK_CONST(0x0)
+#define AVPBSEA_SECURE_INPUT_SELECT_0_SECURE_RNG_ENB_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define AVPBSEA_SECURE_INPUT_SELECT_0_SECURE_RNG_ENB_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define AVPBSEA_SECURE_INPUT_SELECT_0_SECURE_RNG_ENB_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// SECURE engine: Init vector select
+#define AVPBSEA_SECURE_INPUT_SELECT_0_SECURE_IV_SELECT_SHIFT                    _MK_SHIFT_CONST(10)
+#define AVPBSEA_SECURE_INPUT_SELECT_0_SECURE_IV_SELECT_FIELD                    (_MK_MASK_CONST(0x1) << AVPBSEA_SECURE_INPUT_SELECT_0_SECURE_IV_SELECT_SHIFT)
+#define AVPBSEA_SECURE_INPUT_SELECT_0_SECURE_IV_SELECT_RANGE                    10:10
+#define AVPBSEA_SECURE_INPUT_SELECT_0_SECURE_IV_SELECT_WOFFSET                  0x0
+#define AVPBSEA_SECURE_INPUT_SELECT_0_SECURE_IV_SELECT_DEFAULT                  _MK_MASK_CONST(0x0)
+#define AVPBSEA_SECURE_INPUT_SELECT_0_SECURE_IV_SELECT_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define AVPBSEA_SECURE_INPUT_SELECT_0_SECURE_IV_SELECT_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define AVPBSEA_SECURE_INPUT_SELECT_0_SECURE_IV_SELECT_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+// CRYPTO/inv-CRYPTO core selection (use for shiftrow direction)
+#define AVPBSEA_SECURE_INPUT_SELECT_0_SECURE_CORE_SEL_SHIFT                     _MK_SHIFT_CONST(9)
+#define AVPBSEA_SECURE_INPUT_SELECT_0_SECURE_CORE_SEL_FIELD                     (_MK_MASK_CONST(0x1) << AVPBSEA_SECURE_INPUT_SELECT_0_SECURE_CORE_SEL_SHIFT)
+#define AVPBSEA_SECURE_INPUT_SELECT_0_SECURE_CORE_SEL_RANGE                     9:9
+#define AVPBSEA_SECURE_INPUT_SELECT_0_SECURE_CORE_SEL_WOFFSET                   0x0
+#define AVPBSEA_SECURE_INPUT_SELECT_0_SECURE_CORE_SEL_DEFAULT                   _MK_MASK_CONST(0x0)
+#define AVPBSEA_SECURE_INPUT_SELECT_0_SECURE_CORE_SEL_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define AVPBSEA_SECURE_INPUT_SELECT_0_SECURE_CORE_SEL_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define AVPBSEA_SECURE_INPUT_SELECT_0_SECURE_CORE_SEL_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+// Vector RAM select
+// 00: From AHB input vector
+// 01: reserved
+// 10: Init Vector for first round and CRYPTO output for the rest rounds
+// 11: Init Vector for the first round and previous AHB input for the rest rounds
+#define AVPBSEA_SECURE_INPUT_SELECT_0_SECURE_VCTRAM_SEL_SHIFT                   _MK_SHIFT_CONST(7)
+#define AVPBSEA_SECURE_INPUT_SELECT_0_SECURE_VCTRAM_SEL_FIELD                   (_MK_MASK_CONST(0x3) << AVPBSEA_SECURE_INPUT_SELECT_0_SECURE_VCTRAM_SEL_SHIFT)
+#define AVPBSEA_SECURE_INPUT_SELECT_0_SECURE_VCTRAM_SEL_RANGE                   8:7
+#define AVPBSEA_SECURE_INPUT_SELECT_0_SECURE_VCTRAM_SEL_WOFFSET                 0x0
+#define AVPBSEA_SECURE_INPUT_SELECT_0_SECURE_VCTRAM_SEL_DEFAULT                 _MK_MASK_CONST(0x0)
+#define AVPBSEA_SECURE_INPUT_SELECT_0_SECURE_VCTRAM_SEL_DEFAULT_MASK                    _MK_MASK_CONST(0x3)
+#define AVPBSEA_SECURE_INPUT_SELECT_0_SECURE_VCTRAM_SEL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define AVPBSEA_SECURE_INPUT_SELECT_0_SECURE_VCTRAM_SEL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+// CRYPTO input select
+// 00: From AHB input vector
+// 01: reserved
+// 10: Init Vector for first round and CRYPTO output for the rest rounds
+// 11: Counter
+#define AVPBSEA_SECURE_INPUT_SELECT_0_SECURE_INPUT_SEL_SHIFT                    _MK_SHIFT_CONST(5)
+#define AVPBSEA_SECURE_INPUT_SELECT_0_SECURE_INPUT_SEL_FIELD                    (_MK_MASK_CONST(0x3) << AVPBSEA_SECURE_INPUT_SELECT_0_SECURE_INPUT_SEL_SHIFT)
+#define AVPBSEA_SECURE_INPUT_SELECT_0_SECURE_INPUT_SEL_RANGE                    6:5
+#define AVPBSEA_SECURE_INPUT_SELECT_0_SECURE_INPUT_SEL_WOFFSET                  0x0
+#define AVPBSEA_SECURE_INPUT_SELECT_0_SECURE_INPUT_SEL_DEFAULT                  _MK_MASK_CONST(0x0)
+#define AVPBSEA_SECURE_INPUT_SELECT_0_SECURE_INPUT_SEL_DEFAULT_MASK                     _MK_MASK_CONST(0x3)
+#define AVPBSEA_SECURE_INPUT_SELECT_0_SECURE_INPUT_SEL_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define AVPBSEA_SECURE_INPUT_SELECT_0_SECURE_INPUT_SEL_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+// CRYPTO XOR position
+// 0x: Bypass
+// 10: top, before CRYPTO
+// 11: bottom, after CRYPTO
+#define AVPBSEA_SECURE_INPUT_SELECT_0_SECURE_XOR_POS_SHIFT                      _MK_SHIFT_CONST(3)
+#define AVPBSEA_SECURE_INPUT_SELECT_0_SECURE_XOR_POS_FIELD                      (_MK_MASK_CONST(0x3) << AVPBSEA_SECURE_INPUT_SELECT_0_SECURE_XOR_POS_SHIFT)
+#define AVPBSEA_SECURE_INPUT_SELECT_0_SECURE_XOR_POS_RANGE                      4:3
+#define AVPBSEA_SECURE_INPUT_SELECT_0_SECURE_XOR_POS_WOFFSET                    0x0
+#define AVPBSEA_SECURE_INPUT_SELECT_0_SECURE_XOR_POS_DEFAULT                    _MK_MASK_CONST(0x0)
+#define AVPBSEA_SECURE_INPUT_SELECT_0_SECURE_XOR_POS_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
+#define AVPBSEA_SECURE_INPUT_SELECT_0_SECURE_XOR_POS_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define AVPBSEA_SECURE_INPUT_SELECT_0_SECURE_XOR_POS_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// CYRPTO hash enable
+#define AVPBSEA_SECURE_INPUT_SELECT_0_SECURE_HASH_ENB_SHIFT                     _MK_SHIFT_CONST(2)
+#define AVPBSEA_SECURE_INPUT_SELECT_0_SECURE_HASH_ENB_FIELD                     (_MK_MASK_CONST(0x1) << AVPBSEA_SECURE_INPUT_SELECT_0_SECURE_HASH_ENB_SHIFT)
+#define AVPBSEA_SECURE_INPUT_SELECT_0_SECURE_HASH_ENB_RANGE                     2:2
+#define AVPBSEA_SECURE_INPUT_SELECT_0_SECURE_HASH_ENB_WOFFSET                   0x0
+#define AVPBSEA_SECURE_INPUT_SELECT_0_SECURE_HASH_ENB_DEFAULT                   _MK_MASK_CONST(0x0)
+#define AVPBSEA_SECURE_INPUT_SELECT_0_SECURE_HASH_ENB_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define AVPBSEA_SECURE_INPUT_SELECT_0_SECURE_HASH_ENB_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define AVPBSEA_SECURE_INPUT_SELECT_0_SECURE_HASH_ENB_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+// CYRPTO hash destination, this is valid only when SECURE_HASH_ENB = 1
+// 0: Do not write output to memory pointed by destination address.
+//    Data can be read from HASH_RESULT
+// 1: Write final 128-bit output to memory pointed by destination address
+#define AVPBSEA_SECURE_INPUT_SELECT_0_SECURE_HASH_DEST_SHIFT                    _MK_SHIFT_CONST(1)
+#define AVPBSEA_SECURE_INPUT_SELECT_0_SECURE_HASH_DEST_FIELD                    (_MK_MASK_CONST(0x1) << AVPBSEA_SECURE_INPUT_SELECT_0_SECURE_HASH_DEST_SHIFT)
+#define AVPBSEA_SECURE_INPUT_SELECT_0_SECURE_HASH_DEST_RANGE                    1:1
+#define AVPBSEA_SECURE_INPUT_SELECT_0_SECURE_HASH_DEST_WOFFSET                  0x0
+#define AVPBSEA_SECURE_INPUT_SELECT_0_SECURE_HASH_DEST_DEFAULT                  _MK_MASK_CONST(0x0)
+#define AVPBSEA_SECURE_INPUT_SELECT_0_SECURE_HASH_DEST_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define AVPBSEA_SECURE_INPUT_SELECT_0_SECURE_HASH_DEST_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define AVPBSEA_SECURE_INPUT_SELECT_0_SECURE_HASH_DEST_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+// Register AVPBSEA_SECURE_CONFIG_0
+#define AVPBSEA_SECURE_CONFIG_0                 _MK_ADDR_CONST(0x108)
+#define AVPBSEA_SECURE_CONFIG_0_SECURE                  0x0
+#define AVPBSEA_SECURE_CONFIG_0_WORD_COUNT                      0x1
+#define AVPBSEA_SECURE_CONFIG_0_RESET_VAL                       _MK_MASK_CONST(0x0)
+#define AVPBSEA_SECURE_CONFIG_0_RESET_MASK                      _MK_MASK_CONST(0x1ffffff)
+#define AVPBSEA_SECURE_CONFIG_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define AVPBSEA_SECURE_CONFIG_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define AVPBSEA_SECURE_CONFIG_0_READ_MASK                       _MK_MASK_CONST(0x1ffffff)
+#define AVPBSEA_SECURE_CONFIG_0_WRITE_MASK                      _MK_MASK_CONST(0x1ffffff)
+
+// 5-bit index to select between the 8-keys(value greater than 7 is reserved)
+#define AVPBSEA_SECURE_CONFIG_0_SECURE_KEY_INDEX_SHIFT                  _MK_SHIFT_CONST(20)
+#define AVPBSEA_SECURE_CONFIG_0_SECURE_KEY_INDEX_FIELD                  (_MK_MASK_CONST(0x1f) << AVPBSEA_SECURE_CONFIG_0_SECURE_KEY_INDEX_SHIFT)
+#define AVPBSEA_SECURE_CONFIG_0_SECURE_KEY_INDEX_RANGE                  24:20
+#define AVPBSEA_SECURE_CONFIG_0_SECURE_KEY_INDEX_WOFFSET                        0x0
+#define AVPBSEA_SECURE_CONFIG_0_SECURE_KEY_INDEX_DEFAULT                        _MK_MASK_CONST(0x0)
+#define AVPBSEA_SECURE_CONFIG_0_SECURE_KEY_INDEX_DEFAULT_MASK                   _MK_MASK_CONST(0x1f)
+#define AVPBSEA_SECURE_CONFIG_0_SECURE_KEY_INDEX_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define AVPBSEA_SECURE_CONFIG_0_SECURE_KEY_INDEX_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// Register AVPBSEA_SECURE_CONFIG_EXT_0
+#define AVPBSEA_SECURE_CONFIG_EXT_0                     _MK_ADDR_CONST(0x10c)
+#define AVPBSEA_SECURE_CONFIG_EXT_0_SECURE                      0x0
+#define AVPBSEA_SECURE_CONFIG_EXT_0_WORD_COUNT                  0x1
+#define AVPBSEA_SECURE_CONFIG_EXT_0_RESET_VAL                   _MK_MASK_CONST(0x10000)
+#define AVPBSEA_SECURE_CONFIG_EXT_0_RESET_MASK                  _MK_MASK_CONST(0xffff8000)
+#define AVPBSEA_SECURE_CONFIG_EXT_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define AVPBSEA_SECURE_CONFIG_EXT_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define AVPBSEA_SECURE_CONFIG_EXT_0_READ_MASK                   _MK_MASK_CONST(0xffff8000)
+#define AVPBSEA_SECURE_CONFIG_EXT_0_WRITE_MASK                  _MK_MASK_CONST(0xffff8000)
+
+// CRYPTO encryption/decryption with 16B*N offset.
+// 0: every 16B is encrypted/decrypted
+// N: first 16B is encrypted/decrypted and N*16B is not
+#define AVPBSEA_SECURE_CONFIG_EXT_0_SECURE_OFFSET_CNT_SHIFT                     _MK_SHIFT_CONST(24)
+#define AVPBSEA_SECURE_CONFIG_EXT_0_SECURE_OFFSET_CNT_FIELD                     (_MK_MASK_CONST(0xff) << AVPBSEA_SECURE_CONFIG_EXT_0_SECURE_OFFSET_CNT_SHIFT)
+#define AVPBSEA_SECURE_CONFIG_EXT_0_SECURE_OFFSET_CNT_RANGE                     31:24
+#define AVPBSEA_SECURE_CONFIG_EXT_0_SECURE_OFFSET_CNT_WOFFSET                   0x0
+#define AVPBSEA_SECURE_CONFIG_EXT_0_SECURE_OFFSET_CNT_DEFAULT                   _MK_MASK_CONST(0x0)
+#define AVPBSEA_SECURE_CONFIG_EXT_0_SECURE_OFFSET_CNT_DEFAULT_MASK                      _MK_MASK_CONST(0xff)
+#define AVPBSEA_SECURE_CONFIG_EXT_0_SECURE_OFFSET_CNT_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define AVPBSEA_SECURE_CONFIG_EXT_0_SECURE_OFFSET_CNT_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+// Must be set to 0. Anything else is illegal.
+#define AVPBSEA_SECURE_CONFIG_EXT_0_SECURE_KEY_SCH_DIS_SHIFT                    _MK_SHIFT_CONST(15)
+#define AVPBSEA_SECURE_CONFIG_EXT_0_SECURE_KEY_SCH_DIS_FIELD                    (_MK_MASK_CONST(0x1) << AVPBSEA_SECURE_CONFIG_EXT_0_SECURE_KEY_SCH_DIS_SHIFT)
+#define AVPBSEA_SECURE_CONFIG_EXT_0_SECURE_KEY_SCH_DIS_RANGE                    15:15
+#define AVPBSEA_SECURE_CONFIG_EXT_0_SECURE_KEY_SCH_DIS_WOFFSET                  0x0
+#define AVPBSEA_SECURE_CONFIG_EXT_0_SECURE_KEY_SCH_DIS_DEFAULT                  _MK_MASK_CONST(0x0)
+#define AVPBSEA_SECURE_CONFIG_EXT_0_SECURE_KEY_SCH_DIS_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define AVPBSEA_SECURE_CONFIG_EXT_0_SECURE_KEY_SCH_DIS_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define AVPBSEA_SECURE_CONFIG_EXT_0_SECURE_KEY_SCH_DIS_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+// Register AVPBSEA_SECURE_SECURITY_0
+#define AVPBSEA_SECURE_SECURITY_0                       _MK_ADDR_CONST(0x110)
+#define AVPBSEA_SECURE_SECURITY_0_SECURE                        0x0
+#define AVPBSEA_SECURE_SECURITY_0_WORD_COUNT                    0x1
+#define AVPBSEA_SECURE_SECURITY_0_RESET_VAL                     _MK_MASK_CONST(0x6)
+#define AVPBSEA_SECURE_SECURITY_0_RESET_MASK                    _MK_MASK_CONST(0x7)
+#define AVPBSEA_SECURE_SECURITY_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
+#define AVPBSEA_SECURE_SECURITY_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define AVPBSEA_SECURE_SECURITY_0_READ_MASK                     _MK_MASK_CONST(0x7)
+#define AVPBSEA_SECURE_SECURITY_0_WRITE_MASK                    _MK_MASK_CONST(0x7)
+
+// Sticky bit. Must be set to 0.
+#define AVPBSEA_SECURE_SECURITY_0_KEY_SCHED_READ_SHIFT                  _MK_SHIFT_CONST(1)
+#define AVPBSEA_SECURE_SECURITY_0_KEY_SCHED_READ_FIELD                  (_MK_MASK_CONST(0x1) << AVPBSEA_SECURE_SECURITY_0_KEY_SCHED_READ_SHIFT)
+#define AVPBSEA_SECURE_SECURITY_0_KEY_SCHED_READ_RANGE                  1:1
+#define AVPBSEA_SECURE_SECURITY_0_KEY_SCHED_READ_WOFFSET                        0x0
+#define AVPBSEA_SECURE_SECURITY_0_KEY_SCHED_READ_DEFAULT                        _MK_MASK_CONST(0x1)
+#define AVPBSEA_SECURE_SECURITY_0_KEY_SCHED_READ_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define AVPBSEA_SECURE_SECURITY_0_KEY_SCHED_READ_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define AVPBSEA_SECURE_SECURITY_0_KEY_SCHED_READ_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// Sticky bit. When this value is "1", crypto engine will be disabled.
+// Software will not be able to use the crypto engine until the next system reset.
+#define AVPBSEA_SECURE_SECURITY_0_SECURE_ENG_DIS_SHIFT                  _MK_SHIFT_CONST(0)
+#define AVPBSEA_SECURE_SECURITY_0_SECURE_ENG_DIS_FIELD                  (_MK_MASK_CONST(0x1) << AVPBSEA_SECURE_SECURITY_0_SECURE_ENG_DIS_SHIFT)
+#define AVPBSEA_SECURE_SECURITY_0_SECURE_ENG_DIS_RANGE                  0:0
+#define AVPBSEA_SECURE_SECURITY_0_SECURE_ENG_DIS_WOFFSET                        0x0
+#define AVPBSEA_SECURE_SECURITY_0_SECURE_ENG_DIS_DEFAULT                        _MK_MASK_CONST(0x0)
+#define AVPBSEA_SECURE_SECURITY_0_SECURE_ENG_DIS_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define AVPBSEA_SECURE_SECURITY_0_SECURE_ENG_DIS_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define AVPBSEA_SECURE_SECURITY_0_SECURE_ENG_DIS_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// Register AVPBSEA_SECURE_HASH_RESULT0_0
+#define AVPBSEA_SECURE_HASH_RESULT0_0                   _MK_ADDR_CONST(0x120)
+#define AVPBSEA_SECURE_HASH_RESULT0_0_SECURE                    0x0
+#define AVPBSEA_SECURE_HASH_RESULT0_0_WORD_COUNT                        0x1
+#define AVPBSEA_SECURE_HASH_RESULT0_0_RESET_VAL                         _MK_MASK_CONST(0x0)
+#define AVPBSEA_SECURE_HASH_RESULT0_0_RESET_MASK                        _MK_MASK_CONST(0xffffffff)
+#define AVPBSEA_SECURE_HASH_RESULT0_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define AVPBSEA_SECURE_HASH_RESULT0_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define AVPBSEA_SECURE_HASH_RESULT0_0_READ_MASK                         _MK_MASK_CONST(0xffffffff)
+#define AVPBSEA_SECURE_HASH_RESULT0_0_WRITE_MASK                        _MK_MASK_CONST(0xffffffff)
+
+// CRYPTO Hash result [31:0]
+#define AVPBSEA_SECURE_HASH_RESULT0_0_SECURE_HASH_RESULT0_SHIFT                 _MK_SHIFT_CONST(0)
+#define AVPBSEA_SECURE_HASH_RESULT0_0_SECURE_HASH_RESULT0_FIELD                 (_MK_MASK_CONST(0xffffffff) << AVPBSEA_SECURE_HASH_RESULT0_0_SECURE_HASH_RESULT0_SHIFT)
+#define AVPBSEA_SECURE_HASH_RESULT0_0_SECURE_HASH_RESULT0_RANGE                 31:0
+#define AVPBSEA_SECURE_HASH_RESULT0_0_SECURE_HASH_RESULT0_WOFFSET                       0x0
+#define AVPBSEA_SECURE_HASH_RESULT0_0_SECURE_HASH_RESULT0_DEFAULT                       _MK_MASK_CONST(0x0)
+#define AVPBSEA_SECURE_HASH_RESULT0_0_SECURE_HASH_RESULT0_DEFAULT_MASK                  _MK_MASK_CONST(0xffffffff)
+#define AVPBSEA_SECURE_HASH_RESULT0_0_SECURE_HASH_RESULT0_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define AVPBSEA_SECURE_HASH_RESULT0_0_SECURE_HASH_RESULT0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// Register AVPBSEA_SECURE_HASH_RESULT1_0
+#define AVPBSEA_SECURE_HASH_RESULT1_0                   _MK_ADDR_CONST(0x124)
+#define AVPBSEA_SECURE_HASH_RESULT1_0_SECURE                    0x0
+#define AVPBSEA_SECURE_HASH_RESULT1_0_WORD_COUNT                        0x1
+#define AVPBSEA_SECURE_HASH_RESULT1_0_RESET_VAL                         _MK_MASK_CONST(0x0)
+#define AVPBSEA_SECURE_HASH_RESULT1_0_RESET_MASK                        _MK_MASK_CONST(0xffffffff)
+#define AVPBSEA_SECURE_HASH_RESULT1_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define AVPBSEA_SECURE_HASH_RESULT1_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define AVPBSEA_SECURE_HASH_RESULT1_0_READ_MASK                         _MK_MASK_CONST(0xffffffff)
+#define AVPBSEA_SECURE_HASH_RESULT1_0_WRITE_MASK                        _MK_MASK_CONST(0xffffffff)
+
+// CRYPTO Hash result [63:32]
+#define AVPBSEA_SECURE_HASH_RESULT1_0_SECURE_HASH_RESULT1_SHIFT                 _MK_SHIFT_CONST(0)
+#define AVPBSEA_SECURE_HASH_RESULT1_0_SECURE_HASH_RESULT1_FIELD                 (_MK_MASK_CONST(0xffffffff) << AVPBSEA_SECURE_HASH_RESULT1_0_SECURE_HASH_RESULT1_SHIFT)
+#define AVPBSEA_SECURE_HASH_RESULT1_0_SECURE_HASH_RESULT1_RANGE                 31:0
+#define AVPBSEA_SECURE_HASH_RESULT1_0_SECURE_HASH_RESULT1_WOFFSET                       0x0
+#define AVPBSEA_SECURE_HASH_RESULT1_0_SECURE_HASH_RESULT1_DEFAULT                       _MK_MASK_CONST(0x0)
+#define AVPBSEA_SECURE_HASH_RESULT1_0_SECURE_HASH_RESULT1_DEFAULT_MASK                  _MK_MASK_CONST(0xffffffff)
+#define AVPBSEA_SECURE_HASH_RESULT1_0_SECURE_HASH_RESULT1_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define AVPBSEA_SECURE_HASH_RESULT1_0_SECURE_HASH_RESULT1_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// Register AVPBSEA_SECURE_HASH_RESULT2_0
+#define AVPBSEA_SECURE_HASH_RESULT2_0                   _MK_ADDR_CONST(0x128)
+#define AVPBSEA_SECURE_HASH_RESULT2_0_SECURE                    0x0
+#define AVPBSEA_SECURE_HASH_RESULT2_0_WORD_COUNT                        0x1
+#define AVPBSEA_SECURE_HASH_RESULT2_0_RESET_VAL                         _MK_MASK_CONST(0x0)
+#define AVPBSEA_SECURE_HASH_RESULT2_0_RESET_MASK                        _MK_MASK_CONST(0xffffffff)
+#define AVPBSEA_SECURE_HASH_RESULT2_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define AVPBSEA_SECURE_HASH_RESULT2_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define AVPBSEA_SECURE_HASH_RESULT2_0_READ_MASK                         _MK_MASK_CONST(0xffffffff)
+#define AVPBSEA_SECURE_HASH_RESULT2_0_WRITE_MASK                        _MK_MASK_CONST(0xffffffff)
+
+// CRYPTO Hash result [95:64]
+#define AVPBSEA_SECURE_HASH_RESULT2_0_SECURE_HASH_RESULT2_SHIFT                 _MK_SHIFT_CONST(0)
+#define AVPBSEA_SECURE_HASH_RESULT2_0_SECURE_HASH_RESULT2_FIELD                 (_MK_MASK_CONST(0xffffffff) << AVPBSEA_SECURE_HASH_RESULT2_0_SECURE_HASH_RESULT2_SHIFT)
+#define AVPBSEA_SECURE_HASH_RESULT2_0_SECURE_HASH_RESULT2_RANGE                 31:0
+#define AVPBSEA_SECURE_HASH_RESULT2_0_SECURE_HASH_RESULT2_WOFFSET                       0x0
+#define AVPBSEA_SECURE_HASH_RESULT2_0_SECURE_HASH_RESULT2_DEFAULT                       _MK_MASK_CONST(0x0)
+#define AVPBSEA_SECURE_HASH_RESULT2_0_SECURE_HASH_RESULT2_DEFAULT_MASK                  _MK_MASK_CONST(0xffffffff)
+#define AVPBSEA_SECURE_HASH_RESULT2_0_SECURE_HASH_RESULT2_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define AVPBSEA_SECURE_HASH_RESULT2_0_SECURE_HASH_RESULT2_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// Register AVPBSEA_SECURE_HASH_RESULT3_0
+#define AVPBSEA_SECURE_HASH_RESULT3_0                   _MK_ADDR_CONST(0x12c)
+#define AVPBSEA_SECURE_HASH_RESULT3_0_SECURE                    0x0
+#define AVPBSEA_SECURE_HASH_RESULT3_0_WORD_COUNT                        0x1
+#define AVPBSEA_SECURE_HASH_RESULT3_0_RESET_VAL                         _MK_MASK_CONST(0x0)
+#define AVPBSEA_SECURE_HASH_RESULT3_0_RESET_MASK                        _MK_MASK_CONST(0xffffffff)
+#define AVPBSEA_SECURE_HASH_RESULT3_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define AVPBSEA_SECURE_HASH_RESULT3_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define AVPBSEA_SECURE_HASH_RESULT3_0_READ_MASK                         _MK_MASK_CONST(0xffffffff)
+#define AVPBSEA_SECURE_HASH_RESULT3_0_WRITE_MASK                        _MK_MASK_CONST(0xffffffff)
+
+// CRYPTO Hash result [127:96]
+#define AVPBSEA_SECURE_HASH_RESULT3_0_SECURE_HASH_RESULT3_SHIFT                 _MK_SHIFT_CONST(0)
+#define AVPBSEA_SECURE_HASH_RESULT3_0_SECURE_HASH_RESULT3_FIELD                 (_MK_MASK_CONST(0xffffffff) << AVPBSEA_SECURE_HASH_RESULT3_0_SECURE_HASH_RESULT3_SHIFT)
+#define AVPBSEA_SECURE_HASH_RESULT3_0_SECURE_HASH_RESULT3_RANGE                 31:0
+#define AVPBSEA_SECURE_HASH_RESULT3_0_SECURE_HASH_RESULT3_WOFFSET                       0x0
+#define AVPBSEA_SECURE_HASH_RESULT3_0_SECURE_HASH_RESULT3_DEFAULT                       _MK_MASK_CONST(0x0)
+#define AVPBSEA_SECURE_HASH_RESULT3_0_SECURE_HASH_RESULT3_DEFAULT_MASK                  _MK_MASK_CONST(0xffffffff)
+#define AVPBSEA_SECURE_HASH_RESULT3_0_SECURE_HASH_RESULT3_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define AVPBSEA_SECURE_HASH_RESULT3_0_SECURE_HASH_RESULT3_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// Register AVPBSEA_SECURE_SEC_SEL0_0
+#define AVPBSEA_SECURE_SEC_SEL0_0                       _MK_ADDR_CONST(0x140)
+#define AVPBSEA_SECURE_SEC_SEL0_0_SECURE                        0x0
+#define AVPBSEA_SECURE_SEC_SEL0_0_WORD_COUNT                    0x1
+#define AVPBSEA_SECURE_SEC_SEL0_0_RESET_VAL                     _MK_MASK_CONST(0x1f)
+#define AVPBSEA_SECURE_SEC_SEL0_0_RESET_MASK                    _MK_MASK_CONST(0x1f)
+#define AVPBSEA_SECURE_SEC_SEL0_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
+#define AVPBSEA_SECURE_SEC_SEL0_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define AVPBSEA_SECURE_SEC_SEL0_0_READ_MASK                     _MK_MASK_CONST(0x1f)
+#define AVPBSEA_SECURE_SEC_SEL0_0_WRITE_MASK                    _MK_MASK_CONST(0x1f)
+
+// Sticky bit, When set to "0", it will not be possible to change the value of this bit until the next system reset.
+// When this value is "0", software will not be able to update key 0 and original initialization vector 0.
+#define AVPBSEA_SECURE_SEC_SEL0_0_KEYUPDATE_ENB0_SHIFT                  _MK_SHIFT_CONST(1)
+#define AVPBSEA_SECURE_SEC_SEL0_0_KEYUPDATE_ENB0_FIELD                  (_MK_MASK_CONST(0x1) << AVPBSEA_SECURE_SEC_SEL0_0_KEYUPDATE_ENB0_SHIFT)
+#define AVPBSEA_SECURE_SEC_SEL0_0_KEYUPDATE_ENB0_RANGE                  1:1
+#define AVPBSEA_SECURE_SEC_SEL0_0_KEYUPDATE_ENB0_WOFFSET                        0x0
+#define AVPBSEA_SECURE_SEC_SEL0_0_KEYUPDATE_ENB0_DEFAULT                        _MK_MASK_CONST(0x1)
+#define AVPBSEA_SECURE_SEC_SEL0_0_KEYUPDATE_ENB0_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define AVPBSEA_SECURE_SEC_SEL0_0_KEYUPDATE_ENB0_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define AVPBSEA_SECURE_SEC_SEL0_0_KEYUPDATE_ENB0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// Sticky bit, When set to "0", it will not be possible to change the value of this bit until the next system reset.
+// When this value is "0", software will not be able to read back key 0 and original initialization vector 0
+#define AVPBSEA_SECURE_SEC_SEL0_0_KEYREAD_ENB0_SHIFT                    _MK_SHIFT_CONST(0)
+#define AVPBSEA_SECURE_SEC_SEL0_0_KEYREAD_ENB0_FIELD                    (_MK_MASK_CONST(0x1) << AVPBSEA_SECURE_SEC_SEL0_0_KEYREAD_ENB0_SHIFT)
+#define AVPBSEA_SECURE_SEC_SEL0_0_KEYREAD_ENB0_RANGE                    0:0
+#define AVPBSEA_SECURE_SEC_SEL0_0_KEYREAD_ENB0_WOFFSET                  0x0
+#define AVPBSEA_SECURE_SEC_SEL0_0_KEYREAD_ENB0_DEFAULT                  _MK_MASK_CONST(0x1)
+#define AVPBSEA_SECURE_SEC_SEL0_0_KEYREAD_ENB0_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define AVPBSEA_SECURE_SEC_SEL0_0_KEYREAD_ENB0_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define AVPBSEA_SECURE_SEC_SEL0_0_KEYREAD_ENB0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+// Sticky bit, When set to "0", it will not be possible to change the value of this bit until the next system reset.
+// When this value is "0", software will not be able to read back the current and updated initialization vector 0.
+#define AVPBSEA_SECURE_SEC_SEL0_0_IVREAD_ENB0_SHIFT                     _MK_SHIFT_CONST(2)
+#define AVPBSEA_SECURE_SEC_SEL0_0_IVREAD_ENB0_FIELD                     (_MK_MASK_CONST(0x1) << AVPBSEA_SECURE_SEC_SEL0_0_IVREAD_ENB0_SHIFT)
+#define AVPBSEA_SECURE_SEC_SEL0_0_IVREAD_ENB0_RANGE                     2:2
+#define AVPBSEA_SECURE_SEC_SEL0_0_IVREAD_ENB0_WOFFSET                   0x0
+#define AVPBSEA_SECURE_SEC_SEL0_0_IVREAD_ENB0_DEFAULT                   _MK_MASK_CONST(0x1)
+#define AVPBSEA_SECURE_SEC_SEL0_0_IVREAD_ENB0_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define AVPBSEA_SECURE_SEC_SEL0_0_IVREAD_ENB0_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define AVPBSEA_SECURE_SEC_SEL0_0_IVREAD_ENB0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+// Register AVPBSEA_SECURE_SEC_SEL1_0
+#define AVPBSEA_SECURE_SEC_SEL1_0                       _MK_ADDR_CONST(0x144)
+#define AVPBSEA_SECURE_SEC_SEL1_0_SECURE                        0x0
+#define AVPBSEA_SECURE_SEC_SEL1_0_WORD_COUNT                    0x1
+#define AVPBSEA_SECURE_SEC_SEL1_0_RESET_VAL                     _MK_MASK_CONST(0x1f)
+#define AVPBSEA_SECURE_SEC_SEL1_0_RESET_MASK                    _MK_MASK_CONST(0x1f)
+#define AVPBSEA_SECURE_SEC_SEL1_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
+#define AVPBSEA_SECURE_SEC_SEL1_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define AVPBSEA_SECURE_SEC_SEL1_0_READ_MASK                     _MK_MASK_CONST(0x1f)
+#define AVPBSEA_SECURE_SEC_SEL1_0_WRITE_MASK                    _MK_MASK_CONST(0x1f)
+
+// Sticky bit, When set to "0", it will not be possible to change the value of this bit until the next system reset.
+// When this value is "0", software will not be able to update key 1 and original initialization vector 1.
+#define AVPBSEA_SECURE_SEC_SEL1_0_KEYUPDATE_ENB1_SHIFT                  _MK_SHIFT_CONST(1)
+#define AVPBSEA_SECURE_SEC_SEL1_0_KEYUPDATE_ENB1_FIELD                  (_MK_MASK_CONST(0x1) << AVPBSEA_SECURE_SEC_SEL1_0_KEYUPDATE_ENB1_SHIFT)
+#define AVPBSEA_SECURE_SEC_SEL1_0_KEYUPDATE_ENB1_RANGE                  1:1
+#define AVPBSEA_SECURE_SEC_SEL1_0_KEYUPDATE_ENB1_WOFFSET                        0x0
+#define AVPBSEA_SECURE_SEC_SEL1_0_KEYUPDATE_ENB1_DEFAULT                        _MK_MASK_CONST(0x1)
+#define AVPBSEA_SECURE_SEC_SEL1_0_KEYUPDATE_ENB1_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define AVPBSEA_SECURE_SEC_SEL1_0_KEYUPDATE_ENB1_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define AVPBSEA_SECURE_SEC_SEL1_0_KEYUPDATE_ENB1_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// Sticky bit, When set to "0", it will not be possible to change the value of this bit until the next system reset.
+// When this value is "0", software will not be able to read back key 1 and original initialization vector 1
+#define AVPBSEA_SECURE_SEC_SEL1_0_KEYREAD_ENB1_SHIFT                    _MK_SHIFT_CONST(0)
+#define AVPBSEA_SECURE_SEC_SEL1_0_KEYREAD_ENB1_FIELD                    (_MK_MASK_CONST(0x1) << AVPBSEA_SECURE_SEC_SEL1_0_KEYREAD_ENB1_SHIFT)
+#define AVPBSEA_SECURE_SEC_SEL1_0_KEYREAD_ENB1_RANGE                    0:0
+#define AVPBSEA_SECURE_SEC_SEL1_0_KEYREAD_ENB1_WOFFSET                  0x0
+#define AVPBSEA_SECURE_SEC_SEL1_0_KEYREAD_ENB1_DEFAULT                  _MK_MASK_CONST(0x1)
+#define AVPBSEA_SECURE_SEC_SEL1_0_KEYREAD_ENB1_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define AVPBSEA_SECURE_SEC_SEL1_0_KEYREAD_ENB1_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define AVPBSEA_SECURE_SEC_SEL1_0_KEYREAD_ENB1_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+// Sticky bit, When set to "0", it will not be possible to change the value of this bit until the next system reset.
+// When this value is "0", software will not be able to read back the current and updated initialization vector 1.
+#define AVPBSEA_SECURE_SEC_SEL1_0_IVREAD_ENB1_SHIFT                     _MK_SHIFT_CONST(2)
+#define AVPBSEA_SECURE_SEC_SEL1_0_IVREAD_ENB1_FIELD                     (_MK_MASK_CONST(0x1) << AVPBSEA_SECURE_SEC_SEL1_0_IVREAD_ENB1_SHIFT)
+#define AVPBSEA_SECURE_SEC_SEL1_0_IVREAD_ENB1_RANGE                     2:2
+#define AVPBSEA_SECURE_SEC_SEL1_0_IVREAD_ENB1_WOFFSET                   0x0
+#define AVPBSEA_SECURE_SEC_SEL1_0_IVREAD_ENB1_DEFAULT                   _MK_MASK_CONST(0x1)
+#define AVPBSEA_SECURE_SEC_SEL1_0_IVREAD_ENB1_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define AVPBSEA_SECURE_SEC_SEL1_0_IVREAD_ENB1_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define AVPBSEA_SECURE_SEC_SEL1_0_IVREAD_ENB1_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+// Register AVPBSEA_SECURE_SEC_SEL2_0
+#define AVPBSEA_SECURE_SEC_SEL2_0                       _MK_ADDR_CONST(0x148)
+#define AVPBSEA_SECURE_SEC_SEL2_0_SECURE                        0x0
+#define AVPBSEA_SECURE_SEC_SEL2_0_WORD_COUNT                    0x1
+#define AVPBSEA_SECURE_SEC_SEL2_0_RESET_VAL                     _MK_MASK_CONST(0x1f)
+#define AVPBSEA_SECURE_SEC_SEL2_0_RESET_MASK                    _MK_MASK_CONST(0x1f)
+#define AVPBSEA_SECURE_SEC_SEL2_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
+#define AVPBSEA_SECURE_SEC_SEL2_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define AVPBSEA_SECURE_SEC_SEL2_0_READ_MASK                     _MK_MASK_CONST(0x1f)
+#define AVPBSEA_SECURE_SEC_SEL2_0_WRITE_MASK                    _MK_MASK_CONST(0x1f)
+
+// Sticky bit, When set to "0", it will not be possible to change the value of this bit until the next system reset.
+// When this value is "0", software will not be able to update key 2 and original initialization vector 2.
+#define AVPBSEA_SECURE_SEC_SEL2_0_KEYUPDATE_ENB2_SHIFT                  _MK_SHIFT_CONST(1)
+#define AVPBSEA_SECURE_SEC_SEL2_0_KEYUPDATE_ENB2_FIELD                  (_MK_MASK_CONST(0x1) << AVPBSEA_SECURE_SEC_SEL2_0_KEYUPDATE_ENB2_SHIFT)
+#define AVPBSEA_SECURE_SEC_SEL2_0_KEYUPDATE_ENB2_RANGE                  1:1
+#define AVPBSEA_SECURE_SEC_SEL2_0_KEYUPDATE_ENB2_WOFFSET                        0x0
+#define AVPBSEA_SECURE_SEC_SEL2_0_KEYUPDATE_ENB2_DEFAULT                        _MK_MASK_CONST(0x1)
+#define AVPBSEA_SECURE_SEC_SEL2_0_KEYUPDATE_ENB2_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define AVPBSEA_SECURE_SEC_SEL2_0_KEYUPDATE_ENB2_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define AVPBSEA_SECURE_SEC_SEL2_0_KEYUPDATE_ENB2_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// Sticky bit, When set to "0", it will not be possible to change the value of this bit until the next system reset.
+// When this value is "0", software will not be able to read back key 2 and original initialization vector 2
+#define AVPBSEA_SECURE_SEC_SEL2_0_KEYREAD_ENB2_SHIFT                    _MK_SHIFT_CONST(0)
+#define AVPBSEA_SECURE_SEC_SEL2_0_KEYREAD_ENB2_FIELD                    (_MK_MASK_CONST(0x1) << AVPBSEA_SECURE_SEC_SEL2_0_KEYREAD_ENB2_SHIFT)
+#define AVPBSEA_SECURE_SEC_SEL2_0_KEYREAD_ENB2_RANGE                    0:0
+#define AVPBSEA_SECURE_SEC_SEL2_0_KEYREAD_ENB2_WOFFSET                  0x0
+#define AVPBSEA_SECURE_SEC_SEL2_0_KEYREAD_ENB2_DEFAULT                  _MK_MASK_CONST(0x1)
+#define AVPBSEA_SECURE_SEC_SEL2_0_KEYREAD_ENB2_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define AVPBSEA_SECURE_SEC_SEL2_0_KEYREAD_ENB2_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define AVPBSEA_SECURE_SEC_SEL2_0_KEYREAD_ENB2_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+// Sticky bit, When set to "0", it will not be possible to change the value of this bit until the next system reset.
+// When this value is "0", software will not be able to read back the current and updated initialization vector 2.
+#define AVPBSEA_SECURE_SEC_SEL2_0_IVREAD_ENB2_SHIFT                     _MK_SHIFT_CONST(2)
+#define AVPBSEA_SECURE_SEC_SEL2_0_IVREAD_ENB2_FIELD                     (_MK_MASK_CONST(0x1) << AVPBSEA_SECURE_SEC_SEL2_0_IVREAD_ENB2_SHIFT)
+#define AVPBSEA_SECURE_SEC_SEL2_0_IVREAD_ENB2_RANGE                     2:2
+#define AVPBSEA_SECURE_SEC_SEL2_0_IVREAD_ENB2_WOFFSET                   0x0
+#define AVPBSEA_SECURE_SEC_SEL2_0_IVREAD_ENB2_DEFAULT                   _MK_MASK_CONST(0x1)
+#define AVPBSEA_SECURE_SEC_SEL2_0_IVREAD_ENB2_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define AVPBSEA_SECURE_SEC_SEL2_0_IVREAD_ENB2_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define AVPBSEA_SECURE_SEC_SEL2_0_IVREAD_ENB2_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+// Register AVPBSEA_SECURE_SEC_SEL3_0
+#define AVPBSEA_SECURE_SEC_SEL3_0                       _MK_ADDR_CONST(0x14c)
+#define AVPBSEA_SECURE_SEC_SEL3_0_SECURE                        0x0
+#define AVPBSEA_SECURE_SEC_SEL3_0_WORD_COUNT                    0x1
+#define AVPBSEA_SECURE_SEC_SEL3_0_RESET_VAL                     _MK_MASK_CONST(0x1f)
+#define AVPBSEA_SECURE_SEC_SEL3_0_RESET_MASK                    _MK_MASK_CONST(0x1f)
+#define AVPBSEA_SECURE_SEC_SEL3_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
+#define AVPBSEA_SECURE_SEC_SEL3_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define AVPBSEA_SECURE_SEC_SEL3_0_READ_MASK                     _MK_MASK_CONST(0x1f)
+#define AVPBSEA_SECURE_SEC_SEL3_0_WRITE_MASK                    _MK_MASK_CONST(0x1f)
+
+// Sticky bit, When set to "0", it will not be possible to change the value of this bit until the next system reset.
+// When this value is "0", software will not be able to update key 3 and original initialization vector 3.
+#define AVPBSEA_SECURE_SEC_SEL3_0_KEYUPDATE_ENB3_SHIFT                  _MK_SHIFT_CONST(1)
+#define AVPBSEA_SECURE_SEC_SEL3_0_KEYUPDATE_ENB3_FIELD                  (_MK_MASK_CONST(0x1) << AVPBSEA_SECURE_SEC_SEL3_0_KEYUPDATE_ENB3_SHIFT)
+#define AVPBSEA_SECURE_SEC_SEL3_0_KEYUPDATE_ENB3_RANGE                  1:1
+#define AVPBSEA_SECURE_SEC_SEL3_0_KEYUPDATE_ENB3_WOFFSET                        0x0
+#define AVPBSEA_SECURE_SEC_SEL3_0_KEYUPDATE_ENB3_DEFAULT                        _MK_MASK_CONST(0x1)
+#define AVPBSEA_SECURE_SEC_SEL3_0_KEYUPDATE_ENB3_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define AVPBSEA_SECURE_SEC_SEL3_0_KEYUPDATE_ENB3_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define AVPBSEA_SECURE_SEC_SEL3_0_KEYUPDATE_ENB3_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// Sticky bit, When set to "0", it will not be possible to change the value of this bit until the next system reset.
+// When this value is "0", software will not be able to read back key 3 and original initialization vector 3
+#define AVPBSEA_SECURE_SEC_SEL3_0_KEYREAD_ENB3_SHIFT                    _MK_SHIFT_CONST(0)
+#define AVPBSEA_SECURE_SEC_SEL3_0_KEYREAD_ENB3_FIELD                    (_MK_MASK_CONST(0x1) << AVPBSEA_SECURE_SEC_SEL3_0_KEYREAD_ENB3_SHIFT)
+#define AVPBSEA_SECURE_SEC_SEL3_0_KEYREAD_ENB3_RANGE                    0:0
+#define AVPBSEA_SECURE_SEC_SEL3_0_KEYREAD_ENB3_WOFFSET                  0x0
+#define AVPBSEA_SECURE_SEC_SEL3_0_KEYREAD_ENB3_DEFAULT                  _MK_MASK_CONST(0x1)
+#define AVPBSEA_SECURE_SEC_SEL3_0_KEYREAD_ENB3_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define AVPBSEA_SECURE_SEC_SEL3_0_KEYREAD_ENB3_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define AVPBSEA_SECURE_SEC_SEL3_0_KEYREAD_ENB3_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+// Sticky bit, When set to "0", it will not be possible to change the value of this bit until the next system reset.
+// When this value is "0", software will not be able to read back the current and updated initialization vector 3.
+#define AVPBSEA_SECURE_SEC_SEL3_0_IVREAD_ENB3_SHIFT                     _MK_SHIFT_CONST(2)
+#define AVPBSEA_SECURE_SEC_SEL3_0_IVREAD_ENB3_FIELD                     (_MK_MASK_CONST(0x1) << AVPBSEA_SECURE_SEC_SEL3_0_IVREAD_ENB3_SHIFT)
+#define AVPBSEA_SECURE_SEC_SEL3_0_IVREAD_ENB3_RANGE                     2:2
+#define AVPBSEA_SECURE_SEC_SEL3_0_IVREAD_ENB3_WOFFSET                   0x0
+#define AVPBSEA_SECURE_SEC_SEL3_0_IVREAD_ENB3_DEFAULT                   _MK_MASK_CONST(0x1)
+#define AVPBSEA_SECURE_SEC_SEL3_0_IVREAD_ENB3_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define AVPBSEA_SECURE_SEC_SEL3_0_IVREAD_ENB3_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define AVPBSEA_SECURE_SEC_SEL3_0_IVREAD_ENB3_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+// Register AVPBSEA_SECURE_SEC_SEL4_0
+#define AVPBSEA_SECURE_SEC_SEL4_0                       _MK_ADDR_CONST(0x150)
+#define AVPBSEA_SECURE_SEC_SEL4_0_SECURE                        0x0
+#define AVPBSEA_SECURE_SEC_SEL4_0_WORD_COUNT                    0x1
+#define AVPBSEA_SECURE_SEC_SEL4_0_RESET_VAL                     _MK_MASK_CONST(0x1f)
+#define AVPBSEA_SECURE_SEC_SEL4_0_RESET_MASK                    _MK_MASK_CONST(0x1f)
+#define AVPBSEA_SECURE_SEC_SEL4_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
+#define AVPBSEA_SECURE_SEC_SEL4_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define AVPBSEA_SECURE_SEC_SEL4_0_READ_MASK                     _MK_MASK_CONST(0x1f)
+#define AVPBSEA_SECURE_SEC_SEL4_0_WRITE_MASK                    _MK_MASK_CONST(0x1f)
+
+// Sticky bit, When set to "0", it will not be possible to change the value of this bit until the next system reset.
+// When this value is "0", software will not be able to update key 4 and original initialization vector 4.
+#define AVPBSEA_SECURE_SEC_SEL4_0_KEYUPDATE_ENB4_SHIFT                  _MK_SHIFT_CONST(1)
+#define AVPBSEA_SECURE_SEC_SEL4_0_KEYUPDATE_ENB4_FIELD                  (_MK_MASK_CONST(0x1) << AVPBSEA_SECURE_SEC_SEL4_0_KEYUPDATE_ENB4_SHIFT)
+#define AVPBSEA_SECURE_SEC_SEL4_0_KEYUPDATE_ENB4_RANGE                  1:1
+#define AVPBSEA_SECURE_SEC_SEL4_0_KEYUPDATE_ENB4_WOFFSET                        0x0
+#define AVPBSEA_SECURE_SEC_SEL4_0_KEYUPDATE_ENB4_DEFAULT                        _MK_MASK_CONST(0x1)
+#define AVPBSEA_SECURE_SEC_SEL4_0_KEYUPDATE_ENB4_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define AVPBSEA_SECURE_SEC_SEL4_0_KEYUPDATE_ENB4_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define AVPBSEA_SECURE_SEC_SEL4_0_KEYUPDATE_ENB4_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// Sticky bit, When set to "0", it will not be possible to change the value of this bit until the next system reset.
+// When this value is "0", software will not be able to read back key 4 and original initialization vector 4
+#define AVPBSEA_SECURE_SEC_SEL4_0_KEYREAD_ENB4_SHIFT                    _MK_SHIFT_CONST(0)
+#define AVPBSEA_SECURE_SEC_SEL4_0_KEYREAD_ENB4_FIELD                    (_MK_MASK_CONST(0x1) << AVPBSEA_SECURE_SEC_SEL4_0_KEYREAD_ENB4_SHIFT)
+#define AVPBSEA_SECURE_SEC_SEL4_0_KEYREAD_ENB4_RANGE                    0:0
+#define AVPBSEA_SECURE_SEC_SEL4_0_KEYREAD_ENB4_WOFFSET                  0x0
+#define AVPBSEA_SECURE_SEC_SEL4_0_KEYREAD_ENB4_DEFAULT                  _MK_MASK_CONST(0x1)
+#define AVPBSEA_SECURE_SEC_SEL4_0_KEYREAD_ENB4_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define AVPBSEA_SECURE_SEC_SEL4_0_KEYREAD_ENB4_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define AVPBSEA_SECURE_SEC_SEL4_0_KEYREAD_ENB4_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+// Sticky bit, When set to "0", it will not be possible to change the value of this bit until the next system reset.
+// When this value is "0", software will not be able to read back the current and updated initialization vector 4.
+#define AVPBSEA_SECURE_SEC_SEL4_0_IVREAD_ENB4_SHIFT                     _MK_SHIFT_CONST(2)
+#define AVPBSEA_SECURE_SEC_SEL4_0_IVREAD_ENB4_FIELD                     (_MK_MASK_CONST(0x1) << AVPBSEA_SECURE_SEC_SEL4_0_IVREAD_ENB4_SHIFT)
+#define AVPBSEA_SECURE_SEC_SEL4_0_IVREAD_ENB4_RANGE                     2:2
+#define AVPBSEA_SECURE_SEC_SEL4_0_IVREAD_ENB4_WOFFSET                   0x0
+#define AVPBSEA_SECURE_SEC_SEL4_0_IVREAD_ENB4_DEFAULT                   _MK_MASK_CONST(0x1)
+#define AVPBSEA_SECURE_SEC_SEL4_0_IVREAD_ENB4_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define AVPBSEA_SECURE_SEC_SEL4_0_IVREAD_ENB4_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define AVPBSEA_SECURE_SEC_SEL4_0_IVREAD_ENB4_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+// Register AVPBSEA_SECURE_SEC_SEL5_0
+#define AVPBSEA_SECURE_SEC_SEL5_0                       _MK_ADDR_CONST(0x154)
+#define AVPBSEA_SECURE_SEC_SEL5_0_SECURE                        0x0
+#define AVPBSEA_SECURE_SEC_SEL5_0_WORD_COUNT                    0x1
+#define AVPBSEA_SECURE_SEC_SEL5_0_RESET_VAL                     _MK_MASK_CONST(0x1f)
+#define AVPBSEA_SECURE_SEC_SEL5_0_RESET_MASK                    _MK_MASK_CONST(0x1f)
+#define AVPBSEA_SECURE_SEC_SEL5_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
+#define AVPBSEA_SECURE_SEC_SEL5_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define AVPBSEA_SECURE_SEC_SEL5_0_READ_MASK                     _MK_MASK_CONST(0x1f)
+#define AVPBSEA_SECURE_SEC_SEL5_0_WRITE_MASK                    _MK_MASK_CONST(0x1f)
+
+// Sticky bit, When set to "0", it will not be possible to change the value of this bit until the next system reset.
+// When this value is "0", software will not be able to update key 5 and original initialization vector 5.
+#define AVPBSEA_SECURE_SEC_SEL5_0_KEYUPDATE_ENB5_SHIFT                  _MK_SHIFT_CONST(1)
+#define AVPBSEA_SECURE_SEC_SEL5_0_KEYUPDATE_ENB5_FIELD                  (_MK_MASK_CONST(0x1) << AVPBSEA_SECURE_SEC_SEL5_0_KEYUPDATE_ENB5_SHIFT)
+#define AVPBSEA_SECURE_SEC_SEL5_0_KEYUPDATE_ENB5_RANGE                  1:1
+#define AVPBSEA_SECURE_SEC_SEL5_0_KEYUPDATE_ENB5_WOFFSET                        0x0
+#define AVPBSEA_SECURE_SEC_SEL5_0_KEYUPDATE_ENB5_DEFAULT                        _MK_MASK_CONST(0x1)
+#define AVPBSEA_SECURE_SEC_SEL5_0_KEYUPDATE_ENB5_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define AVPBSEA_SECURE_SEC_SEL5_0_KEYUPDATE_ENB5_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define AVPBSEA_SECURE_SEC_SEL5_0_KEYUPDATE_ENB5_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// Sticky bit, When set to "0", it will not be possible to change the value of this bit until the next system reset.
+// When this value is "0", software will not be able to read back key 5 and original initialization vector 5
+#define AVPBSEA_SECURE_SEC_SEL5_0_KEYREAD_ENB5_SHIFT                    _MK_SHIFT_CONST(0)
+#define AVPBSEA_SECURE_SEC_SEL5_0_KEYREAD_ENB5_FIELD                    (_MK_MASK_CONST(0x1) << AVPBSEA_SECURE_SEC_SEL5_0_KEYREAD_ENB5_SHIFT)
+#define AVPBSEA_SECURE_SEC_SEL5_0_KEYREAD_ENB5_RANGE                    0:0
+#define AVPBSEA_SECURE_SEC_SEL5_0_KEYREAD_ENB5_WOFFSET                  0x0
+#define AVPBSEA_SECURE_SEC_SEL5_0_KEYREAD_ENB5_DEFAULT                  _MK_MASK_CONST(0x1)
+#define AVPBSEA_SECURE_SEC_SEL5_0_KEYREAD_ENB5_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define AVPBSEA_SECURE_SEC_SEL5_0_KEYREAD_ENB5_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define AVPBSEA_SECURE_SEC_SEL5_0_KEYREAD_ENB5_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+// Sticky bit, When set to "0", it will not be possible to change the value of this bit until the next system reset.
+// When this value is "0", software will not be able to read back the current and updated initialization vector 5.
+#define AVPBSEA_SECURE_SEC_SEL5_0_IVREAD_ENB5_SHIFT                     _MK_SHIFT_CONST(2)
+#define AVPBSEA_SECURE_SEC_SEL5_0_IVREAD_ENB5_FIELD                     (_MK_MASK_CONST(0x1) << AVPBSEA_SECURE_SEC_SEL5_0_IVREAD_ENB5_SHIFT)
+#define AVPBSEA_SECURE_SEC_SEL5_0_IVREAD_ENB5_RANGE                     2:2
+#define AVPBSEA_SECURE_SEC_SEL5_0_IVREAD_ENB5_WOFFSET                   0x0
+#define AVPBSEA_SECURE_SEC_SEL5_0_IVREAD_ENB5_DEFAULT                   _MK_MASK_CONST(0x1)
+#define AVPBSEA_SECURE_SEC_SEL5_0_IVREAD_ENB5_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define AVPBSEA_SECURE_SEC_SEL5_0_IVREAD_ENB5_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define AVPBSEA_SECURE_SEC_SEL5_0_IVREAD_ENB5_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+// Register AVPBSEA_SECURE_SEC_SEL6_0
+#define AVPBSEA_SECURE_SEC_SEL6_0                       _MK_ADDR_CONST(0x158)
+#define AVPBSEA_SECURE_SEC_SEL6_0_SECURE                        0x0
+#define AVPBSEA_SECURE_SEC_SEL6_0_WORD_COUNT                    0x1
+#define AVPBSEA_SECURE_SEC_SEL6_0_RESET_VAL                     _MK_MASK_CONST(0x1f)
+#define AVPBSEA_SECURE_SEC_SEL6_0_RESET_MASK                    _MK_MASK_CONST(0x1f)
+#define AVPBSEA_SECURE_SEC_SEL6_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
+#define AVPBSEA_SECURE_SEC_SEL6_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define AVPBSEA_SECURE_SEC_SEL6_0_READ_MASK                     _MK_MASK_CONST(0x1f)
+#define AVPBSEA_SECURE_SEC_SEL6_0_WRITE_MASK                    _MK_MASK_CONST(0x1f)
+
+// Sticky bit, When set to "0", it will not be possible to change the value of this bit until the next system reset.
+// When this value is "0", software will not be able to update key 6 and original initialization vector 6.
+#define AVPBSEA_SECURE_SEC_SEL6_0_KEYUPDATE_ENB6_SHIFT                  _MK_SHIFT_CONST(1)
+#define AVPBSEA_SECURE_SEC_SEL6_0_KEYUPDATE_ENB6_FIELD                  (_MK_MASK_CONST(0x1) << AVPBSEA_SECURE_SEC_SEL6_0_KEYUPDATE_ENB6_SHIFT)
+#define AVPBSEA_SECURE_SEC_SEL6_0_KEYUPDATE_ENB6_RANGE                  1:1
+#define AVPBSEA_SECURE_SEC_SEL6_0_KEYUPDATE_ENB6_WOFFSET                        0x0
+#define AVPBSEA_SECURE_SEC_SEL6_0_KEYUPDATE_ENB6_DEFAULT                        _MK_MASK_CONST(0x1)
+#define AVPBSEA_SECURE_SEC_SEL6_0_KEYUPDATE_ENB6_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define AVPBSEA_SECURE_SEC_SEL6_0_KEYUPDATE_ENB6_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define AVPBSEA_SECURE_SEC_SEL6_0_KEYUPDATE_ENB6_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// Sticky bit, When set to "0", it will not be possible to change the value of this bit until the next system reset.
+// When this value is "0", software will not be able to read back key 6 and original initialization vector 6
+#define AVPBSEA_SECURE_SEC_SEL6_0_KEYREAD_ENB6_SHIFT                    _MK_SHIFT_CONST(0)
+#define AVPBSEA_SECURE_SEC_SEL6_0_KEYREAD_ENB6_FIELD                    (_MK_MASK_CONST(0x1) << AVPBSEA_SECURE_SEC_SEL6_0_KEYREAD_ENB6_SHIFT)
+#define AVPBSEA_SECURE_SEC_SEL6_0_KEYREAD_ENB6_RANGE                    0:0
+#define AVPBSEA_SECURE_SEC_SEL6_0_KEYREAD_ENB6_WOFFSET                  0x0
+#define AVPBSEA_SECURE_SEC_SEL6_0_KEYREAD_ENB6_DEFAULT                  _MK_MASK_CONST(0x1)
+#define AVPBSEA_SECURE_SEC_SEL6_0_KEYREAD_ENB6_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define AVPBSEA_SECURE_SEC_SEL6_0_KEYREAD_ENB6_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define AVPBSEA_SECURE_SEC_SEL6_0_KEYREAD_ENB6_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+// Sticky bit, When set to "0", it will not be possible to change the value of this bit until the next system reset.
+// When this value is "0", software will not be able to read back the current and updated initialization vector 6.
+#define AVPBSEA_SECURE_SEC_SEL6_0_IVREAD_ENB6_SHIFT                     _MK_SHIFT_CONST(2)
+#define AVPBSEA_SECURE_SEC_SEL6_0_IVREAD_ENB6_FIELD                     (_MK_MASK_CONST(0x1) << AVPBSEA_SECURE_SEC_SEL6_0_IVREAD_ENB6_SHIFT)
+#define AVPBSEA_SECURE_SEC_SEL6_0_IVREAD_ENB6_RANGE                     2:2
+#define AVPBSEA_SECURE_SEC_SEL6_0_IVREAD_ENB6_WOFFSET                   0x0
+#define AVPBSEA_SECURE_SEC_SEL6_0_IVREAD_ENB6_DEFAULT                   _MK_MASK_CONST(0x1)
+#define AVPBSEA_SECURE_SEC_SEL6_0_IVREAD_ENB6_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define AVPBSEA_SECURE_SEC_SEL6_0_IVREAD_ENB6_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define AVPBSEA_SECURE_SEC_SEL6_0_IVREAD_ENB6_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+// Register AVPBSEA_SECURE_SEC_SEL7_0
+#define AVPBSEA_SECURE_SEC_SEL7_0                       _MK_ADDR_CONST(0x15c)
+#define AVPBSEA_SECURE_SEC_SEL7_0_SECURE                        0x0
+#define AVPBSEA_SECURE_SEC_SEL7_0_WORD_COUNT                    0x1
+#define AVPBSEA_SECURE_SEC_SEL7_0_RESET_VAL                     _MK_MASK_CONST(0x1f)
+#define AVPBSEA_SECURE_SEC_SEL7_0_RESET_MASK                    _MK_MASK_CONST(0x1f)
+#define AVPBSEA_SECURE_SEC_SEL7_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
+#define AVPBSEA_SECURE_SEC_SEL7_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define AVPBSEA_SECURE_SEC_SEL7_0_READ_MASK                     _MK_MASK_CONST(0x1f)
+#define AVPBSEA_SECURE_SEC_SEL7_0_WRITE_MASK                    _MK_MASK_CONST(0x1f)
+
+// Sticky bit, When set to "0", it will not be possible to change the value of this bit until the next system reset.
+// When this value is "0", software will not be able to update key 7 and original initialization vector 7.
+#define AVPBSEA_SECURE_SEC_SEL7_0_KEYUPDATE_ENB7_SHIFT                  _MK_SHIFT_CONST(1)
+#define AVPBSEA_SECURE_SEC_SEL7_0_KEYUPDATE_ENB7_FIELD                  (_MK_MASK_CONST(0x1) << AVPBSEA_SECURE_SEC_SEL7_0_KEYUPDATE_ENB7_SHIFT)
+#define AVPBSEA_SECURE_SEC_SEL7_0_KEYUPDATE_ENB7_RANGE                  1:1
+#define AVPBSEA_SECURE_SEC_SEL7_0_KEYUPDATE_ENB7_WOFFSET                        0x0
+#define AVPBSEA_SECURE_SEC_SEL7_0_KEYUPDATE_ENB7_DEFAULT                        _MK_MASK_CONST(0x1)
+#define AVPBSEA_SECURE_SEC_SEL7_0_KEYUPDATE_ENB7_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define AVPBSEA_SECURE_SEC_SEL7_0_KEYUPDATE_ENB7_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define AVPBSEA_SECURE_SEC_SEL7_0_KEYUPDATE_ENB7_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// Sticky bit, When set to "0", it will not be possible to change the value of this bit until the next system reset.
+// When this value is "0", software will not be able to read back key 7 and original initialization vector 7
+#define AVPBSEA_SECURE_SEC_SEL7_0_KEYREAD_ENB7_SHIFT                    _MK_SHIFT_CONST(0)
+#define AVPBSEA_SECURE_SEC_SEL7_0_KEYREAD_ENB7_FIELD                    (_MK_MASK_CONST(0x1) << AVPBSEA_SECURE_SEC_SEL7_0_KEYREAD_ENB7_SHIFT)
+#define AVPBSEA_SECURE_SEC_SEL7_0_KEYREAD_ENB7_RANGE                    0:0
+#define AVPBSEA_SECURE_SEC_SEL7_0_KEYREAD_ENB7_WOFFSET                  0x0
+#define AVPBSEA_SECURE_SEC_SEL7_0_KEYREAD_ENB7_DEFAULT                  _MK_MASK_CONST(0x1)
+#define AVPBSEA_SECURE_SEC_SEL7_0_KEYREAD_ENB7_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define AVPBSEA_SECURE_SEC_SEL7_0_KEYREAD_ENB7_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define AVPBSEA_SECURE_SEC_SEL7_0_KEYREAD_ENB7_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+// Sticky bit, When set to "0", it will not be possible to change the value of this bit until the next system reset.
+// When this value is "0", software will not be able to read back the current and updated initialization vector 7.
+#define AVPBSEA_SECURE_SEC_SEL7_0_IVREAD_ENB7_SHIFT                     _MK_SHIFT_CONST(2)
+#define AVPBSEA_SECURE_SEC_SEL7_0_IVREAD_ENB7_FIELD                     (_MK_MASK_CONST(0x1) << AVPBSEA_SECURE_SEC_SEL7_0_IVREAD_ENB7_SHIFT)
+#define AVPBSEA_SECURE_SEC_SEL7_0_IVREAD_ENB7_RANGE                     2:2
+#define AVPBSEA_SECURE_SEC_SEL7_0_IVREAD_ENB7_WOFFSET                   0x0
+#define AVPBSEA_SECURE_SEC_SEL7_0_IVREAD_ENB7_DEFAULT                   _MK_MASK_CONST(0x1)
+#define AVPBSEA_SECURE_SEC_SEL7_0_IVREAD_ENB7_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define AVPBSEA_SECURE_SEC_SEL7_0_IVREAD_ENB7_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define AVPBSEA_SECURE_SEC_SEL7_0_IVREAD_ENB7_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#endif // ifndef ___ARAVP_BSEA_AES_H_INC_
+
diff --git a/arch/arm/mach-tegra/include/ap20/arvde_bsev_aes.h b/arch/arm/mach-tegra/include/ap20/arvde_bsev_aes.h
new file mode 100644
index 000000000000..a7e33b51e6b0
--- /dev/null
+++ b/arch/arm/mach-tegra/include/ap20/arvde_bsev_aes.h
@@ -0,0 +1,813 @@
+//
+// DO NOT EDIT - generated by simspec!
+//
+
+#ifndef ___ARVDE_BSEV_AES_H_INC_
+#define ___ARVDE_BSEV_AES_H_INC_
+
+/*
+ * Copyright (c) 2009 NVIDIA Corporation.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of the NVIDIA Corporation nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+// Register ARVDE_BSEV_ICMDQUE_WR_0
+#define ARVDE_BSEV_ICMDQUE_WR_0                 _MK_ADDR_CONST(0x1000)
+#define ARVDE_BSEV_ICMDQUE_WR_0_SECURE                  0x0
+#define ARVDE_BSEV_ICMDQUE_WR_0_WORD_COUNT                      0x1
+#define ARVDE_BSEV_ICMDQUE_WR_0_RESET_VAL                       _MK_MASK_CONST(0x0)
+#define ARVDE_BSEV_ICMDQUE_WR_0_RESET_MASK                      _MK_MASK_CONST(0x0)
+#define ARVDE_BSEV_ICMDQUE_WR_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define ARVDE_BSEV_ICMDQUE_WR_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define ARVDE_BSEV_ICMDQUE_WR_0_READ_MASK                       _MK_MASK_CONST(0xffffffff)
+#define ARVDE_BSEV_ICMDQUE_WR_0_WRITE_MASK                      _MK_MASK_CONST(0xffffffff)
+#define ARVDE_BSEV_ICMDQUE_WR_0_ICMDQUE_WDATA_SHIFT                     _MK_SHIFT_CONST(0)
+#define ARVDE_BSEV_ICMDQUE_WR_0_ICMDQUE_WDATA_FIELD                     (_MK_MASK_CONST(0xffffffff) << ARVDE_BSEV_ICMDQUE_WR_0_ICMDQUE_WDATA_SHIFT)
+#define ARVDE_BSEV_ICMDQUE_WR_0_ICMDQUE_WDATA_RANGE                     31:0
+#define ARVDE_BSEV_ICMDQUE_WR_0_ICMDQUE_WDATA_WOFFSET                   0x0
+#define ARVDE_BSEV_ICMDQUE_WR_0_ICMDQUE_WDATA_DEFAULT                   _MK_MASK_CONST(0x0)
+#define ARVDE_BSEV_ICMDQUE_WR_0_ICMDQUE_WDATA_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define ARVDE_BSEV_ICMDQUE_WR_0_ICMDQUE_WDATA_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define ARVDE_BSEV_ICMDQUE_WR_0_ICMDQUE_WDATA_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+// Register ARVDE_BSEV_CMDQUE_CONTROL_0
+#define ARVDE_BSEV_CMDQUE_CONTROL_0                     _MK_ADDR_CONST(0x1008)
+#define ARVDE_BSEV_CMDQUE_CONTROL_0_SECURE                      0x0
+#define ARVDE_BSEV_CMDQUE_CONTROL_0_WORD_COUNT                  0x1
+#define ARVDE_BSEV_CMDQUE_CONTROL_0_RESET_VAL                   _MK_MASK_CONST(0x703)
+#define ARVDE_BSEV_CMDQUE_CONTROL_0_RESET_MASK                  _MK_MASK_CONST(0xf3f)
+#define ARVDE_BSEV_CMDQUE_CONTROL_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define ARVDE_BSEV_CMDQUE_CONTROL_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define ARVDE_BSEV_CMDQUE_CONTROL_0_READ_MASK                   _MK_MASK_CONST(0xf3f)
+#define ARVDE_BSEV_CMDQUE_CONTROL_0_WRITE_MASK                  _MK_MASK_CONST(0xf3f)
+
+// Destination Stream interface select
+// 0: through CIF (SDRAM only), 1: through AHB (SDRAM/IRAM)
+#define ARVDE_BSEV_CMDQUE_CONTROL_0_DST_STM_SEL_SHIFT                   _MK_SHIFT_CONST(5)
+#define ARVDE_BSEV_CMDQUE_CONTROL_0_DST_STM_SEL_FIELD                   (_MK_MASK_CONST(0x1) << ARVDE_BSEV_CMDQUE_CONTROL_0_DST_STM_SEL_SHIFT)
+#define ARVDE_BSEV_CMDQUE_CONTROL_0_DST_STM_SEL_RANGE                   5:5
+#define ARVDE_BSEV_CMDQUE_CONTROL_0_DST_STM_SEL_WOFFSET                 0x0
+#define ARVDE_BSEV_CMDQUE_CONTROL_0_DST_STM_SEL_DEFAULT                 _MK_MASK_CONST(0x0)
+#define ARVDE_BSEV_CMDQUE_CONTROL_0_DST_STM_SEL_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define ARVDE_BSEV_CMDQUE_CONTROL_0_DST_STM_SEL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define ARVDE_BSEV_CMDQUE_CONTROL_0_DST_STM_SEL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+// Source Stream interface select
+// 0: through CIF (SDRAM only), 1: through AHB (SDRAM/IRAM)
+#define ARVDE_BSEV_CMDQUE_CONTROL_0_SRC_STM_SEL_SHIFT                   _MK_SHIFT_CONST(4)
+#define ARVDE_BSEV_CMDQUE_CONTROL_0_SRC_STM_SEL_FIELD                   (_MK_MASK_CONST(0x1) << ARVDE_BSEV_CMDQUE_CONTROL_0_SRC_STM_SEL_SHIFT)
+#define ARVDE_BSEV_CMDQUE_CONTROL_0_SRC_STM_SEL_RANGE                   4:4
+#define ARVDE_BSEV_CMDQUE_CONTROL_0_SRC_STM_SEL_WOFFSET                 0x0
+#define ARVDE_BSEV_CMDQUE_CONTROL_0_SRC_STM_SEL_DEFAULT                 _MK_MASK_CONST(0x0)
+#define ARVDE_BSEV_CMDQUE_CONTROL_0_SRC_STM_SEL_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define ARVDE_BSEV_CMDQUE_CONTROL_0_SRC_STM_SEL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define ARVDE_BSEV_CMDQUE_CONTROL_0_SRC_STM_SEL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+// Register ARVDE_BSEV_INTR_STATUS_0
+#define ARVDE_BSEV_INTR_STATUS_0                        _MK_ADDR_CONST(0x1018)
+#define ARVDE_BSEV_INTR_STATUS_0_SECURE                         0x0
+#define ARVDE_BSEV_INTR_STATUS_0_WORD_COUNT                     0x1
+#define ARVDE_BSEV_INTR_STATUS_0_RESET_VAL                      _MK_MASK_CONST(0x158)
+#define ARVDE_BSEV_INTR_STATUS_0_RESET_MASK                     _MK_MASK_CONST(0xffffffff)
+#define ARVDE_BSEV_INTR_STATUS_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
+#define ARVDE_BSEV_INTR_STATUS_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define ARVDE_BSEV_INTR_STATUS_0_READ_MASK                      _MK_MASK_CONST(0xffffffff)
+#define ARVDE_BSEV_INTR_STATUS_0_WRITE_MASK                     _MK_MASK_CONST(0x7ff802)
+
+// DMA engine is still busy (asserted by DMASetup and de-asserted by DMAFinish) (RO)
+#define ARVDE_BSEV_INTR_STATUS_0_DMA_BUSY_SHIFT                 _MK_SHIFT_CONST(9)
+#define ARVDE_BSEV_INTR_STATUS_0_DMA_BUSY_FIELD                 (_MK_MASK_CONST(0x1) << ARVDE_BSEV_INTR_STATUS_0_DMA_BUSY_SHIFT)
+#define ARVDE_BSEV_INTR_STATUS_0_DMA_BUSY_RANGE                 9:9
+#define ARVDE_BSEV_INTR_STATUS_0_DMA_BUSY_WOFFSET                       0x0
+#define ARVDE_BSEV_INTR_STATUS_0_DMA_BUSY_DEFAULT                       _MK_MASK_CONST(0x0)
+#define ARVDE_BSEV_INTR_STATUS_0_DMA_BUSY_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define ARVDE_BSEV_INTR_STATUS_0_DMA_BUSY_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define ARVDE_BSEV_INTR_STATUS_0_DMA_BUSY_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// Interactive command queue is empty (RO)
+#define ARVDE_BSEV_INTR_STATUS_0_ICQ_EMPTY_SHIFT                        _MK_SHIFT_CONST(3)
+#define ARVDE_BSEV_INTR_STATUS_0_ICQ_EMPTY_FIELD                        (_MK_MASK_CONST(0x1) << ARVDE_BSEV_INTR_STATUS_0_ICQ_EMPTY_SHIFT)
+#define ARVDE_BSEV_INTR_STATUS_0_ICQ_EMPTY_RANGE                        3:3
+#define ARVDE_BSEV_INTR_STATUS_0_ICQ_EMPTY_WOFFSET                      0x0
+#define ARVDE_BSEV_INTR_STATUS_0_ICQ_EMPTY_DEFAULT                      _MK_MASK_CONST(0x1)
+#define ARVDE_BSEV_INTR_STATUS_0_ICQ_EMPTY_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define ARVDE_BSEV_INTR_STATUS_0_ICQ_EMPTY_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define ARVDE_BSEV_INTR_STATUS_0_ICQ_EMPTY_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+// AES busy (RO)
+#define ARVDE_BSEV_INTR_STATUS_0_ENGINE_BUSY_SHIFT                      _MK_SHIFT_CONST(0)
+#define ARVDE_BSEV_INTR_STATUS_0_ENGINE_BUSY_FIELD                      (_MK_MASK_CONST(0x1) << ARVDE_BSEV_INTR_STATUS_0_ENGINE_BUSY_SHIFT)
+#define ARVDE_BSEV_INTR_STATUS_0_ENGINE_BUSY_RANGE                      0:0
+#define ARVDE_BSEV_INTR_STATUS_0_ENGINE_BUSY_WOFFSET                    0x0
+#define ARVDE_BSEV_INTR_STATUS_0_ENGINE_BUSY_DEFAULT                    _MK_MASK_CONST(0x0)
+#define ARVDE_BSEV_INTR_STATUS_0_ENGINE_BUSY_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define ARVDE_BSEV_INTR_STATUS_0_ENGINE_BUSY_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define ARVDE_BSEV_INTR_STATUS_0_ENGINE_BUSY_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// Register ARVDE_BSEV_BSE_CONFIG_0
+#define ARVDE_BSEV_BSE_CONFIG_0                 _MK_ADDR_CONST(0x1044)
+#define ARVDE_BSEV_BSE_CONFIG_0_SECURE                  0x0
+#define ARVDE_BSEV_BSE_CONFIG_0_WORD_COUNT                      0x1
+#define ARVDE_BSEV_BSE_CONFIG_0_RESET_VAL                       _MK_MASK_CONST(0xffff0d28)
+#define ARVDE_BSEV_BSE_CONFIG_0_RESET_MASK                      _MK_MASK_CONST(0xffffffff)
+#define ARVDE_BSEV_BSE_CONFIG_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define ARVDE_BSEV_BSE_CONFIG_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define ARVDE_BSEV_BSE_CONFIG_0_READ_MASK                       _MK_MASK_CONST(0xffffffff)
+#define ARVDE_BSEV_BSE_CONFIG_0_WRITE_MASK                      _MK_MASK_CONST(0xffffffff)
+
+// Must be set to 1.
+#define ARVDE_BSEV_BSE_CONFIG_0_ENDIAN_ENB_SHIFT                        _MK_SHIFT_CONST(10)
+#define ARVDE_BSEV_BSE_CONFIG_0_ENDIAN_ENB_FIELD                        (_MK_MASK_CONST(0x1) << ARVDE_BSEV_BSE_CONFIG_0_ENDIAN_ENB_SHIFT)
+#define ARVDE_BSEV_BSE_CONFIG_0_ENDIAN_ENB_RANGE                        10:10
+#define ARVDE_BSEV_BSE_CONFIG_0_ENDIAN_ENB_WOFFSET                      0x0
+#define ARVDE_BSEV_BSE_CONFIG_0_ENDIAN_ENB_DEFAULT                      _MK_MASK_CONST(0x1)
+#define ARVDE_BSEV_BSE_CONFIG_0_ENDIAN_ENB_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define ARVDE_BSEV_BSE_CONFIG_0_ENDIAN_ENB_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define ARVDE_BSEV_BSE_CONFIG_0_ENDIAN_ENB_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+// 00000: CRYPTO mode
+#define ARVDE_BSEV_BSE_CONFIG_0_BSE_MODE_SEL_SHIFT                      _MK_SHIFT_CONST(0)
+#define ARVDE_BSEV_BSE_CONFIG_0_BSE_MODE_SEL_FIELD                      (_MK_MASK_CONST(0x1f) << ARVDE_BSEV_BSE_CONFIG_0_BSE_MODE_SEL_SHIFT)
+#define ARVDE_BSEV_BSE_CONFIG_0_BSE_MODE_SEL_RANGE                      4:0
+#define ARVDE_BSEV_BSE_CONFIG_0_BSE_MODE_SEL_WOFFSET                    0x0
+#define ARVDE_BSEV_BSE_CONFIG_0_BSE_MODE_SEL_DEFAULT                    _MK_MASK_CONST(0x8)
+#define ARVDE_BSEV_BSE_CONFIG_0_BSE_MODE_SEL_DEFAULT_MASK                       _MK_MASK_CONST(0x1f)
+#define ARVDE_BSEV_BSE_CONFIG_0_BSE_MODE_SEL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define ARVDE_BSEV_BSE_CONFIG_0_BSE_MODE_SEL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// Register ARVDE_BSEV_SECURE_DEST_ADDR_0
+#define ARVDE_BSEV_SECURE_DEST_ADDR_0                   _MK_ADDR_CONST(0x1100)
+#define ARVDE_BSEV_SECURE_DEST_ADDR_0_SECURE                    0x0
+#define ARVDE_BSEV_SECURE_DEST_ADDR_0_WORD_COUNT                        0x1
+#define ARVDE_BSEV_SECURE_DEST_ADDR_0_RESET_VAL                         _MK_MASK_CONST(0x0)
+#define ARVDE_BSEV_SECURE_DEST_ADDR_0_RESET_MASK                        _MK_MASK_CONST(0xffffffff)
+#define ARVDE_BSEV_SECURE_DEST_ADDR_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define ARVDE_BSEV_SECURE_DEST_ADDR_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define ARVDE_BSEV_SECURE_DEST_ADDR_0_READ_MASK                         _MK_MASK_CONST(0xffffffff)
+#define ARVDE_BSEV_SECURE_DEST_ADDR_0_WRITE_MASK                        _MK_MASK_CONST(0xffffffff)
+
+// SECURE engine: write back destination write address
+#define ARVDE_BSEV_SECURE_DEST_ADDR_0_SECURE_DEST_ADDR_SHIFT                    _MK_SHIFT_CONST(0)
+#define ARVDE_BSEV_SECURE_DEST_ADDR_0_SECURE_DEST_ADDR_FIELD                    (_MK_MASK_CONST(0xffffffff) << ARVDE_BSEV_SECURE_DEST_ADDR_0_SECURE_DEST_ADDR_SHIFT)
+#define ARVDE_BSEV_SECURE_DEST_ADDR_0_SECURE_DEST_ADDR_RANGE                    31:0
+#define ARVDE_BSEV_SECURE_DEST_ADDR_0_SECURE_DEST_ADDR_WOFFSET                  0x0
+#define ARVDE_BSEV_SECURE_DEST_ADDR_0_SECURE_DEST_ADDR_DEFAULT                  _MK_MASK_CONST(0x0)
+#define ARVDE_BSEV_SECURE_DEST_ADDR_0_SECURE_DEST_ADDR_DEFAULT_MASK                     _MK_MASK_CONST(0xffffffff)
+#define ARVDE_BSEV_SECURE_DEST_ADDR_0_SECURE_DEST_ADDR_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define ARVDE_BSEV_SECURE_DEST_ADDR_0_SECURE_DEST_ADDR_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+// Register ARVDE_BSEV_SECURE_INPUT_SELECT_0
+#define ARVDE_BSEV_SECURE_INPUT_SELECT_0                        _MK_ADDR_CONST(0x1104)
+#define ARVDE_BSEV_SECURE_INPUT_SELECT_0_SECURE                         0x0
+#define ARVDE_BSEV_SECURE_INPUT_SELECT_0_WORD_COUNT                     0x1
+#define ARVDE_BSEV_SECURE_INPUT_SELECT_0_RESET_VAL                      _MK_MASK_CONST(0x10800000)
+#define ARVDE_BSEV_SECURE_INPUT_SELECT_0_RESET_MASK                     _MK_MASK_CONST(0xffff0fff)
+#define ARVDE_BSEV_SECURE_INPUT_SELECT_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
+#define ARVDE_BSEV_SECURE_INPUT_SELECT_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define ARVDE_BSEV_SECURE_INPUT_SELECT_0_READ_MASK                      _MK_MASK_CONST(0xffff0fff)
+#define ARVDE_BSEV_SECURE_INPUT_SELECT_0_WRITE_MASK                     _MK_MASK_CONST(0xffff0fff)
+
+// SECURE engine: random number generator enable
+#define ARVDE_BSEV_SECURE_INPUT_SELECT_0_SECURE_RNG_ENB_SHIFT                   _MK_SHIFT_CONST(11)
+#define ARVDE_BSEV_SECURE_INPUT_SELECT_0_SECURE_RNG_ENB_FIELD                   (_MK_MASK_CONST(0x1) << ARVDE_BSEV_SECURE_INPUT_SELECT_0_SECURE_RNG_ENB_SHIFT)
+#define ARVDE_BSEV_SECURE_INPUT_SELECT_0_SECURE_RNG_ENB_RANGE                   11:11
+#define ARVDE_BSEV_SECURE_INPUT_SELECT_0_SECURE_RNG_ENB_WOFFSET                 0x0
+#define ARVDE_BSEV_SECURE_INPUT_SELECT_0_SECURE_RNG_ENB_DEFAULT                 _MK_MASK_CONST(0x0)
+#define ARVDE_BSEV_SECURE_INPUT_SELECT_0_SECURE_RNG_ENB_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define ARVDE_BSEV_SECURE_INPUT_SELECT_0_SECURE_RNG_ENB_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define ARVDE_BSEV_SECURE_INPUT_SELECT_0_SECURE_RNG_ENB_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+// SECURE engine: Init vector select
+#define ARVDE_BSEV_SECURE_INPUT_SELECT_0_SECURE_IV_SELECT_SHIFT                 _MK_SHIFT_CONST(10)
+#define ARVDE_BSEV_SECURE_INPUT_SELECT_0_SECURE_IV_SELECT_FIELD                 (_MK_MASK_CONST(0x1) << ARVDE_BSEV_SECURE_INPUT_SELECT_0_SECURE_IV_SELECT_SHIFT)
+#define ARVDE_BSEV_SECURE_INPUT_SELECT_0_SECURE_IV_SELECT_RANGE                 10:10
+#define ARVDE_BSEV_SECURE_INPUT_SELECT_0_SECURE_IV_SELECT_WOFFSET                       0x0
+#define ARVDE_BSEV_SECURE_INPUT_SELECT_0_SECURE_IV_SELECT_DEFAULT                       _MK_MASK_CONST(0x0)
+#define ARVDE_BSEV_SECURE_INPUT_SELECT_0_SECURE_IV_SELECT_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define ARVDE_BSEV_SECURE_INPUT_SELECT_0_SECURE_IV_SELECT_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define ARVDE_BSEV_SECURE_INPUT_SELECT_0_SECURE_IV_SELECT_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// CRYPTO/inv-CRYPTO core selection (use for shiftrow direction)
+#define ARVDE_BSEV_SECURE_INPUT_SELECT_0_SECURE_CORE_SEL_SHIFT                  _MK_SHIFT_CONST(9)
+#define ARVDE_BSEV_SECURE_INPUT_SELECT_0_SECURE_CORE_SEL_FIELD                  (_MK_MASK_CONST(0x1) << ARVDE_BSEV_SECURE_INPUT_SELECT_0_SECURE_CORE_SEL_SHIFT)
+#define ARVDE_BSEV_SECURE_INPUT_SELECT_0_SECURE_CORE_SEL_RANGE                  9:9
+#define ARVDE_BSEV_SECURE_INPUT_SELECT_0_SECURE_CORE_SEL_WOFFSET                        0x0
+#define ARVDE_BSEV_SECURE_INPUT_SELECT_0_SECURE_CORE_SEL_DEFAULT                        _MK_MASK_CONST(0x0)
+#define ARVDE_BSEV_SECURE_INPUT_SELECT_0_SECURE_CORE_SEL_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define ARVDE_BSEV_SECURE_INPUT_SELECT_0_SECURE_CORE_SEL_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define ARVDE_BSEV_SECURE_INPUT_SELECT_0_SECURE_CORE_SEL_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// Vector RAM select
+// 00: From AHB input vector
+// 01: reserved
+// 10: Init Vector for first round and CRYPTO output for the rest rounds
+// 11: Init Vector for the first round and previous AHB input for the rest rounds
+#define ARVDE_BSEV_SECURE_INPUT_SELECT_0_SECURE_VCTRAM_SEL_SHIFT                        _MK_SHIFT_CONST(7)
+#define ARVDE_BSEV_SECURE_INPUT_SELECT_0_SECURE_VCTRAM_SEL_FIELD                        (_MK_MASK_CONST(0x3) << ARVDE_BSEV_SECURE_INPUT_SELECT_0_SECURE_VCTRAM_SEL_SHIFT)
+#define ARVDE_BSEV_SECURE_INPUT_SELECT_0_SECURE_VCTRAM_SEL_RANGE                        8:7
+#define ARVDE_BSEV_SECURE_INPUT_SELECT_0_SECURE_VCTRAM_SEL_WOFFSET                      0x0
+#define ARVDE_BSEV_SECURE_INPUT_SELECT_0_SECURE_VCTRAM_SEL_DEFAULT                      _MK_MASK_CONST(0x0)
+#define ARVDE_BSEV_SECURE_INPUT_SELECT_0_SECURE_VCTRAM_SEL_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
+#define ARVDE_BSEV_SECURE_INPUT_SELECT_0_SECURE_VCTRAM_SEL_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define ARVDE_BSEV_SECURE_INPUT_SELECT_0_SECURE_VCTRAM_SEL_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+// CRYPTO input select
+// 00: From AHB input vector
+// 01: reserved
+// 10: Init Vector for first round and CRYPTO output for the rest rounds
+// 11: Counter
+#define ARVDE_BSEV_SECURE_INPUT_SELECT_0_SECURE_INPUT_SEL_SHIFT                 _MK_SHIFT_CONST(5)
+#define ARVDE_BSEV_SECURE_INPUT_SELECT_0_SECURE_INPUT_SEL_FIELD                 (_MK_MASK_CONST(0x3) << ARVDE_BSEV_SECURE_INPUT_SELECT_0_SECURE_INPUT_SEL_SHIFT)
+#define ARVDE_BSEV_SECURE_INPUT_SELECT_0_SECURE_INPUT_SEL_RANGE                 6:5
+#define ARVDE_BSEV_SECURE_INPUT_SELECT_0_SECURE_INPUT_SEL_WOFFSET                       0x0
+#define ARVDE_BSEV_SECURE_INPUT_SELECT_0_SECURE_INPUT_SEL_DEFAULT                       _MK_MASK_CONST(0x0)
+#define ARVDE_BSEV_SECURE_INPUT_SELECT_0_SECURE_INPUT_SEL_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define ARVDE_BSEV_SECURE_INPUT_SELECT_0_SECURE_INPUT_SEL_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define ARVDE_BSEV_SECURE_INPUT_SELECT_0_SECURE_INPUT_SEL_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// CRYPTO XOR position
+// 0x: Bypass
+// 10: top, before CRYPTO
+// 11: bottom, after CRYPTO
+#define ARVDE_BSEV_SECURE_INPUT_SELECT_0_SECURE_XOR_POS_SHIFT                   _MK_SHIFT_CONST(3)
+#define ARVDE_BSEV_SECURE_INPUT_SELECT_0_SECURE_XOR_POS_FIELD                   (_MK_MASK_CONST(0x3) << ARVDE_BSEV_SECURE_INPUT_SELECT_0_SECURE_XOR_POS_SHIFT)
+#define ARVDE_BSEV_SECURE_INPUT_SELECT_0_SECURE_XOR_POS_RANGE                   4:3
+#define ARVDE_BSEV_SECURE_INPUT_SELECT_0_SECURE_XOR_POS_WOFFSET                 0x0
+#define ARVDE_BSEV_SECURE_INPUT_SELECT_0_SECURE_XOR_POS_DEFAULT                 _MK_MASK_CONST(0x0)
+#define ARVDE_BSEV_SECURE_INPUT_SELECT_0_SECURE_XOR_POS_DEFAULT_MASK                    _MK_MASK_CONST(0x3)
+#define ARVDE_BSEV_SECURE_INPUT_SELECT_0_SECURE_XOR_POS_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define ARVDE_BSEV_SECURE_INPUT_SELECT_0_SECURE_XOR_POS_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+// CYRPTO hash enable
+#define ARVDE_BSEV_SECURE_INPUT_SELECT_0_SECURE_HASH_ENB_SHIFT                  _MK_SHIFT_CONST(2)
+#define ARVDE_BSEV_SECURE_INPUT_SELECT_0_SECURE_HASH_ENB_FIELD                  (_MK_MASK_CONST(0x1) << ARVDE_BSEV_SECURE_INPUT_SELECT_0_SECURE_HASH_ENB_SHIFT)
+#define ARVDE_BSEV_SECURE_INPUT_SELECT_0_SECURE_HASH_ENB_RANGE                  2:2
+#define ARVDE_BSEV_SECURE_INPUT_SELECT_0_SECURE_HASH_ENB_WOFFSET                        0x0
+#define ARVDE_BSEV_SECURE_INPUT_SELECT_0_SECURE_HASH_ENB_DEFAULT                        _MK_MASK_CONST(0x0)
+#define ARVDE_BSEV_SECURE_INPUT_SELECT_0_SECURE_HASH_ENB_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define ARVDE_BSEV_SECURE_INPUT_SELECT_0_SECURE_HASH_ENB_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define ARVDE_BSEV_SECURE_INPUT_SELECT_0_SECURE_HASH_ENB_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// CYRPTO hash destination, this is valid only when SECURE_HASH_ENB = 1
+// 0: Do not write output to memory pointed by destination address.
+//    Data can be read from HASH_RESULT
+// 1: Write final 128-bit output to memory pointed by destination address
+#define ARVDE_BSEV_SECURE_INPUT_SELECT_0_SECURE_HASH_DEST_SHIFT                 _MK_SHIFT_CONST(1)
+#define ARVDE_BSEV_SECURE_INPUT_SELECT_0_SECURE_HASH_DEST_FIELD                 (_MK_MASK_CONST(0x1) << ARVDE_BSEV_SECURE_INPUT_SELECT_0_SECURE_HASH_DEST_SHIFT)
+#define ARVDE_BSEV_SECURE_INPUT_SELECT_0_SECURE_HASH_DEST_RANGE                 1:1
+#define ARVDE_BSEV_SECURE_INPUT_SELECT_0_SECURE_HASH_DEST_WOFFSET                       0x0
+#define ARVDE_BSEV_SECURE_INPUT_SELECT_0_SECURE_HASH_DEST_DEFAULT                       _MK_MASK_CONST(0x0)
+#define ARVDE_BSEV_SECURE_INPUT_SELECT_0_SECURE_HASH_DEST_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define ARVDE_BSEV_SECURE_INPUT_SELECT_0_SECURE_HASH_DEST_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define ARVDE_BSEV_SECURE_INPUT_SELECT_0_SECURE_HASH_DEST_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// Register ARVDE_BSEV_SECURE_CONFIG_0
+#define ARVDE_BSEV_SECURE_CONFIG_0                      _MK_ADDR_CONST(0x1108)
+#define ARVDE_BSEV_SECURE_CONFIG_0_SECURE                       0x0
+#define ARVDE_BSEV_SECURE_CONFIG_0_WORD_COUNT                   0x1
+#define ARVDE_BSEV_SECURE_CONFIG_0_RESET_VAL                    _MK_MASK_CONST(0x0)
+#define ARVDE_BSEV_SECURE_CONFIG_0_RESET_MASK                   _MK_MASK_CONST(0x1ffffff)
+#define ARVDE_BSEV_SECURE_CONFIG_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define ARVDE_BSEV_SECURE_CONFIG_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define ARVDE_BSEV_SECURE_CONFIG_0_READ_MASK                    _MK_MASK_CONST(0x1ffffff)
+#define ARVDE_BSEV_SECURE_CONFIG_0_WRITE_MASK                   _MK_MASK_CONST(0x1ffffff)
+
+// 5-bit index to select between the 8-keys(value greater than 7 is reserved)
+#define ARVDE_BSEV_SECURE_CONFIG_0_SECURE_KEY_INDEX_SHIFT                       _MK_SHIFT_CONST(20)
+#define ARVDE_BSEV_SECURE_CONFIG_0_SECURE_KEY_INDEX_FIELD                       (_MK_MASK_CONST(0x1f) << ARVDE_BSEV_SECURE_CONFIG_0_SECURE_KEY_INDEX_SHIFT)
+#define ARVDE_BSEV_SECURE_CONFIG_0_SECURE_KEY_INDEX_RANGE                       24:20
+#define ARVDE_BSEV_SECURE_CONFIG_0_SECURE_KEY_INDEX_WOFFSET                     0x0
+#define ARVDE_BSEV_SECURE_CONFIG_0_SECURE_KEY_INDEX_DEFAULT                     _MK_MASK_CONST(0x0)
+#define ARVDE_BSEV_SECURE_CONFIG_0_SECURE_KEY_INDEX_DEFAULT_MASK                        _MK_MASK_CONST(0x1f)
+#define ARVDE_BSEV_SECURE_CONFIG_0_SECURE_KEY_INDEX_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define ARVDE_BSEV_SECURE_CONFIG_0_SECURE_KEY_INDEX_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+// Register ARVDE_BSEV_SECURE_CONFIG_EXT_0
+#define ARVDE_BSEV_SECURE_CONFIG_EXT_0                  _MK_ADDR_CONST(0x110c)
+#define ARVDE_BSEV_SECURE_CONFIG_EXT_0_SECURE                   0x0
+#define ARVDE_BSEV_SECURE_CONFIG_EXT_0_WORD_COUNT                       0x1
+#define ARVDE_BSEV_SECURE_CONFIG_EXT_0_RESET_VAL                        _MK_MASK_CONST(0x10000)
+#define ARVDE_BSEV_SECURE_CONFIG_EXT_0_RESET_MASK                       _MK_MASK_CONST(0xffff8000)
+#define ARVDE_BSEV_SECURE_CONFIG_EXT_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define ARVDE_BSEV_SECURE_CONFIG_EXT_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define ARVDE_BSEV_SECURE_CONFIG_EXT_0_READ_MASK                        _MK_MASK_CONST(0xffff8000)
+#define ARVDE_BSEV_SECURE_CONFIG_EXT_0_WRITE_MASK                       _MK_MASK_CONST(0xffff8000)
+
+// CRYPTO encryption/decryption with 16B*N offset.
+// 0: every 16B is encrypted/decrypted
+// N: first 16B is encrypted/decrypted and N*16B is not
+#define ARVDE_BSEV_SECURE_CONFIG_EXT_0_SECURE_OFFSET_CNT_SHIFT                  _MK_SHIFT_CONST(24)
+#define ARVDE_BSEV_SECURE_CONFIG_EXT_0_SECURE_OFFSET_CNT_FIELD                  (_MK_MASK_CONST(0xff) << ARVDE_BSEV_SECURE_CONFIG_EXT_0_SECURE_OFFSET_CNT_SHIFT)
+#define ARVDE_BSEV_SECURE_CONFIG_EXT_0_SECURE_OFFSET_CNT_RANGE                  31:24
+#define ARVDE_BSEV_SECURE_CONFIG_EXT_0_SECURE_OFFSET_CNT_WOFFSET                        0x0
+#define ARVDE_BSEV_SECURE_CONFIG_EXT_0_SECURE_OFFSET_CNT_DEFAULT                        _MK_MASK_CONST(0x0)
+#define ARVDE_BSEV_SECURE_CONFIG_EXT_0_SECURE_OFFSET_CNT_DEFAULT_MASK                   _MK_MASK_CONST(0xff)
+#define ARVDE_BSEV_SECURE_CONFIG_EXT_0_SECURE_OFFSET_CNT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define ARVDE_BSEV_SECURE_CONFIG_EXT_0_SECURE_OFFSET_CNT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// Must be set to 0. Anything else is illegal.
+#define ARVDE_BSEV_SECURE_CONFIG_EXT_0_SECURE_KEY_SCH_DIS_SHIFT                 _MK_SHIFT_CONST(15)
+#define ARVDE_BSEV_SECURE_CONFIG_EXT_0_SECURE_KEY_SCH_DIS_FIELD                 (_MK_MASK_CONST(0x1) << ARVDE_BSEV_SECURE_CONFIG_EXT_0_SECURE_KEY_SCH_DIS_SHIFT)
+#define ARVDE_BSEV_SECURE_CONFIG_EXT_0_SECURE_KEY_SCH_DIS_RANGE                 15:15
+#define ARVDE_BSEV_SECURE_CONFIG_EXT_0_SECURE_KEY_SCH_DIS_WOFFSET                       0x0
+#define ARVDE_BSEV_SECURE_CONFIG_EXT_0_SECURE_KEY_SCH_DIS_DEFAULT                       _MK_MASK_CONST(0x0)
+#define ARVDE_BSEV_SECURE_CONFIG_EXT_0_SECURE_KEY_SCH_DIS_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define ARVDE_BSEV_SECURE_CONFIG_EXT_0_SECURE_KEY_SCH_DIS_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define ARVDE_BSEV_SECURE_CONFIG_EXT_0_SECURE_KEY_SCH_DIS_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// Register ARVDE_BSEV_SECURE_SECURITY_0
+#define ARVDE_BSEV_SECURE_SECURITY_0                    _MK_ADDR_CONST(0x1110)
+#define ARVDE_BSEV_SECURE_SECURITY_0_SECURE                     0x0
+#define ARVDE_BSEV_SECURE_SECURITY_0_WORD_COUNT                         0x1
+#define ARVDE_BSEV_SECURE_SECURITY_0_RESET_VAL                  _MK_MASK_CONST(0x6)
+#define ARVDE_BSEV_SECURE_SECURITY_0_RESET_MASK                         _MK_MASK_CONST(0x7)
+#define ARVDE_BSEV_SECURE_SECURITY_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define ARVDE_BSEV_SECURE_SECURITY_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define ARVDE_BSEV_SECURE_SECURITY_0_READ_MASK                  _MK_MASK_CONST(0x7)
+#define ARVDE_BSEV_SECURE_SECURITY_0_WRITE_MASK                         _MK_MASK_CONST(0x7)
+
+// Sticky bit. Must be set to 0.
+#define ARVDE_BSEV_SECURE_SECURITY_0_KEY_SCHED_READ_SHIFT                       _MK_SHIFT_CONST(1)
+#define ARVDE_BSEV_SECURE_SECURITY_0_KEY_SCHED_READ_FIELD                       (_MK_MASK_CONST(0x1) << ARVDE_BSEV_SECURE_SECURITY_0_KEY_SCHED_READ_SHIFT)
+#define ARVDE_BSEV_SECURE_SECURITY_0_KEY_SCHED_READ_RANGE                       1:1
+#define ARVDE_BSEV_SECURE_SECURITY_0_KEY_SCHED_READ_WOFFSET                     0x0
+#define ARVDE_BSEV_SECURE_SECURITY_0_KEY_SCHED_READ_DEFAULT                     _MK_MASK_CONST(0x1)
+#define ARVDE_BSEV_SECURE_SECURITY_0_KEY_SCHED_READ_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define ARVDE_BSEV_SECURE_SECURITY_0_KEY_SCHED_READ_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define ARVDE_BSEV_SECURE_SECURITY_0_KEY_SCHED_READ_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+// Sticky bit. When this value is "1", crypto engine will be disabled.
+// Software will not be able to use the crypto engine until the next system reset.
+#define ARVDE_BSEV_SECURE_SECURITY_0_SECURE_ENG_DIS_SHIFT                       _MK_SHIFT_CONST(0)
+#define ARVDE_BSEV_SECURE_SECURITY_0_SECURE_ENG_DIS_FIELD                       (_MK_MASK_CONST(0x1) << ARVDE_BSEV_SECURE_SECURITY_0_SECURE_ENG_DIS_SHIFT)
+#define ARVDE_BSEV_SECURE_SECURITY_0_SECURE_ENG_DIS_RANGE                       0:0
+#define ARVDE_BSEV_SECURE_SECURITY_0_SECURE_ENG_DIS_WOFFSET                     0x0
+#define ARVDE_BSEV_SECURE_SECURITY_0_SECURE_ENG_DIS_DEFAULT                     _MK_MASK_CONST(0x0)
+#define ARVDE_BSEV_SECURE_SECURITY_0_SECURE_ENG_DIS_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define ARVDE_BSEV_SECURE_SECURITY_0_SECURE_ENG_DIS_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define ARVDE_BSEV_SECURE_SECURITY_0_SECURE_ENG_DIS_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+// Register ARVDE_BSEV_SECURE_HASH_RESULT0_0
+#define ARVDE_BSEV_SECURE_HASH_RESULT0_0                        _MK_ADDR_CONST(0x1120)
+#define ARVDE_BSEV_SECURE_HASH_RESULT0_0_SECURE                         0x0
+#define ARVDE_BSEV_SECURE_HASH_RESULT0_0_WORD_COUNT                     0x1
+#define ARVDE_BSEV_SECURE_HASH_RESULT0_0_RESET_VAL                      _MK_MASK_CONST(0x0)
+#define ARVDE_BSEV_SECURE_HASH_RESULT0_0_RESET_MASK                     _MK_MASK_CONST(0xffffffff)
+#define ARVDE_BSEV_SECURE_HASH_RESULT0_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
+#define ARVDE_BSEV_SECURE_HASH_RESULT0_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define ARVDE_BSEV_SECURE_HASH_RESULT0_0_READ_MASK                      _MK_MASK_CONST(0xffffffff)
+#define ARVDE_BSEV_SECURE_HASH_RESULT0_0_WRITE_MASK                     _MK_MASK_CONST(0xffffffff)
+
+// CRYPTO Hash result [31:0]
+#define ARVDE_BSEV_SECURE_HASH_RESULT0_0_SECURE_HASH_RESULT0_SHIFT                      _MK_SHIFT_CONST(0)
+#define ARVDE_BSEV_SECURE_HASH_RESULT0_0_SECURE_HASH_RESULT0_FIELD                      (_MK_MASK_CONST(0xffffffff) << ARVDE_BSEV_SECURE_HASH_RESULT0_0_SECURE_HASH_RESULT0_SHIFT)
+#define ARVDE_BSEV_SECURE_HASH_RESULT0_0_SECURE_HASH_RESULT0_RANGE                      31:0
+#define ARVDE_BSEV_SECURE_HASH_RESULT0_0_SECURE_HASH_RESULT0_WOFFSET                    0x0
+#define ARVDE_BSEV_SECURE_HASH_RESULT0_0_SECURE_HASH_RESULT0_DEFAULT                    _MK_MASK_CONST(0x0)
+#define ARVDE_BSEV_SECURE_HASH_RESULT0_0_SECURE_HASH_RESULT0_DEFAULT_MASK                       _MK_MASK_CONST(0xffffffff)
+#define ARVDE_BSEV_SECURE_HASH_RESULT0_0_SECURE_HASH_RESULT0_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define ARVDE_BSEV_SECURE_HASH_RESULT0_0_SECURE_HASH_RESULT0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// Register ARVDE_BSEV_SECURE_HASH_RESULT1_0
+#define ARVDE_BSEV_SECURE_HASH_RESULT1_0                        _MK_ADDR_CONST(0x1124)
+#define ARVDE_BSEV_SECURE_HASH_RESULT1_0_SECURE                         0x0
+#define ARVDE_BSEV_SECURE_HASH_RESULT1_0_WORD_COUNT                     0x1
+#define ARVDE_BSEV_SECURE_HASH_RESULT1_0_RESET_VAL                      _MK_MASK_CONST(0x0)
+#define ARVDE_BSEV_SECURE_HASH_RESULT1_0_RESET_MASK                     _MK_MASK_CONST(0xffffffff)
+#define ARVDE_BSEV_SECURE_HASH_RESULT1_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
+#define ARVDE_BSEV_SECURE_HASH_RESULT1_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define ARVDE_BSEV_SECURE_HASH_RESULT1_0_READ_MASK                      _MK_MASK_CONST(0xffffffff)
+#define ARVDE_BSEV_SECURE_HASH_RESULT1_0_WRITE_MASK                     _MK_MASK_CONST(0xffffffff)
+
+// CRYPTO Hash result [63:32]
+#define ARVDE_BSEV_SECURE_HASH_RESULT1_0_SECURE_HASH_RESULT1_SHIFT                      _MK_SHIFT_CONST(0)
+#define ARVDE_BSEV_SECURE_HASH_RESULT1_0_SECURE_HASH_RESULT1_FIELD                      (_MK_MASK_CONST(0xffffffff) << ARVDE_BSEV_SECURE_HASH_RESULT1_0_SECURE_HASH_RESULT1_SHIFT)
+#define ARVDE_BSEV_SECURE_HASH_RESULT1_0_SECURE_HASH_RESULT1_RANGE                      31:0
+#define ARVDE_BSEV_SECURE_HASH_RESULT1_0_SECURE_HASH_RESULT1_WOFFSET                    0x0
+#define ARVDE_BSEV_SECURE_HASH_RESULT1_0_SECURE_HASH_RESULT1_DEFAULT                    _MK_MASK_CONST(0x0)
+#define ARVDE_BSEV_SECURE_HASH_RESULT1_0_SECURE_HASH_RESULT1_DEFAULT_MASK                       _MK_MASK_CONST(0xffffffff)
+#define ARVDE_BSEV_SECURE_HASH_RESULT1_0_SECURE_HASH_RESULT1_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define ARVDE_BSEV_SECURE_HASH_RESULT1_0_SECURE_HASH_RESULT1_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// Register ARVDE_BSEV_SECURE_HASH_RESULT2_0
+#define ARVDE_BSEV_SECURE_HASH_RESULT2_0                        _MK_ADDR_CONST(0x1128)
+#define ARVDE_BSEV_SECURE_HASH_RESULT2_0_SECURE                         0x0
+#define ARVDE_BSEV_SECURE_HASH_RESULT2_0_WORD_COUNT                     0x1
+#define ARVDE_BSEV_SECURE_HASH_RESULT2_0_RESET_VAL                      _MK_MASK_CONST(0x0)
+#define ARVDE_BSEV_SECURE_HASH_RESULT2_0_RESET_MASK                     _MK_MASK_CONST(0xffffffff)
+#define ARVDE_BSEV_SECURE_HASH_RESULT2_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
+#define ARVDE_BSEV_SECURE_HASH_RESULT2_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define ARVDE_BSEV_SECURE_HASH_RESULT2_0_READ_MASK                      _MK_MASK_CONST(0xffffffff)
+#define ARVDE_BSEV_SECURE_HASH_RESULT2_0_WRITE_MASK                     _MK_MASK_CONST(0xffffffff)
+
+// CRYPTO Hash result [95:64]
+#define ARVDE_BSEV_SECURE_HASH_RESULT2_0_SECURE_HASH_RESULT2_SHIFT                      _MK_SHIFT_CONST(0)
+#define ARVDE_BSEV_SECURE_HASH_RESULT2_0_SECURE_HASH_RESULT2_FIELD                      (_MK_MASK_CONST(0xffffffff) << ARVDE_BSEV_SECURE_HASH_RESULT2_0_SECURE_HASH_RESULT2_SHIFT)
+#define ARVDE_BSEV_SECURE_HASH_RESULT2_0_SECURE_HASH_RESULT2_RANGE                      31:0
+#define ARVDE_BSEV_SECURE_HASH_RESULT2_0_SECURE_HASH_RESULT2_WOFFSET                    0x0
+#define ARVDE_BSEV_SECURE_HASH_RESULT2_0_SECURE_HASH_RESULT2_DEFAULT                    _MK_MASK_CONST(0x0)
+#define ARVDE_BSEV_SECURE_HASH_RESULT2_0_SECURE_HASH_RESULT2_DEFAULT_MASK                       _MK_MASK_CONST(0xffffffff)
+#define ARVDE_BSEV_SECURE_HASH_RESULT2_0_SECURE_HASH_RESULT2_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define ARVDE_BSEV_SECURE_HASH_RESULT2_0_SECURE_HASH_RESULT2_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// Register ARVDE_BSEV_SECURE_HASH_RESULT3_0
+#define ARVDE_BSEV_SECURE_HASH_RESULT3_0                        _MK_ADDR_CONST(0x112c)
+#define ARVDE_BSEV_SECURE_HASH_RESULT3_0_SECURE                         0x0
+#define ARVDE_BSEV_SECURE_HASH_RESULT3_0_WORD_COUNT                     0x1
+#define ARVDE_BSEV_SECURE_HASH_RESULT3_0_RESET_VAL                      _MK_MASK_CONST(0x0)
+#define ARVDE_BSEV_SECURE_HASH_RESULT3_0_RESET_MASK                     _MK_MASK_CONST(0xffffffff)
+#define ARVDE_BSEV_SECURE_HASH_RESULT3_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
+#define ARVDE_BSEV_SECURE_HASH_RESULT3_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define ARVDE_BSEV_SECURE_HASH_RESULT3_0_READ_MASK                      _MK_MASK_CONST(0xffffffff)
+#define ARVDE_BSEV_SECURE_HASH_RESULT3_0_WRITE_MASK                     _MK_MASK_CONST(0xffffffff)
+
+// CRYPTO Hash result [127:96]
+#define ARVDE_BSEV_SECURE_HASH_RESULT3_0_SECURE_HASH_RESULT3_SHIFT                      _MK_SHIFT_CONST(0)
+#define ARVDE_BSEV_SECURE_HASH_RESULT3_0_SECURE_HASH_RESULT3_FIELD                      (_MK_MASK_CONST(0xffffffff) << ARVDE_BSEV_SECURE_HASH_RESULT3_0_SECURE_HASH_RESULT3_SHIFT)
+#define ARVDE_BSEV_SECURE_HASH_RESULT3_0_SECURE_HASH_RESULT3_RANGE                      31:0
+#define ARVDE_BSEV_SECURE_HASH_RESULT3_0_SECURE_HASH_RESULT3_WOFFSET                    0x0
+#define ARVDE_BSEV_SECURE_HASH_RESULT3_0_SECURE_HASH_RESULT3_DEFAULT                    _MK_MASK_CONST(0x0)
+#define ARVDE_BSEV_SECURE_HASH_RESULT3_0_SECURE_HASH_RESULT3_DEFAULT_MASK                       _MK_MASK_CONST(0xffffffff)
+#define ARVDE_BSEV_SECURE_HASH_RESULT3_0_SECURE_HASH_RESULT3_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define ARVDE_BSEV_SECURE_HASH_RESULT3_0_SECURE_HASH_RESULT3_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// Register ARVDE_BSEV_SECURE_SEC_SEL0_0
+#define ARVDE_BSEV_SECURE_SEC_SEL0_0                    _MK_ADDR_CONST(0x1140)
+#define ARVDE_BSEV_SECURE_SEC_SEL0_0_SECURE                     0x0
+#define ARVDE_BSEV_SECURE_SEC_SEL0_0_WORD_COUNT                         0x1
+#define ARVDE_BSEV_SECURE_SEC_SEL0_0_RESET_VAL                  _MK_MASK_CONST(0x1f)
+#define ARVDE_BSEV_SECURE_SEC_SEL0_0_RESET_MASK                         _MK_MASK_CONST(0x1f)
+#define ARVDE_BSEV_SECURE_SEC_SEL0_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define ARVDE_BSEV_SECURE_SEC_SEL0_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define ARVDE_BSEV_SECURE_SEC_SEL0_0_READ_MASK                  _MK_MASK_CONST(0x1f)
+#define ARVDE_BSEV_SECURE_SEC_SEL0_0_WRITE_MASK                         _MK_MASK_CONST(0x1f)
+
+// Sticky bit, When set to "0", it will not be possible to change the value of this bit until the next system reset.
+// When this value is "0", software will not be able to update key 0 and original initialization vector 0.
+#define ARVDE_BSEV_SECURE_SEC_SEL0_0_KEYUPDATE_ENB0_SHIFT                       _MK_SHIFT_CONST(1)
+#define ARVDE_BSEV_SECURE_SEC_SEL0_0_KEYUPDATE_ENB0_FIELD                       (_MK_MASK_CONST(0x1) << ARVDE_BSEV_SECURE_SEC_SEL0_0_KEYUPDATE_ENB0_SHIFT)
+#define ARVDE_BSEV_SECURE_SEC_SEL0_0_KEYUPDATE_ENB0_RANGE                       1:1
+#define ARVDE_BSEV_SECURE_SEC_SEL0_0_KEYUPDATE_ENB0_WOFFSET                     0x0
+#define ARVDE_BSEV_SECURE_SEC_SEL0_0_KEYUPDATE_ENB0_DEFAULT                     _MK_MASK_CONST(0x1)
+#define ARVDE_BSEV_SECURE_SEC_SEL0_0_KEYUPDATE_ENB0_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define ARVDE_BSEV_SECURE_SEC_SEL0_0_KEYUPDATE_ENB0_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define ARVDE_BSEV_SECURE_SEC_SEL0_0_KEYUPDATE_ENB0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+// Sticky bit, When set to "0", it will not be possible to change the value of this bit until the next system reset.
+// When this value is "0", software will not be able to read back key 0 and original initialization vector 0
+#define ARVDE_BSEV_SECURE_SEC_SEL0_0_KEYREAD_ENB0_SHIFT                 _MK_SHIFT_CONST(0)
+#define ARVDE_BSEV_SECURE_SEC_SEL0_0_KEYREAD_ENB0_FIELD                 (_MK_MASK_CONST(0x1) << ARVDE_BSEV_SECURE_SEC_SEL0_0_KEYREAD_ENB0_SHIFT)
+#define ARVDE_BSEV_SECURE_SEC_SEL0_0_KEYREAD_ENB0_RANGE                 0:0
+#define ARVDE_BSEV_SECURE_SEC_SEL0_0_KEYREAD_ENB0_WOFFSET                       0x0
+#define ARVDE_BSEV_SECURE_SEC_SEL0_0_KEYREAD_ENB0_DEFAULT                       _MK_MASK_CONST(0x1)
+#define ARVDE_BSEV_SECURE_SEC_SEL0_0_KEYREAD_ENB0_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define ARVDE_BSEV_SECURE_SEC_SEL0_0_KEYREAD_ENB0_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define ARVDE_BSEV_SECURE_SEC_SEL0_0_KEYREAD_ENB0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// Sticky bit, When set to "0", it will not be possible to change the value of this bit until the next system reset.
+// When this value is "0", software will not be able to read back the current and updated initialization vector 0.
+#define ARVDE_BSEV_SECURE_SEC_SEL0_0_IVREAD_ENB0_SHIFT                  _MK_SHIFT_CONST(2)
+#define ARVDE_BSEV_SECURE_SEC_SEL0_0_IVREAD_ENB0_FIELD                  (_MK_MASK_CONST(0x1) << ARVDE_BSEV_SECURE_SEC_SEL0_0_IVREAD_ENB0_SHIFT)
+#define ARVDE_BSEV_SECURE_SEC_SEL0_0_IVREAD_ENB0_RANGE                  2:2
+#define ARVDE_BSEV_SECURE_SEC_SEL0_0_IVREAD_ENB0_WOFFSET                        0x0
+#define ARVDE_BSEV_SECURE_SEC_SEL0_0_IVREAD_ENB0_DEFAULT                        _MK_MASK_CONST(0x1)
+#define ARVDE_BSEV_SECURE_SEC_SEL0_0_IVREAD_ENB0_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define ARVDE_BSEV_SECURE_SEC_SEL0_0_IVREAD_ENB0_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define ARVDE_BSEV_SECURE_SEC_SEL0_0_IVREAD_ENB0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// Register ARVDE_BSEV_SECURE_SEC_SEL1_0
+#define ARVDE_BSEV_SECURE_SEC_SEL1_0                    _MK_ADDR_CONST(0x1144)
+#define ARVDE_BSEV_SECURE_SEC_SEL1_0_SECURE                     0x0
+#define ARVDE_BSEV_SECURE_SEC_SEL1_0_WORD_COUNT                         0x1
+#define ARVDE_BSEV_SECURE_SEC_SEL1_0_RESET_VAL                  _MK_MASK_CONST(0x1f)
+#define ARVDE_BSEV_SECURE_SEC_SEL1_0_RESET_MASK                         _MK_MASK_CONST(0x1f)
+#define ARVDE_BSEV_SECURE_SEC_SEL1_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define ARVDE_BSEV_SECURE_SEC_SEL1_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define ARVDE_BSEV_SECURE_SEC_SEL1_0_READ_MASK                  _MK_MASK_CONST(0x1f)
+#define ARVDE_BSEV_SECURE_SEC_SEL1_0_WRITE_MASK                         _MK_MASK_CONST(0x1f)
+
+// Sticky bit, When set to "0", it will not be possible to change the value of this bit until the next system reset.
+// When this value is "0", software will not be able to update key 1 and original initialization vector 1.
+#define ARVDE_BSEV_SECURE_SEC_SEL1_0_KEYUPDATE_ENB1_SHIFT                       _MK_SHIFT_CONST(1)
+#define ARVDE_BSEV_SECURE_SEC_SEL1_0_KEYUPDATE_ENB1_FIELD                       (_MK_MASK_CONST(0x1) << ARVDE_BSEV_SECURE_SEC_SEL1_0_KEYUPDATE_ENB1_SHIFT)
+#define ARVDE_BSEV_SECURE_SEC_SEL1_0_KEYUPDATE_ENB1_RANGE                       1:1
+#define ARVDE_BSEV_SECURE_SEC_SEL1_0_KEYUPDATE_ENB1_WOFFSET                     0x0
+#define ARVDE_BSEV_SECURE_SEC_SEL1_0_KEYUPDATE_ENB1_DEFAULT                     _MK_MASK_CONST(0x1)
+#define ARVDE_BSEV_SECURE_SEC_SEL1_0_KEYUPDATE_ENB1_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define ARVDE_BSEV_SECURE_SEC_SEL1_0_KEYUPDATE_ENB1_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define ARVDE_BSEV_SECURE_SEC_SEL1_0_KEYUPDATE_ENB1_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+// Sticky bit, When set to "0", it will not be possible to change the value of this bit until the next system reset.
+// When this value is "0", software will not be able to read back key 1 and original initialization vector 1
+#define ARVDE_BSEV_SECURE_SEC_SEL1_0_KEYREAD_ENB1_SHIFT                 _MK_SHIFT_CONST(0)
+#define ARVDE_BSEV_SECURE_SEC_SEL1_0_KEYREAD_ENB1_FIELD                 (_MK_MASK_CONST(0x1) << ARVDE_BSEV_SECURE_SEC_SEL1_0_KEYREAD_ENB1_SHIFT)
+#define ARVDE_BSEV_SECURE_SEC_SEL1_0_KEYREAD_ENB1_RANGE                 0:0
+#define ARVDE_BSEV_SECURE_SEC_SEL1_0_KEYREAD_ENB1_WOFFSET                       0x0
+#define ARVDE_BSEV_SECURE_SEC_SEL1_0_KEYREAD_ENB1_DEFAULT                       _MK_MASK_CONST(0x1)
+#define ARVDE_BSEV_SECURE_SEC_SEL1_0_KEYREAD_ENB1_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define ARVDE_BSEV_SECURE_SEC_SEL1_0_KEYREAD_ENB1_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define ARVDE_BSEV_SECURE_SEC_SEL1_0_KEYREAD_ENB1_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// Sticky bit, When set to "0", it will not be possible to change the value of this bit until the next system reset.
+// When this value is "0", software will not be able to read back the current and updated initialization vector 1.
+#define ARVDE_BSEV_SECURE_SEC_SEL1_0_IVREAD_ENB1_SHIFT                  _MK_SHIFT_CONST(2)
+#define ARVDE_BSEV_SECURE_SEC_SEL1_0_IVREAD_ENB1_FIELD                  (_MK_MASK_CONST(0x1) << ARVDE_BSEV_SECURE_SEC_SEL1_0_IVREAD_ENB1_SHIFT)
+#define ARVDE_BSEV_SECURE_SEC_SEL1_0_IVREAD_ENB1_RANGE                  2:2
+#define ARVDE_BSEV_SECURE_SEC_SEL1_0_IVREAD_ENB1_WOFFSET                        0x0
+#define ARVDE_BSEV_SECURE_SEC_SEL1_0_IVREAD_ENB1_DEFAULT                        _MK_MASK_CONST(0x1)
+#define ARVDE_BSEV_SECURE_SEC_SEL1_0_IVREAD_ENB1_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define ARVDE_BSEV_SECURE_SEC_SEL1_0_IVREAD_ENB1_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define ARVDE_BSEV_SECURE_SEC_SEL1_0_IVREAD_ENB1_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// Register ARVDE_BSEV_SECURE_SEC_SEL2_0
+#define ARVDE_BSEV_SECURE_SEC_SEL2_0                    _MK_ADDR_CONST(0x1148)
+#define ARVDE_BSEV_SECURE_SEC_SEL2_0_SECURE                     0x0
+#define ARVDE_BSEV_SECURE_SEC_SEL2_0_WORD_COUNT                         0x1
+#define ARVDE_BSEV_SECURE_SEC_SEL2_0_RESET_VAL                  _MK_MASK_CONST(0x1f)
+#define ARVDE_BSEV_SECURE_SEC_SEL2_0_RESET_MASK                         _MK_MASK_CONST(0x1f)
+#define ARVDE_BSEV_SECURE_SEC_SEL2_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define ARVDE_BSEV_SECURE_SEC_SEL2_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define ARVDE_BSEV_SECURE_SEC_SEL2_0_READ_MASK                  _MK_MASK_CONST(0x1f)
+#define ARVDE_BSEV_SECURE_SEC_SEL2_0_WRITE_MASK                         _MK_MASK_CONST(0x1f)
+
+// Sticky bit, When set to "0", it will not be possible to change the value of this bit until the next system reset.
+// When this value is "0", software will not be able to update key 2 and original initialization vector 2.
+#define ARVDE_BSEV_SECURE_SEC_SEL2_0_KEYUPDATE_ENB2_SHIFT                       _MK_SHIFT_CONST(1)
+#define ARVDE_BSEV_SECURE_SEC_SEL2_0_KEYUPDATE_ENB2_FIELD                       (_MK_MASK_CONST(0x1) << ARVDE_BSEV_SECURE_SEC_SEL2_0_KEYUPDATE_ENB2_SHIFT)
+#define ARVDE_BSEV_SECURE_SEC_SEL2_0_KEYUPDATE_ENB2_RANGE                       1:1
+#define ARVDE_BSEV_SECURE_SEC_SEL2_0_KEYUPDATE_ENB2_WOFFSET                     0x0
+#define ARVDE_BSEV_SECURE_SEC_SEL2_0_KEYUPDATE_ENB2_DEFAULT                     _MK_MASK_CONST(0x1)
+#define ARVDE_BSEV_SECURE_SEC_SEL2_0_KEYUPDATE_ENB2_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define ARVDE_BSEV_SECURE_SEC_SEL2_0_KEYUPDATE_ENB2_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define ARVDE_BSEV_SECURE_SEC_SEL2_0_KEYUPDATE_ENB2_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+// Sticky bit, When set to "0", it will not be possible to change the value of this bit until the next system reset.
+// When this value is "0", software will not be able to read back key 2 and original initialization vector 2
+#define ARVDE_BSEV_SECURE_SEC_SEL2_0_KEYREAD_ENB2_SHIFT                 _MK_SHIFT_CONST(0)
+#define ARVDE_BSEV_SECURE_SEC_SEL2_0_KEYREAD_ENB2_FIELD                 (_MK_MASK_CONST(0x1) << ARVDE_BSEV_SECURE_SEC_SEL2_0_KEYREAD_ENB2_SHIFT)
+#define ARVDE_BSEV_SECURE_SEC_SEL2_0_KEYREAD_ENB2_RANGE                 0:0
+#define ARVDE_BSEV_SECURE_SEC_SEL2_0_KEYREAD_ENB2_WOFFSET                       0x0
+#define ARVDE_BSEV_SECURE_SEC_SEL2_0_KEYREAD_ENB2_DEFAULT                       _MK_MASK_CONST(0x1)
+#define ARVDE_BSEV_SECURE_SEC_SEL2_0_KEYREAD_ENB2_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define ARVDE_BSEV_SECURE_SEC_SEL2_0_KEYREAD_ENB2_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define ARVDE_BSEV_SECURE_SEC_SEL2_0_KEYREAD_ENB2_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// Sticky bit, When set to "0", it will not be possible to change the value of this bit until the next system reset.
+// When this value is "0", software will not be able to read back the current and updated initialization vector 2.
+#define ARVDE_BSEV_SECURE_SEC_SEL2_0_IVREAD_ENB2_SHIFT                  _MK_SHIFT_CONST(2)
+#define ARVDE_BSEV_SECURE_SEC_SEL2_0_IVREAD_ENB2_FIELD                  (_MK_MASK_CONST(0x1) << ARVDE_BSEV_SECURE_SEC_SEL2_0_IVREAD_ENB2_SHIFT)
+#define ARVDE_BSEV_SECURE_SEC_SEL2_0_IVREAD_ENB2_RANGE                  2:2
+#define ARVDE_BSEV_SECURE_SEC_SEL2_0_IVREAD_ENB2_WOFFSET                        0x0
+#define ARVDE_BSEV_SECURE_SEC_SEL2_0_IVREAD_ENB2_DEFAULT                        _MK_MASK_CONST(0x1)
+#define ARVDE_BSEV_SECURE_SEC_SEL2_0_IVREAD_ENB2_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define ARVDE_BSEV_SECURE_SEC_SEL2_0_IVREAD_ENB2_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define ARVDE_BSEV_SECURE_SEC_SEL2_0_IVREAD_ENB2_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// Register ARVDE_BSEV_SECURE_SEC_SEL3_0
+#define ARVDE_BSEV_SECURE_SEC_SEL3_0                    _MK_ADDR_CONST(0x114c)
+#define ARVDE_BSEV_SECURE_SEC_SEL3_0_SECURE                     0x0
+#define ARVDE_BSEV_SECURE_SEC_SEL3_0_WORD_COUNT                         0x1
+#define ARVDE_BSEV_SECURE_SEC_SEL3_0_RESET_VAL                  _MK_MASK_CONST(0x1f)
+#define ARVDE_BSEV_SECURE_SEC_SEL3_0_RESET_MASK                         _MK_MASK_CONST(0x1f)
+#define ARVDE_BSEV_SECURE_SEC_SEL3_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define ARVDE_BSEV_SECURE_SEC_SEL3_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define ARVDE_BSEV_SECURE_SEC_SEL3_0_READ_MASK                  _MK_MASK_CONST(0x1f)
+#define ARVDE_BSEV_SECURE_SEC_SEL3_0_WRITE_MASK                         _MK_MASK_CONST(0x1f)
+
+// Sticky bit, When set to "0", it will not be possible to change the value of this bit until the next system reset.
+// When this value is "0", software will not be able to update key 3 and original initialization vector 3.
+#define ARVDE_BSEV_SECURE_SEC_SEL3_0_KEYUPDATE_ENB3_SHIFT                       _MK_SHIFT_CONST(1)
+#define ARVDE_BSEV_SECURE_SEC_SEL3_0_KEYUPDATE_ENB3_FIELD                       (_MK_MASK_CONST(0x1) << ARVDE_BSEV_SECURE_SEC_SEL3_0_KEYUPDATE_ENB3_SHIFT)
+#define ARVDE_BSEV_SECURE_SEC_SEL3_0_KEYUPDATE_ENB3_RANGE                       1:1
+#define ARVDE_BSEV_SECURE_SEC_SEL3_0_KEYUPDATE_ENB3_WOFFSET                     0x0
+#define ARVDE_BSEV_SECURE_SEC_SEL3_0_KEYUPDATE_ENB3_DEFAULT                     _MK_MASK_CONST(0x1)
+#define ARVDE_BSEV_SECURE_SEC_SEL3_0_KEYUPDATE_ENB3_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define ARVDE_BSEV_SECURE_SEC_SEL3_0_KEYUPDATE_ENB3_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define ARVDE_BSEV_SECURE_SEC_SEL3_0_KEYUPDATE_ENB3_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+// Sticky bit, When set to "0", it will not be possible to change the value of this bit until the next system reset.
+// When this value is "0", software will not be able to read back key 3 and original initialization vector 3
+#define ARVDE_BSEV_SECURE_SEC_SEL3_0_KEYREAD_ENB3_SHIFT                 _MK_SHIFT_CONST(0)
+#define ARVDE_BSEV_SECURE_SEC_SEL3_0_KEYREAD_ENB3_FIELD                 (_MK_MASK_CONST(0x1) << ARVDE_BSEV_SECURE_SEC_SEL3_0_KEYREAD_ENB3_SHIFT)
+#define ARVDE_BSEV_SECURE_SEC_SEL3_0_KEYREAD_ENB3_RANGE                 0:0
+#define ARVDE_BSEV_SECURE_SEC_SEL3_0_KEYREAD_ENB3_WOFFSET                       0x0
+#define ARVDE_BSEV_SECURE_SEC_SEL3_0_KEYREAD_ENB3_DEFAULT                       _MK_MASK_CONST(0x1)
+#define ARVDE_BSEV_SECURE_SEC_SEL3_0_KEYREAD_ENB3_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define ARVDE_BSEV_SECURE_SEC_SEL3_0_KEYREAD_ENB3_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define ARVDE_BSEV_SECURE_SEC_SEL3_0_KEYREAD_ENB3_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// Sticky bit, When set to "0", it will not be possible to change the value of this bit until the next system reset.
+// When this value is "0", software will not be able to read back the current and updated initialization vector 3.
+#define ARVDE_BSEV_SECURE_SEC_SEL3_0_IVREAD_ENB3_SHIFT                  _MK_SHIFT_CONST(2)
+#define ARVDE_BSEV_SECURE_SEC_SEL3_0_IVREAD_ENB3_FIELD                  (_MK_MASK_CONST(0x1) << ARVDE_BSEV_SECURE_SEC_SEL3_0_IVREAD_ENB3_SHIFT)
+#define ARVDE_BSEV_SECURE_SEC_SEL3_0_IVREAD_ENB3_RANGE                  2:2
+#define ARVDE_BSEV_SECURE_SEC_SEL3_0_IVREAD_ENB3_WOFFSET                        0x0
+#define ARVDE_BSEV_SECURE_SEC_SEL3_0_IVREAD_ENB3_DEFAULT                        _MK_MASK_CONST(0x1)
+#define ARVDE_BSEV_SECURE_SEC_SEL3_0_IVREAD_ENB3_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define ARVDE_BSEV_SECURE_SEC_SEL3_0_IVREAD_ENB3_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define ARVDE_BSEV_SECURE_SEC_SEL3_0_IVREAD_ENB3_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// Register ARVDE_BSEV_SECURE_SEC_SEL4_0
+#define ARVDE_BSEV_SECURE_SEC_SEL4_0                    _MK_ADDR_CONST(0x1150)
+#define ARVDE_BSEV_SECURE_SEC_SEL4_0_SECURE                     0x0
+#define ARVDE_BSEV_SECURE_SEC_SEL4_0_WORD_COUNT                         0x1
+#define ARVDE_BSEV_SECURE_SEC_SEL4_0_RESET_VAL                  _MK_MASK_CONST(0x1f)
+#define ARVDE_BSEV_SECURE_SEC_SEL4_0_RESET_MASK                         _MK_MASK_CONST(0x1f)
+#define ARVDE_BSEV_SECURE_SEC_SEL4_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define ARVDE_BSEV_SECURE_SEC_SEL4_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define ARVDE_BSEV_SECURE_SEC_SEL4_0_READ_MASK                  _MK_MASK_CONST(0x1f)
+#define ARVDE_BSEV_SECURE_SEC_SEL4_0_WRITE_MASK                         _MK_MASK_CONST(0x1f)
+
+// Sticky bit, When set to "0", it will not be possible to change the value of this bit until the next system reset.
+// When this value is "0", software will not be able to update key 4 and original initialization vector 4.
+#define ARVDE_BSEV_SECURE_SEC_SEL4_0_KEYUPDATE_ENB4_SHIFT                       _MK_SHIFT_CONST(1)
+#define ARVDE_BSEV_SECURE_SEC_SEL4_0_KEYUPDATE_ENB4_FIELD                       (_MK_MASK_CONST(0x1) << ARVDE_BSEV_SECURE_SEC_SEL4_0_KEYUPDATE_ENB4_SHIFT)
+#define ARVDE_BSEV_SECURE_SEC_SEL4_0_KEYUPDATE_ENB4_RANGE                       1:1
+#define ARVDE_BSEV_SECURE_SEC_SEL4_0_KEYUPDATE_ENB4_WOFFSET                     0x0
+#define ARVDE_BSEV_SECURE_SEC_SEL4_0_KEYUPDATE_ENB4_DEFAULT                     _MK_MASK_CONST(0x1)
+#define ARVDE_BSEV_SECURE_SEC_SEL4_0_KEYUPDATE_ENB4_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define ARVDE_BSEV_SECURE_SEC_SEL4_0_KEYUPDATE_ENB4_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define ARVDE_BSEV_SECURE_SEC_SEL4_0_KEYUPDATE_ENB4_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+// Sticky bit, When set to "0", it will not be possible to change the value of this bit until the next system reset.
+// When this value is "0", software will not be able to read back key 4 and original initialization vector 4
+#define ARVDE_BSEV_SECURE_SEC_SEL4_0_KEYREAD_ENB4_SHIFT                 _MK_SHIFT_CONST(0)
+#define ARVDE_BSEV_SECURE_SEC_SEL4_0_KEYREAD_ENB4_FIELD                 (_MK_MASK_CONST(0x1) << ARVDE_BSEV_SECURE_SEC_SEL4_0_KEYREAD_ENB4_SHIFT)
+#define ARVDE_BSEV_SECURE_SEC_SEL4_0_KEYREAD_ENB4_RANGE                 0:0
+#define ARVDE_BSEV_SECURE_SEC_SEL4_0_KEYREAD_ENB4_WOFFSET                       0x0
+#define ARVDE_BSEV_SECURE_SEC_SEL4_0_KEYREAD_ENB4_DEFAULT                       _MK_MASK_CONST(0x1)
+#define ARVDE_BSEV_SECURE_SEC_SEL4_0_KEYREAD_ENB4_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define ARVDE_BSEV_SECURE_SEC_SEL4_0_KEYREAD_ENB4_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define ARVDE_BSEV_SECURE_SEC_SEL4_0_KEYREAD_ENB4_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// Sticky bit, When set to "0", it will not be possible to change the value of this bit until the next system reset.
+// When this value is "0", software will not be able to read back the current and updated initialization vector 4.
+#define ARVDE_BSEV_SECURE_SEC_SEL4_0_IVREAD_ENB4_SHIFT                  _MK_SHIFT_CONST(2)
+#define ARVDE_BSEV_SECURE_SEC_SEL4_0_IVREAD_ENB4_FIELD                  (_MK_MASK_CONST(0x1) << ARVDE_BSEV_SECURE_SEC_SEL4_0_IVREAD_ENB4_SHIFT)
+#define ARVDE_BSEV_SECURE_SEC_SEL4_0_IVREAD_ENB4_RANGE                  2:2
+#define ARVDE_BSEV_SECURE_SEC_SEL4_0_IVREAD_ENB4_WOFFSET                        0x0
+#define ARVDE_BSEV_SECURE_SEC_SEL4_0_IVREAD_ENB4_DEFAULT                        _MK_MASK_CONST(0x1)
+#define ARVDE_BSEV_SECURE_SEC_SEL4_0_IVREAD_ENB4_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define ARVDE_BSEV_SECURE_SEC_SEL4_0_IVREAD_ENB4_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define ARVDE_BSEV_SECURE_SEC_SEL4_0_IVREAD_ENB4_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// Register ARVDE_BSEV_SECURE_SEC_SEL5_0
+#define ARVDE_BSEV_SECURE_SEC_SEL5_0                    _MK_ADDR_CONST(0x1154)
+#define ARVDE_BSEV_SECURE_SEC_SEL5_0_SECURE                     0x0
+#define ARVDE_BSEV_SECURE_SEC_SEL5_0_WORD_COUNT                         0x1
+#define ARVDE_BSEV_SECURE_SEC_SEL5_0_RESET_VAL                  _MK_MASK_CONST(0x1f)
+#define ARVDE_BSEV_SECURE_SEC_SEL5_0_RESET_MASK                         _MK_MASK_CONST(0x1f)
+#define ARVDE_BSEV_SECURE_SEC_SEL5_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define ARVDE_BSEV_SECURE_SEC_SEL5_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define ARVDE_BSEV_SECURE_SEC_SEL5_0_READ_MASK                  _MK_MASK_CONST(0x1f)
+#define ARVDE_BSEV_SECURE_SEC_SEL5_0_WRITE_MASK                         _MK_MASK_CONST(0x1f)
+
+// Sticky bit, When set to "0", it will not be possible to change the value of this bit until the next system reset.
+// When this value is "0", software will not be able to update key 5 and original initialization vector 5.
+#define ARVDE_BSEV_SECURE_SEC_SEL5_0_KEYUPDATE_ENB5_SHIFT                       _MK_SHIFT_CONST(1)
+#define ARVDE_BSEV_SECURE_SEC_SEL5_0_KEYUPDATE_ENB5_FIELD                       (_MK_MASK_CONST(0x1) << ARVDE_BSEV_SECURE_SEC_SEL5_0_KEYUPDATE_ENB5_SHIFT)
+#define ARVDE_BSEV_SECURE_SEC_SEL5_0_KEYUPDATE_ENB5_RANGE                       1:1
+#define ARVDE_BSEV_SECURE_SEC_SEL5_0_KEYUPDATE_ENB5_WOFFSET                     0x0
+#define ARVDE_BSEV_SECURE_SEC_SEL5_0_KEYUPDATE_ENB5_DEFAULT                     _MK_MASK_CONST(0x1)
+#define ARVDE_BSEV_SECURE_SEC_SEL5_0_KEYUPDATE_ENB5_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define ARVDE_BSEV_SECURE_SEC_SEL5_0_KEYUPDATE_ENB5_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define ARVDE_BSEV_SECURE_SEC_SEL5_0_KEYUPDATE_ENB5_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+// Sticky bit, When set to "0", it will not be possible to change the value of this bit until the next system reset.
+// When this value is "0", software will not be able to read back key 5 and original initialization vector 5
+#define ARVDE_BSEV_SECURE_SEC_SEL5_0_KEYREAD_ENB5_SHIFT                 _MK_SHIFT_CONST(0)
+#define ARVDE_BSEV_SECURE_SEC_SEL5_0_KEYREAD_ENB5_FIELD                 (_MK_MASK_CONST(0x1) << ARVDE_BSEV_SECURE_SEC_SEL5_0_KEYREAD_ENB5_SHIFT)
+#define ARVDE_BSEV_SECURE_SEC_SEL5_0_KEYREAD_ENB5_RANGE                 0:0
+#define ARVDE_BSEV_SECURE_SEC_SEL5_0_KEYREAD_ENB5_WOFFSET                       0x0
+#define ARVDE_BSEV_SECURE_SEC_SEL5_0_KEYREAD_ENB5_DEFAULT                       _MK_MASK_CONST(0x1)
+#define ARVDE_BSEV_SECURE_SEC_SEL5_0_KEYREAD_ENB5_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define ARVDE_BSEV_SECURE_SEC_SEL5_0_KEYREAD_ENB5_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define ARVDE_BSEV_SECURE_SEC_SEL5_0_KEYREAD_ENB5_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// Sticky bit, When set to "0", it will not be possible to change the value of this bit until the next system reset.
+// When this value is "0", software will not be able to read back the current and updated initialization vector 5.
+#define ARVDE_BSEV_SECURE_SEC_SEL5_0_IVREAD_ENB5_SHIFT                  _MK_SHIFT_CONST(2)
+#define ARVDE_BSEV_SECURE_SEC_SEL5_0_IVREAD_ENB5_FIELD                  (_MK_MASK_CONST(0x1) << ARVDE_BSEV_SECURE_SEC_SEL5_0_IVREAD_ENB5_SHIFT)
+#define ARVDE_BSEV_SECURE_SEC_SEL5_0_IVREAD_ENB5_RANGE                  2:2
+#define ARVDE_BSEV_SECURE_SEC_SEL5_0_IVREAD_ENB5_WOFFSET                        0x0
+#define ARVDE_BSEV_SECURE_SEC_SEL5_0_IVREAD_ENB5_DEFAULT                        _MK_MASK_CONST(0x1)
+#define ARVDE_BSEV_SECURE_SEC_SEL5_0_IVREAD_ENB5_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define ARVDE_BSEV_SECURE_SEC_SEL5_0_IVREAD_ENB5_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define ARVDE_BSEV_SECURE_SEC_SEL5_0_IVREAD_ENB5_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// Register ARVDE_BSEV_SECURE_SEC_SEL6_0
+#define ARVDE_BSEV_SECURE_SEC_SEL6_0                    _MK_ADDR_CONST(0x1158)
+#define ARVDE_BSEV_SECURE_SEC_SEL6_0_SECURE                     0x0
+#define ARVDE_BSEV_SECURE_SEC_SEL6_0_WORD_COUNT                         0x1
+#define ARVDE_BSEV_SECURE_SEC_SEL6_0_RESET_VAL                  _MK_MASK_CONST(0x1f)
+#define ARVDE_BSEV_SECURE_SEC_SEL6_0_RESET_MASK                         _MK_MASK_CONST(0x1f)
+#define ARVDE_BSEV_SECURE_SEC_SEL6_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define ARVDE_BSEV_SECURE_SEC_SEL6_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define ARVDE_BSEV_SECURE_SEC_SEL6_0_READ_MASK                  _MK_MASK_CONST(0x1f)
+#define ARVDE_BSEV_SECURE_SEC_SEL6_0_WRITE_MASK                         _MK_MASK_CONST(0x1f)
+
+// Sticky bit, When set to "0", it will not be possible to change the value of this bit until the next system reset.
+// When this value is "0", software will not be able to update key 6 and original initialization vector 6.
+#define ARVDE_BSEV_SECURE_SEC_SEL6_0_KEYUPDATE_ENB6_SHIFT                       _MK_SHIFT_CONST(1)
+#define ARVDE_BSEV_SECURE_SEC_SEL6_0_KEYUPDATE_ENB6_FIELD                       (_MK_MASK_CONST(0x1) << ARVDE_BSEV_SECURE_SEC_SEL6_0_KEYUPDATE_ENB6_SHIFT)
+#define ARVDE_BSEV_SECURE_SEC_SEL6_0_KEYUPDATE_ENB6_RANGE                       1:1
+#define ARVDE_BSEV_SECURE_SEC_SEL6_0_KEYUPDATE_ENB6_WOFFSET                     0x0
+#define ARVDE_BSEV_SECURE_SEC_SEL6_0_KEYUPDATE_ENB6_DEFAULT                     _MK_MASK_CONST(0x1)
+#define ARVDE_BSEV_SECURE_SEC_SEL6_0_KEYUPDATE_ENB6_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define ARVDE_BSEV_SECURE_SEC_SEL6_0_KEYUPDATE_ENB6_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define ARVDE_BSEV_SECURE_SEC_SEL6_0_KEYUPDATE_ENB6_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+// Sticky bit, When set to "0", it will not be possible to change the value of this bit until the next system reset.
+// When this value is "0", software will not be able to read back key 6 and original initialization vector 6
+#define ARVDE_BSEV_SECURE_SEC_SEL6_0_KEYREAD_ENB6_SHIFT                 _MK_SHIFT_CONST(0)
+#define ARVDE_BSEV_SECURE_SEC_SEL6_0_KEYREAD_ENB6_FIELD                 (_MK_MASK_CONST(0x1) << ARVDE_BSEV_SECURE_SEC_SEL6_0_KEYREAD_ENB6_SHIFT)
+#define ARVDE_BSEV_SECURE_SEC_SEL6_0_KEYREAD_ENB6_RANGE                 0:0
+#define ARVDE_BSEV_SECURE_SEC_SEL6_0_KEYREAD_ENB6_WOFFSET                       0x0
+#define ARVDE_BSEV_SECURE_SEC_SEL6_0_KEYREAD_ENB6_DEFAULT                       _MK_MASK_CONST(0x1)
+#define ARVDE_BSEV_SECURE_SEC_SEL6_0_KEYREAD_ENB6_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define ARVDE_BSEV_SECURE_SEC_SEL6_0_KEYREAD_ENB6_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define ARVDE_BSEV_SECURE_SEC_SEL6_0_KEYREAD_ENB6_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// Sticky bit, When set to "0", it will not be possible to change the value of this bit until the next system reset.
+// When this value is "0", software will not be able to read back the current and updated initialization vector 6.
+#define ARVDE_BSEV_SECURE_SEC_SEL6_0_IVREAD_ENB6_SHIFT                  _MK_SHIFT_CONST(2)
+#define ARVDE_BSEV_SECURE_SEC_SEL6_0_IVREAD_ENB6_FIELD                  (_MK_MASK_CONST(0x1) << ARVDE_BSEV_SECURE_SEC_SEL6_0_IVREAD_ENB6_SHIFT)
+#define ARVDE_BSEV_SECURE_SEC_SEL6_0_IVREAD_ENB6_RANGE                  2:2
+#define ARVDE_BSEV_SECURE_SEC_SEL6_0_IVREAD_ENB6_WOFFSET                        0x0
+#define ARVDE_BSEV_SECURE_SEC_SEL6_0_IVREAD_ENB6_DEFAULT                        _MK_MASK_CONST(0x1)
+#define ARVDE_BSEV_SECURE_SEC_SEL6_0_IVREAD_ENB6_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define ARVDE_BSEV_SECURE_SEC_SEL6_0_IVREAD_ENB6_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define ARVDE_BSEV_SECURE_SEC_SEL6_0_IVREAD_ENB6_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// Register ARVDE_BSEV_SECURE_SEC_SEL7_0
+#define ARVDE_BSEV_SECURE_SEC_SEL7_0                    _MK_ADDR_CONST(0x115c)
+#define ARVDE_BSEV_SECURE_SEC_SEL7_0_SECURE                     0x0
+#define ARVDE_BSEV_SECURE_SEC_SEL7_0_WORD_COUNT                         0x1
+#define ARVDE_BSEV_SECURE_SEC_SEL7_0_RESET_VAL                  _MK_MASK_CONST(0x1f)
+#define ARVDE_BSEV_SECURE_SEC_SEL7_0_RESET_MASK                         _MK_MASK_CONST(0x1f)
+#define ARVDE_BSEV_SECURE_SEC_SEL7_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define ARVDE_BSEV_SECURE_SEC_SEL7_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define ARVDE_BSEV_SECURE_SEC_SEL7_0_READ_MASK                  _MK_MASK_CONST(0x1f)
+#define ARVDE_BSEV_SECURE_SEC_SEL7_0_WRITE_MASK                         _MK_MASK_CONST(0x1f)
+
+// Sticky bit, When set to "0", it will not be possible to change the value of this bit until the next system reset.
+// When this value is "0", software will not be able to update key 7 and original initialization vector 7.
+#define ARVDE_BSEV_SECURE_SEC_SEL7_0_KEYUPDATE_ENB7_SHIFT                       _MK_SHIFT_CONST(1)
+#define ARVDE_BSEV_SECURE_SEC_SEL7_0_KEYUPDATE_ENB7_FIELD                       (_MK_MASK_CONST(0x1) << ARVDE_BSEV_SECURE_SEC_SEL7_0_KEYUPDATE_ENB7_SHIFT)
+#define ARVDE_BSEV_SECURE_SEC_SEL7_0_KEYUPDATE_ENB7_RANGE                       1:1
+#define ARVDE_BSEV_SECURE_SEC_SEL7_0_KEYUPDATE_ENB7_WOFFSET                     0x0
+#define ARVDE_BSEV_SECURE_SEC_SEL7_0_KEYUPDATE_ENB7_DEFAULT                     _MK_MASK_CONST(0x1)
+#define ARVDE_BSEV_SECURE_SEC_SEL7_0_KEYUPDATE_ENB7_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define ARVDE_BSEV_SECURE_SEC_SEL7_0_KEYUPDATE_ENB7_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define ARVDE_BSEV_SECURE_SEC_SEL7_0_KEYUPDATE_ENB7_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+// Sticky bit, When set to "0", it will not be possible to change the value of this bit until the next system reset.
+// When this value is "0", software will not be able to read back key 7 and original initialization vector 7
+#define ARVDE_BSEV_SECURE_SEC_SEL7_0_KEYREAD_ENB7_SHIFT                 _MK_SHIFT_CONST(0)
+#define ARVDE_BSEV_SECURE_SEC_SEL7_0_KEYREAD_ENB7_FIELD                 (_MK_MASK_CONST(0x1) << ARVDE_BSEV_SECURE_SEC_SEL7_0_KEYREAD_ENB7_SHIFT)
+#define ARVDE_BSEV_SECURE_SEC_SEL7_0_KEYREAD_ENB7_RANGE                 0:0
+#define ARVDE_BSEV_SECURE_SEC_SEL7_0_KEYREAD_ENB7_WOFFSET                       0x0
+#define ARVDE_BSEV_SECURE_SEC_SEL7_0_KEYREAD_ENB7_DEFAULT                       _MK_MASK_CONST(0x1)
+#define ARVDE_BSEV_SECURE_SEC_SEL7_0_KEYREAD_ENB7_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define ARVDE_BSEV_SECURE_SEC_SEL7_0_KEYREAD_ENB7_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define ARVDE_BSEV_SECURE_SEC_SEL7_0_KEYREAD_ENB7_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// Sticky bit, When set to "0", it will not be possible to change the value of this bit until the next system reset.
+// When this value is "0", software will not be able to read back the current and updated initialization vector 7.
+#define ARVDE_BSEV_SECURE_SEC_SEL7_0_IVREAD_ENB7_SHIFT                  _MK_SHIFT_CONST(2)
+#define ARVDE_BSEV_SECURE_SEC_SEL7_0_IVREAD_ENB7_FIELD                  (_MK_MASK_CONST(0x1) << ARVDE_BSEV_SECURE_SEC_SEL7_0_IVREAD_ENB7_SHIFT)
+#define ARVDE_BSEV_SECURE_SEC_SEL7_0_IVREAD_ENB7_RANGE                  2:2
+#define ARVDE_BSEV_SECURE_SEC_SEL7_0_IVREAD_ENB7_WOFFSET                        0x0
+#define ARVDE_BSEV_SECURE_SEC_SEL7_0_IVREAD_ENB7_DEFAULT                        _MK_MASK_CONST(0x1)
+#define ARVDE_BSEV_SECURE_SEC_SEL7_0_IVREAD_ENB7_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define ARVDE_BSEV_SECURE_SEC_SEL7_0_IVREAD_ENB7_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define ARVDE_BSEV_SECURE_SEC_SEL7_0_IVREAD_ENB7_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+#endif // ifndef ___ARVDE_BSEV_AES_H_INC_
+
author	Gary King <gking@nvidia.com>	2010-06-07 09:46:21 -0700
committer	Gary King <gking@nvidia.com>	2010-06-07 12:35:55 -0700
commit	4dcd7a1c7fc8a02c93f9bdf954dda9eab6cad44f (patch)
tree	f27737f0bd8b03a11902e0ce7dc8ac9627362723 /arch/arm/mach-tegra/include/ap20
parent	5ce1e0a1a36b2034708366a47a88fce38ef4a252 (diff)