diff options
author | Alex Frid <afrid@nvidia.com> | 2012-01-14 17:48:15 -0800 |
---|---|---|
committer | Dan Willemsen <dwillemsen@nvidia.com> | 2013-09-14 00:59:01 -0700 |
commit | af65341f5998ea777e8a376153b5f40752b9c223 (patch) | |
tree | 097cdbf3ac6d7d9e1855f7490e917a2a31875c3a /arch/arm/mach-tegra/include/mach/uncompress.h | |
parent | 931787a1847eb918d898240c44b7983e700ada09 (diff) |
ARM: tegra: clock: Auto-detect PLLP rate in kernel uncompress
Tegra3 platform may boot with one of the predefined fixed PLLP
(peripheral PLL) output rates: 216MHz, 408MHz, or 204MHz. This
commit implements auto-detection of PLLP rate, and debug uart
configuration during kernel uncompressing.
Bug 928260
Change-Id: I435c228691191434a10847fdbccef048a8d507c7
Reviewed-on: http://git-master/r/75848
Signed-off-by: Alex Frid <afrid@nvidia.com>
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Reviewed-on: http://git-master/r/77293
Reviewed-by: Automatic_Commit_Validation_User
Rebase-Id: R3378ab9504babe64eb1e6433d1affd738a7b1250
Diffstat (limited to 'arch/arm/mach-tegra/include/mach/uncompress.h')
-rw-r--r-- | arch/arm/mach-tegra/include/mach/uncompress.h | 48 |
1 files changed, 41 insertions, 7 deletions
diff --git a/arch/arm/mach-tegra/include/mach/uncompress.h b/arch/arm/mach-tegra/include/mach/uncompress.h index 77241f593a03..6dc6bfc59b54 100644 --- a/arch/arm/mach-tegra/include/mach/uncompress.h +++ b/arch/arm/mach-tegra/include/mach/uncompress.h @@ -11,7 +11,7 @@ * Doug Anderson <dianders@chromium.org> * Stephen Warren <swarren@nvidia.com> * - * Copyright (C) 2010-2011 NVIDIA Corporation + * Copyright (C) 2010-2012 NVIDIA Corporation * * This software is licensed under the terms of the GNU General Public * License version 2, as published by the Free Software Foundation, and @@ -76,6 +76,16 @@ volatile u8 *uart; #define DEBUG_UART_RST_CLR_REG 0 #define DEBUG_UART_RST_CLR_BIT 0 #endif +#define PLLP_BASE (TEGRA_CLK_RESET_BASE + 0x0a0) +#define PLLP_BASE_OVERRIDE (1 << 28) +#define PLLP_BASE_DIVP_SHIFT 20 +#define PLLP_BASE_DIVP_MASK (0x7 << 20) +#define PLLP_BASE_DIVN_SHIFT 8 +#define PLLP_BASE_DIVN_MASK (0x3FF << 8) + +#define DEBUG_UART_DLL_216 0x75 +#define DEBUG_UART_DLL_408 0xdd +#define DEBUG_UART_DLL_204 0x6f static void putc(int c) { @@ -175,7 +185,9 @@ static inline void arch_decomp_setup(void) { int uart_id; volatile u32 *apb_misc = (volatile u32 *)TEGRA_APB_MISC_BASE; - u32 chip, div; + volatile u32 *addr; + u32 div = DEBUG_UART_DLL_216; + u32 val; #if defined(CONFIG_TEGRA_DEBUG_UART_AUTO_ODMDATA) uart_id = auto_odmdata(); @@ -200,11 +212,33 @@ static inline void arch_decomp_setup(void) if (uart == NULL) return; - chip = (apb_misc[0x804 / 4] >> 8) & 0xff; - if (chip == 0x20) - div = 0x0075; - else - div = 0x00dd; + /* + * On Tegra2 platforms PLLP always run at 216MHz + * On Tegra3 platforms PLLP can run at 216MHz, 204MHz, or 408MHz + * Discrimantion algorithm below assumes that PLLP is configured + * according to h/w recomendations with update rate 1MHz or 1.2MHz + * depending on oscillator frequency + */ + addr = (volatile u32 *)PLLP_BASE; + val = *addr; + if (val & PLLP_BASE_OVERRIDE) { + u32 p = (val & PLLP_BASE_DIVP_MASK) >> PLLP_BASE_DIVP_SHIFT; + val = (val & PLLP_BASE_DIVN_MASK) >> (PLLP_BASE_DIVN_SHIFT + p); + switch (val) { + case 170: + case 204: + div = DEBUG_UART_DLL_204; + break; + case 340: + case 408: + div = DEBUG_UART_DLL_408; + break; + case 180: + case 216: + default: + break; + } + } uart[UART_LCR << DEBUG_UART_SHIFT] |= UART_LCR_DLAB; uart[UART_DLL << DEBUG_UART_SHIFT] = div & 0xff; |