diff options
| author | Gary King <gking@nvidia.com> | 2009-12-14 17:15:38 -0800 |
|---|---|---|
| committer | Gary King <gking@nvidia.com> | 2009-12-15 12:10:10 -0800 |
| commit | 24c17475126d7e59c1e178d55eb5b108ec1e18dd (patch) | |
| tree | 3896b7b3cfdf7e760754eceade3c7092caacbaf8 /arch/arm/mach-tegra/include/mach | |
| parent | e63beee3c98a1becfdfd398aabb3cfb796a45822 (diff) | |
networking: align network skid buffers to the L1 cache line for Tegra
Unaligned DMA accesses on NVIDIA Tegra SoCs cause 4B of data to be
written past the end of the buffer. Work-around is to align all skid buffers
to the cacheline
Change-Id: I57b885cc463d2621655c07064900d1c4921670a4
Diffstat (limited to 'arch/arm/mach-tegra/include/mach')
| -rw-r--r-- | arch/arm/mach-tegra/include/mach/memory.h | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/arch/arm/mach-tegra/include/mach/memory.h b/arch/arm/mach-tegra/include/mach/memory.h index 589cd6a9b86c..20043d3e9d8d 100644 --- a/arch/arm/mach-tegra/include/mach/memory.h +++ b/arch/arm/mach-tegra/include/mach/memory.h @@ -28,6 +28,14 @@ #error "Invalid Tegra SoC family selection" #endif +/* + * Unaligned DMA causes tegra dma to place data on 4-byte boundary after + * expected address. Call to skb_reserve(skb, NET_IP_ALIGN) was causing skb + * buffers in usbnet.c to become unaligned. + */ +#define NET_IP_ALIGN 0 +#define NET_SKB_PAD L1_CACHE_BYTES + /* bus address and physical addresses are identical */ #define __virt_to_bus(x) __virt_to_phys(x) #define __bus_to_virt(x) __phys_to_virt(x) |