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authorGary King <gking@nvidia.com>2010-02-26 16:23:33 -0800
committerGerrit Code Review <gerrit2@git-master-01.nvidia.com>2010-02-26 16:23:33 -0800
commit478bdc11006dd79e14d6943489f298f8a093321f (patch)
treeb6f3782815acb96fa77d210561e2324506081456 /arch/arm/mach-tegra/include
parent1a890b9dbd1193527a8c4ff277042024507aa962 (diff)
parent3c5f25f31edf3ae05052d69db18417d1908ac171 (diff)
Merge "tegra-w1: Add support read_bit, write_bit and touch_bit routines Change-Id: I313de2e32b1dd64470ce7eb9f21a60c590e689c6" into android-tegra-2.6.29
Diffstat (limited to 'arch/arm/mach-tegra/include')
-rwxr-xr-xarch/arm/mach-tegra/include/nvrm_owr.h9
1 files changed, 9 insertions, 0 deletions
diff --git a/arch/arm/mach-tegra/include/nvrm_owr.h b/arch/arm/mach-tegra/include/nvrm_owr.h
index c8af6f79c7a7..8aebb28e4ad0 100755
--- a/arch/arm/mach-tegra/include/nvrm_owr.h
+++ b/arch/arm/mach-tegra/include/nvrm_owr.h
@@ -108,6 +108,15 @@ typedef enum
/// OWR memory Check Presence
NvRmOwr_CheckPresence,
+
+ /// OWR readbit transaction.
+ /// The LSB will be received first.
+ NvRmOwr_ReadBit,
+
+ /// OWR writebit transaction.
+ /// The LSB will be transmitted first.
+ NvRmOwr_WriteBit,
+
NvRmOwrTransactionFlags_Num,
NvRmOwrTransactionFlags_Force32 = 0x7FFFFFFF
} NvRmOwrTransactionFlags;